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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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LIBRARY unisim;
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USE unisim.all;
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ARCHITECTURE xilinx OF clocks IS
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COMPONENT DCM
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generic
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(
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CLKDV_DIVIDE : real := 2.0;
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CLKFX_DIVIDE : integer := 1;
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CLKFX_MULTIPLY : integer := 4;
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CLKIN_DIVIDE_BY_2 : boolean := false;
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CLKIN_PERIOD : real := 10.0;
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CLKOUT_PHASE_SHIFT : string := "NONE";
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CLK_FEEDBACK : string := "1X";
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DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
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DFS_FREQUENCY_MODE : string := "LOW";
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DLL_FREQUENCY_MODE : string := "LOW";
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DSS_MODE : string := "NONE";
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DUTY_CYCLE_CORRECTION : boolean := true;
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FACTORY_JF : bit_vector := X"C080";
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PHASE_SHIFT : integer := 0;
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STARTUP_WAIT : boolean := false --non-simulatable
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);
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port
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(
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CLK0 : out std_ulogic := '0';
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CLK180 : out std_ulogic := '0';
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CLK270 : out std_ulogic := '0';
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CLK2X : out std_ulogic := '0';
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CLK2X180 : out std_ulogic := '0';
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CLK90 : out std_ulogic := '0';
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CLKDV : out std_ulogic := '0';
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CLKFX : out std_ulogic := '0';
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CLKFX180 : out std_ulogic := '0';
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LOCKED : out std_ulogic := '0';
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PSDONE : out std_ulogic := '0';
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STATUS : out std_logic_vector(7 downto 0) := "00000000";
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CLKFB : in std_ulogic := '0';
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CLKIN : in std_ulogic := '0';
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DSSEN : in std_ulogic := '0';
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PSCLK : in std_ulogic := '0';
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PSEN : in std_ulogic := '0';
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PSINCDEC : in std_ulogic := '0';
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RST : in std_ulogic := '0'
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);
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END COMPONENT;
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COMPONENT BUFG
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PORT ( I : IN std_logic;
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O : OUT std_logic );
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END COMPONENT;
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COMPONENT FD
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GENERIC ( INIT : bit );
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PORT( C : IN std_logic;
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D : IN std_logic;
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Q : OUT std_logic );
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END COMPONENT;
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SIGNAL s_user_clock_1_reset_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_user_clock_1_reset : std_logic;
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SIGNAL s_user_clock_1_out_ub : std_logic;
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SIGNAL s_user_clock_2_reset_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_user_clock_2_reset : std_logic;
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SIGNAL s_user_clock_2_out_ub : std_logic;
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SIGNAL s_lock_48_mul : std_logic;
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SIGNAL s_48MHz_mul : std_logic;
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SIGNAL s_mul_reset_count_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_clk_48_ubuf : std_logic;
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SIGNAL s_clk_96_ubuf : std_logic;
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SIGNAL s_clk_75_ubuf : std_logic;
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SIGNAL s_clk_48MHz : std_logic;
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SIGNAL s_clk_96MHz : std_logic;
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SIGNAL s_lock_48 : std_logic;
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SIGNAL s_reset_count_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_clock_div_reg : std_logic;
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SIGNAL s_msec_counter_reg : std_logic_vector(16 DOWNTO 0 );
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BEGIN
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--------------------------------------------------------------------------------
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--- Here some outputs are defined ---
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--------------------------------------------------------------------------------
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clk_48MHz <= s_clk_48MHz;
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clk_96MHz <= s_clk_96MHz;
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reset_out <= s_reset_count_reg(7);
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msec_tick <= s_msec_counter_reg(16);
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make_clock_div_reg : PROCESS( s_reset_count_reg , s_clk_96MHz )
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BEGIN
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IF (s_reset_count_reg(7) = '1') THEN s_clock_div_reg <= '0';
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ELSIF (s_clk_96MHz'event AND (s_clk_96MHz = '1')) THEN
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s_clock_div_reg <= NOT(s_clock_div_reg);
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END IF;
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END PROCESS make_clock_div_reg;
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clk48_ff : FD
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GENERIC MAP ( INIT => '0' )
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PORT MAP ( C => s_clk_96MHz,
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D => s_clock_div_reg,
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Q => clock_48MHz_out );
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make_msec_counter : PROCESS( s_clk_48MHz , s_reset_count_reg ,
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s_msec_counter_reg )
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BEGIN
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IF (s_reset_count_reg(7) = '1') THEN
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s_msec_counter_reg <= (OTHERS => '0');
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ELSIF (s_clk_48MHz'event AND (s_clk_48MHz = '1')) THEN
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IF (s_msec_counter_reg(16) = '1') THEN
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s_msec_counter_reg <= "0"&X"BB7E";
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ELSE
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s_msec_counter_reg <= unsigned(s_msec_counter_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_msec_counter;
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--------------------------------------------------------------------------------
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--- Here all internal FPGA signals are generated ---
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--------------------------------------------------------------------------------
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dcm3 : DCM
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GENERIC MAP ( CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 1,
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CLKFX_MULTIPLY => 3,
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CLKIN_DIVIDE_BY_2 => false,
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CLKIN_PERIOD => 62.5,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "NONE",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DSS_MODE => "NONE",
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DUTY_CYCLE_CORRECTION => true,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => false )
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PORT MAP ( CLK0 => OPEN,
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CLK180 => OPEN,
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CLK270 => OPEN,
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CLK2X => OPEN,
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CLK2X180 => OPEN,
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CLK90 => OPEN,
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CLKDV => OPEN,
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CLKFX => s_48MHz_mul,
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CLKFX180 => OPEN,
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LOCKED => s_lock_48_mul,
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PSDONE => OPEN,
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STATUS => OPEN,
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CLKFB => '0',
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CLKIN => clock_16MHz,
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DSSEN => '1',
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PSCLK => '0',
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PSEN => '0',
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PSINCDEC => '0',
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RST => '0');
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make_mul_reset_counter : PROCESS( s_48MHz_mul , s_lock_48_mul )
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BEGIN
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IF (s_lock_48_mul = '0') THEN s_mul_reset_count_reg <= (OTHERS => '1');
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ELSIF (s_48MHz_mul'event AND (s_48MHz_mul = '1')) THEN
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IF (s_mul_reset_count_reg(7) = '1') THEN
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s_mul_reset_count_reg <= unsigned(s_mul_reset_count_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_mul_reset_counter;
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dcm4 : DCM
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GENERIC MAP ( CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 16,
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CLKFX_MULTIPLY => 25,
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CLKIN_DIVIDE_BY_2 => false,
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CLKIN_PERIOD => 20.83,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DSS_MODE => "NONE",
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DUTY_CYCLE_CORRECTION => true,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => false )
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PORT MAP ( CLK0 => s_clk_48_ubuf,
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CLK180 => OPEN,
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CLK270 => OPEN,
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CLK2X => s_clk_96_ubuf,
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CLK2X180 => OPEN,
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CLK90 => OPEN,
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CLKDV => OPEN,
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CLKFX => s_clk_75_ubuf,
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CLKFX180 => OPEN,
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LOCKED => s_lock_48,
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PSDONE => OPEN,
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STATUS => OPEN,
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CLKFB => s_clk_48MHz,
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CLKIN => s_48MHz_mul,
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DSSEN => '1',
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PSCLK => '0',
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PSEN => '0',
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PSINCDEC => '0',
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RST => s_mul_reset_count_reg(7));
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buf3 : BUFG
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PORT MAP ( I => s_clk_48_ubuf,
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O => s_clk_48MHz );
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buf4 : BUFG
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PORT MAP ( I => s_clk_96_ubuf,
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O => s_clk_96MHz );
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buf5 : BUFG
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PORT MAP ( I => s_clk_75_ubuf,
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O => clk_75MHz );
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make_reset_count_reg : PROCESS( s_clk_48MHz , s_lock_48 )
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BEGIN
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IF (s_lock_48 = '0') THEN s_reset_count_reg <= (OTHERS => '1');
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ELSIF (s_clk_48MHz'event AND (s_clk_48MHz = '1')) THEN
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IF (s_reset_count_reg(7) = '1') THEN
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s_reset_count_reg <= unsigned(s_reset_count_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_reset_count_reg;
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--------------------------------------------------------------------------------
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--- Here the 25MHz is defined ---
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--------------------------------------------------------------------------------
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clock_25MHz_out <= NOT(clock_25MHz);
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--------------------------------------------------------------------------------
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--- Here the user clocks are defined ---
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--------------------------------------------------------------------------------
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make_user_clock_1_reset_reg : PROCESS( user_clock_1 , system_n_reset )
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BEGIN
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IF (system_n_reset = '0') THEN s_user_clock_1_reset_reg <= (OTHERS => '0');
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ELSIF (user_clock_1'event AND (user_clock_1 = '1')) THEN
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IF (s_user_clock_1_reset_reg(7) = '0') THEN
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s_user_clock_1_reset_reg <= unsigned(s_user_clock_1_reset_reg) + 1;
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END IF;
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END IF;
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END PROCESS make_user_clock_1_reset_reg;
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s_user_clock_1_reset <= NOT(s_user_clock_1_reset_reg(7));
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dcm1 : DCM
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GENERIC MAP ( CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 1,
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CLKFX_MULTIPLY => 3,
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| 277 |
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CLKIN_DIVIDE_BY_2 => false,
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| 278 |
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CLKIN_PERIOD => 10.0,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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| 281 |
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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| 282 |
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DFS_FREQUENCY_MODE => "LOW",
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| 283 |
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DLL_FREQUENCY_MODE => "LOW",
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| 284 |
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DSS_MODE => "NONE",
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| 285 |
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DUTY_CYCLE_CORRECTION => true,
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FACTORY_JF => X"C080",
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| 287 |
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PHASE_SHIFT => 0,
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| 288 |
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STARTUP_WAIT => false )
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PORT MAP ( CLK0 => s_user_clock_1_out_ub,
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CLK180 => OPEN,
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| 291 |
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CLK270 => OPEN,
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| 292 |
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CLK2X => OPEN,
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| 293 |
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CLK2X180 => OPEN,
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| 294 |
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CLK90 => OPEN,
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| 295 |
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CLKDV => OPEN,
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| 296 |
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CLKFX => OPEN,
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| 297 |
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CLKFX180 => OPEN,
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| 298 |
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LOCKED => user_clock_1_lock,
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| 299 |
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PSDONE => OPEN,
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STATUS => OPEN,
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CLKFB => user_clock_1_fb,
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| 302 |
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CLKIN => user_clock_1,
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DSSEN => '1',
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PSCLK => '0',
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| 305 |
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PSEN => '0',
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| 306 |
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PSINCDEC => '0',
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RST => s_user_clock_1_reset);
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buf1 : BUFG
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| 309 |
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PORT MAP ( I => s_user_clock_1_out_ub,
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| 310 |
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O => user_clock_1_out );
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| 311 |
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| 312 |
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make_user_clock_2_reset_reg : PROCESS( user_clock_2 , system_n_reset )
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| 313 |
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BEGIN
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| 314 |
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IF (system_n_reset = '0') THEN s_user_clock_2_reset_reg <= (OTHERS => '0');
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| 315 |
|
|
ELSIF (user_clock_2'event AND (user_clock_2 = '1')) THEN
|
| 316 |
|
|
IF (s_user_clock_2_reset_reg(7) = '0') THEN
|
| 317 |
|
|
s_user_clock_2_reset_reg <= unsigned(s_user_clock_2_reset_reg) + 1;
|
| 318 |
|
|
END IF;
|
| 319 |
|
|
END IF;
|
| 320 |
|
|
END PROCESS make_user_clock_2_reset_reg;
|
| 321 |
|
|
|
| 322 |
|
|
s_user_clock_2_reset <= NOT(s_user_clock_2_reset_reg(7));
|
| 323 |
|
|
|
| 324 |
|
|
dcm2 : DCM
|
| 325 |
|
|
GENERIC MAP ( CLKDV_DIVIDE => 2.0,
|
| 326 |
|
|
CLKFX_DIVIDE => 1,
|
| 327 |
|
|
CLKFX_MULTIPLY => 3,
|
| 328 |
|
|
CLKIN_DIVIDE_BY_2 => false,
|
| 329 |
|
|
CLKIN_PERIOD => 10.0,
|
| 330 |
|
|
CLKOUT_PHASE_SHIFT => "NONE",
|
| 331 |
|
|
CLK_FEEDBACK => "1X",
|
| 332 |
|
|
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
| 333 |
|
|
DFS_FREQUENCY_MODE => "LOW",
|
| 334 |
|
|
DLL_FREQUENCY_MODE => "LOW",
|
| 335 |
|
|
DSS_MODE => "NONE",
|
| 336 |
|
|
DUTY_CYCLE_CORRECTION => true,
|
| 337 |
|
|
FACTORY_JF => X"C080",
|
| 338 |
|
|
PHASE_SHIFT => 0,
|
| 339 |
|
|
STARTUP_WAIT => false )
|
| 340 |
|
|
PORT MAP ( CLK0 => s_user_clock_2_out_ub,
|
| 341 |
|
|
CLK180 => OPEN,
|
| 342 |
|
|
CLK270 => OPEN,
|
| 343 |
|
|
CLK2X => OPEN,
|
| 344 |
|
|
CLK2X180 => OPEN,
|
| 345 |
|
|
CLK90 => OPEN,
|
| 346 |
|
|
CLKDV => OPEN,
|
| 347 |
|
|
CLKFX => OPEN,
|
| 348 |
|
|
CLKFX180 => OPEN,
|
| 349 |
|
|
LOCKED => user_clock_2_lock,
|
| 350 |
|
|
PSDONE => OPEN,
|
| 351 |
|
|
STATUS => OPEN,
|
| 352 |
|
|
CLKFB => user_clock_2_fb,
|
| 353 |
|
|
CLKIN => user_clock_2,
|
| 354 |
|
|
DSSEN => '1',
|
| 355 |
|
|
PSCLK => '0',
|
| 356 |
|
|
PSEN => '0',
|
| 357 |
|
|
PSINCDEC => '0',
|
| 358 |
|
|
RST => s_user_clock_2_reset);
|
| 359 |
|
|
buf2 : BUFG
|
| 360 |
|
|
PORT MAP ( I => s_user_clock_2_out_ub,
|
| 361 |
|
|
O => user_clock_2_out );
|
| 362 |
|
|
END xilinx;
|
