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[/] [gecko4/] [trunk/] [GECKO4com/] [spartan200_an/] [vhdl/] [clockgen/] [clocks-behavior-xilinx.vhdl] - Blame information for rev 5

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1 5 ktt1
--------------------------------------------------------------------------------
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--            _   _            __   ____                                      --
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--           / / | |          / _| |  __|                                     --
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--           | |_| |  _   _  / /   | |_                                       --
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--           |  _  | | | | | | |   |  _|                                      --
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--           | | | | | |_| | \ \_  | |__                                      --
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--           |_| |_| \_____|  \__| |____| microLab                            --
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--                                                                            --
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--           Bern University of Applied Sciences (BFH)                        --
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--           Quellgasse 21                                                    --
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--           Room HG 4.33                                                     --
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--           2501 Biel/Bienne                                                 --
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--           Switzerland                                                      --
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--                                                                            --
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--           http://www.microlab.ch                                           --
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--------------------------------------------------------------------------------
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--   GECKO4com
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--  
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--   2010/2011 Dr. Theo Kluter
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--  
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--   This VHDL code is free code: you can redistribute it and/or modify
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--   it under the terms of the GNU General Public License as published by
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--   the Free Software Foundation, either version 3 of the License, or
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--   (at your option) any later version.
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--  
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--   This VHDL code is distributed in the hope that it will be useful,
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--   but WITHOUT ANY WARRANTY; without even the implied warranty of
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--   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--   GNU General Public License for more details. 
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--   You should have received a copy of the GNU General Public License
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--   along with these sources.  If not, see <http://www.gnu.org/licenses/>.
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--
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34
LIBRARY unisim;
35
USE unisim.all;
36
 
37
ARCHITECTURE xilinx OF clocks IS
38
 
39
   COMPONENT DCM
40
        generic
41
        (
42
                CLKDV_DIVIDE : real := 2.0;
43
                CLKFX_DIVIDE : integer := 1;
44
                CLKFX_MULTIPLY : integer := 4;
45
                CLKIN_DIVIDE_BY_2 : boolean := false;
46
                CLKIN_PERIOD : real := 10.0;
47
                CLKOUT_PHASE_SHIFT : string := "NONE";
48
                CLK_FEEDBACK : string := "1X";
49
                DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
50
                DFS_FREQUENCY_MODE : string := "LOW";
51
                DLL_FREQUENCY_MODE : string := "LOW";
52
                DSS_MODE : string := "NONE";
53
                DUTY_CYCLE_CORRECTION : boolean := true;
54
                FACTORY_JF : bit_vector := X"C080";
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                PHASE_SHIFT : integer := 0;
56
                STARTUP_WAIT : boolean := false                     --non-simulatable
57
        );
58
        port
59
        (
60
                CLK0 : out std_ulogic := '0';
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                CLK180 : out std_ulogic := '0';
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                CLK270 : out std_ulogic := '0';
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                CLK2X : out std_ulogic := '0';
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                CLK2X180 : out std_ulogic := '0';
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                CLK90 : out std_ulogic := '0';
66
                CLKDV : out std_ulogic := '0';
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                CLKFX : out std_ulogic := '0';
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                CLKFX180 : out std_ulogic := '0';
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                LOCKED : out std_ulogic := '0';
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                PSDONE : out std_ulogic := '0';
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                STATUS : out std_logic_vector(7 downto 0) := "00000000";
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                CLKFB : in std_ulogic := '0';
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                CLKIN : in std_ulogic := '0';
74
                DSSEN : in std_ulogic := '0';
75
                PSCLK : in std_ulogic := '0';
76
                PSEN : in std_ulogic := '0';
77
                PSINCDEC : in std_ulogic := '0';
78
                RST : in std_ulogic := '0'
79
        );
80
   END COMPONENT;
81
 
82
   COMPONENT BUFG
83
      PORT ( I  : IN  std_logic;
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             O  : OUT std_logic );
85
   END COMPONENT;
86
 
87
   COMPONENT FD
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      GENERIC ( INIT : bit );
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      PORT( C : IN  std_logic;
90
            D : IN  std_logic;
91
            Q : OUT std_logic );
92
   END COMPONENT;
93
 
94
   SIGNAL s_user_clock_1_reset_reg : std_logic_vector( 7 DOWNTO 0 );
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   SIGNAL s_user_clock_1_reset     : std_logic;
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   SIGNAL s_user_clock_1_out_ub    : std_logic;
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   SIGNAL s_user_clock_2_reset_reg : std_logic_vector( 7 DOWNTO 0 );
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   SIGNAL s_user_clock_2_reset     : std_logic;
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   SIGNAL s_user_clock_2_out_ub    : std_logic;
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   SIGNAL s_lock_48_mul            : std_logic;
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   SIGNAL s_48MHz_mul              : std_logic;
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   SIGNAL s_mul_reset_count_reg    : std_logic_vector( 7 DOWNTO 0 );
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   SIGNAL s_clk_48_ubuf            : std_logic;
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   SIGNAL s_clk_96_ubuf            : std_logic;
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   SIGNAL s_clk_75_ubuf            : std_logic;
106
   SIGNAL s_clk_48MHz              : std_logic;
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   SIGNAL s_clk_96MHz              : std_logic;
108
   SIGNAL s_lock_48                : std_logic;
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   SIGNAL s_reset_count_reg        : std_logic_vector( 7 DOWNTO 0 );
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   SIGNAL s_clock_div_reg          : std_logic;
111
   SIGNAL s_msec_counter_reg       : std_logic_vector(16 DOWNTO 0 );
112
 
113
BEGIN
114
--------------------------------------------------------------------------------
115
--- Here some outputs are defined                                            ---
116
--------------------------------------------------------------------------------
117
   clk_48MHz       <= s_clk_48MHz;
118
   clk_96MHz       <= s_clk_96MHz;
119
   reset_out       <= s_reset_count_reg(7);
120
   msec_tick       <= s_msec_counter_reg(16);
121
 
122
   make_clock_div_reg : PROCESS( s_reset_count_reg , s_clk_96MHz )
123
   BEGIN
124
      IF (s_reset_count_reg(7) = '1') THEN s_clock_div_reg <= '0';
125
      ELSIF (s_clk_96MHz'event AND (s_clk_96MHz = '1')) THEN
126
         s_clock_div_reg <= NOT(s_clock_div_reg);
127
      END IF;
128
   END PROCESS make_clock_div_reg;
129
 
130
   clk48_ff : FD
131
              GENERIC MAP ( INIT => '0' )
132
              PORT MAP ( C => s_clk_96MHz,
133
                         D => s_clock_div_reg,
134
                         Q => clock_48MHz_out );
135
 
136
   make_msec_counter : PROCESS( s_clk_48MHz , s_reset_count_reg ,
137
                                s_msec_counter_reg )
138
   BEGIN
139
      IF (s_reset_count_reg(7) = '1') THEN
140
         s_msec_counter_reg <= (OTHERS => '0');
141
      ELSIF (s_clk_48MHz'event AND (s_clk_48MHz = '1')) THEN
142
         IF (s_msec_counter_reg(16) = '1') THEN
143
            s_msec_counter_reg <= "0"&X"BB7E";
144
                                           ELSE
145
            s_msec_counter_reg <= unsigned(s_msec_counter_reg) - 1;
146
         END IF;
147
      END IF;
148
   END PROCESS make_msec_counter;
149
 
150
--------------------------------------------------------------------------------
151
--- Here all internal FPGA signals are generated                             ---
152
--------------------------------------------------------------------------------
153
   dcm3 : DCM
154
          GENERIC MAP (  CLKDV_DIVIDE          => 2.0,
155
                         CLKFX_DIVIDE          => 1,
156
                         CLKFX_MULTIPLY        => 3,
157
                         CLKIN_DIVIDE_BY_2     => false,
158
                         CLKIN_PERIOD          => 62.5,
159
                         CLKOUT_PHASE_SHIFT    => "NONE",
160
                         CLK_FEEDBACK          => "NONE",
161
                         DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
162
                         DFS_FREQUENCY_MODE    => "LOW",
163
                         DLL_FREQUENCY_MODE    => "LOW",
164
                         DSS_MODE              => "NONE",
165
                         DUTY_CYCLE_CORRECTION => true,
166
                         FACTORY_JF            => X"C080",
167
                         PHASE_SHIFT           => 0,
168
                         STARTUP_WAIT          => false )
169
               PORT MAP ( CLK0     => OPEN,
170
                     CLK180   => OPEN,
171
                     CLK270   => OPEN,
172
                     CLK2X    => OPEN,
173
                     CLK2X180 => OPEN,
174
                     CLK90    => OPEN,
175
                     CLKDV    => OPEN,
176
                     CLKFX    => s_48MHz_mul,
177
                     CLKFX180 => OPEN,
178
                     LOCKED   => s_lock_48_mul,
179
                     PSDONE   => OPEN,
180
                     STATUS   => OPEN,
181
                     CLKFB    => '0',
182
                     CLKIN    => clock_16MHz,
183
                     DSSEN    => '1',
184
                     PSCLK    => '0',
185
                     PSEN     => '0',
186
                     PSINCDEC => '0',
187
                     RST           => '0');
188
   make_mul_reset_counter : PROCESS( s_48MHz_mul , s_lock_48_mul )
189
   BEGIN
190
      IF (s_lock_48_mul = '0') THEN s_mul_reset_count_reg <= (OTHERS => '1');
191
      ELSIF (s_48MHz_mul'event AND (s_48MHz_mul = '1')) THEN
192
         IF (s_mul_reset_count_reg(7) = '1') THEN
193
            s_mul_reset_count_reg <= unsigned(s_mul_reset_count_reg) - 1;
194
         END IF;
195
      END IF;
196
   END PROCESS make_mul_reset_counter;
197
 
198
   dcm4 : DCM
199
          GENERIC MAP (  CLKDV_DIVIDE          => 2.0,
200
                         CLKFX_DIVIDE          => 16,
201
                         CLKFX_MULTIPLY        => 25,
202
                         CLKIN_DIVIDE_BY_2     => false,
203
                         CLKIN_PERIOD          => 20.83,
204
                         CLKOUT_PHASE_SHIFT    => "NONE",
205
                         CLK_FEEDBACK          => "1X",
206
                         DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
207
                         DFS_FREQUENCY_MODE    => "LOW",
208
                         DLL_FREQUENCY_MODE    => "LOW",
209
                         DSS_MODE              => "NONE",
210
                         DUTY_CYCLE_CORRECTION => true,
211
                         FACTORY_JF            => X"C080",
212
                         PHASE_SHIFT           => 0,
213
                         STARTUP_WAIT          => false )
214
               PORT MAP ( CLK0     => s_clk_48_ubuf,
215
                     CLK180   => OPEN,
216
                     CLK270   => OPEN,
217
                     CLK2X    => s_clk_96_ubuf,
218
                     CLK2X180 => OPEN,
219
                     CLK90    => OPEN,
220
                     CLKDV    => OPEN,
221
                     CLKFX    => s_clk_75_ubuf,
222
                     CLKFX180 => OPEN,
223
                     LOCKED   => s_lock_48,
224
                     PSDONE   => OPEN,
225
                     STATUS   => OPEN,
226
                     CLKFB    => s_clk_48MHz,
227
                     CLKIN    => s_48MHz_mul,
228
                     DSSEN    => '1',
229
                     PSCLK    => '0',
230
                     PSEN     => '0',
231
                     PSINCDEC => '0',
232
                     RST           => s_mul_reset_count_reg(7));
233
   buf3 : BUFG
234
          PORT MAP ( I => s_clk_48_ubuf,
235
                     O => s_clk_48MHz );
236
   buf4 : BUFG
237
          PORT MAP ( I => s_clk_96_ubuf,
238
                     O => s_clk_96MHz );
239
   buf5 : BUFG
240
          PORT MAP ( I => s_clk_75_ubuf,
241
                     O => clk_75MHz );
242
 
243
   make_reset_count_reg : PROCESS( s_clk_48MHz , s_lock_48 )
244
   BEGIN
245
      IF (s_lock_48 = '0') THEN s_reset_count_reg <= (OTHERS => '1');
246
      ELSIF (s_clk_48MHz'event AND (s_clk_48MHz = '1')) THEN
247
         IF (s_reset_count_reg(7) = '1') THEN
248
            s_reset_count_reg <= unsigned(s_reset_count_reg) - 1;
249
         END IF;
250
      END IF;
251
   END PROCESS make_reset_count_reg;
252
 
253
--------------------------------------------------------------------------------
254
--- Here the 25MHz is defined                                                ---
255
--------------------------------------------------------------------------------
256
   clock_25MHz_out <= NOT(clock_25MHz);
257
 
258
--------------------------------------------------------------------------------
259
--- Here the user clocks are defined                                         ---
260
--------------------------------------------------------------------------------
261
   make_user_clock_1_reset_reg : PROCESS( user_clock_1 , system_n_reset )
262
   BEGIN
263
      IF (system_n_reset = '0') THEN s_user_clock_1_reset_reg <= (OTHERS => '0');
264
      ELSIF (user_clock_1'event AND (user_clock_1 = '1')) THEN
265
         IF (s_user_clock_1_reset_reg(7) = '0') THEN
266
            s_user_clock_1_reset_reg <= unsigned(s_user_clock_1_reset_reg) + 1;
267
         END IF;
268
      END IF;
269
   END PROCESS make_user_clock_1_reset_reg;
270
 
271
   s_user_clock_1_reset <= NOT(s_user_clock_1_reset_reg(7));
272
 
273
   dcm1 : DCM
274
          GENERIC MAP (  CLKDV_DIVIDE          => 2.0,
275
                         CLKFX_DIVIDE          => 1,
276
                         CLKFX_MULTIPLY        => 3,
277
                         CLKIN_DIVIDE_BY_2     => false,
278
                         CLKIN_PERIOD          => 10.0,
279
                         CLKOUT_PHASE_SHIFT    => "NONE",
280
                         CLK_FEEDBACK          => "1X",
281
                         DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
282
                         DFS_FREQUENCY_MODE    => "LOW",
283
                         DLL_FREQUENCY_MODE    => "LOW",
284
                         DSS_MODE              => "NONE",
285
                         DUTY_CYCLE_CORRECTION => true,
286
                         FACTORY_JF            => X"C080",
287
                         PHASE_SHIFT           => 0,
288
                         STARTUP_WAIT          => false )
289
               PORT MAP ( CLK0     => s_user_clock_1_out_ub,
290
                     CLK180   => OPEN,
291
                     CLK270   => OPEN,
292
                     CLK2X    => OPEN,
293
                     CLK2X180 => OPEN,
294
                     CLK90    => OPEN,
295
                     CLKDV    => OPEN,
296
                     CLKFX    => OPEN,
297
                     CLKFX180 => OPEN,
298
                     LOCKED   => user_clock_1_lock,
299
                     PSDONE   => OPEN,
300
                     STATUS   => OPEN,
301
                     CLKFB    => user_clock_1_fb,
302
                     CLKIN    => user_clock_1,
303
                     DSSEN    => '1',
304
                     PSCLK    => '0',
305
                     PSEN     => '0',
306
                     PSINCDEC => '0',
307
                     RST           => s_user_clock_1_reset);
308
   buf1 : BUFG
309
          PORT MAP ( I  => s_user_clock_1_out_ub,
310
                     O  => user_clock_1_out );
311
 
312
   make_user_clock_2_reset_reg : PROCESS( user_clock_2 , system_n_reset )
313
   BEGIN
314
      IF (system_n_reset = '0') THEN s_user_clock_2_reset_reg <= (OTHERS => '0');
315
      ELSIF (user_clock_2'event AND (user_clock_2 = '1')) THEN
316
         IF (s_user_clock_2_reset_reg(7) = '0') THEN
317
            s_user_clock_2_reset_reg <= unsigned(s_user_clock_2_reset_reg) + 1;
318
         END IF;
319
      END IF;
320
   END PROCESS make_user_clock_2_reset_reg;
321
 
322
   s_user_clock_2_reset <= NOT(s_user_clock_2_reset_reg(7));
323
 
324
   dcm2 : DCM
325
          GENERIC MAP (  CLKDV_DIVIDE          => 2.0,
326
                         CLKFX_DIVIDE          => 1,
327
                         CLKFX_MULTIPLY        => 3,
328
                         CLKIN_DIVIDE_BY_2     => false,
329
                         CLKIN_PERIOD          => 10.0,
330
                         CLKOUT_PHASE_SHIFT    => "NONE",
331
                         CLK_FEEDBACK          => "1X",
332
                         DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
333
                         DFS_FREQUENCY_MODE    => "LOW",
334
                         DLL_FREQUENCY_MODE    => "LOW",
335
                         DSS_MODE              => "NONE",
336
                         DUTY_CYCLE_CORRECTION => true,
337
                         FACTORY_JF            => X"C080",
338
                         PHASE_SHIFT           => 0,
339
                         STARTUP_WAIT          => false )
340
               PORT MAP ( CLK0     => s_user_clock_2_out_ub,
341
                     CLK180   => OPEN,
342
                     CLK270   => OPEN,
343
                     CLK2X    => OPEN,
344
                     CLK2X180 => OPEN,
345
                     CLK90    => OPEN,
346
                     CLKDV    => OPEN,
347
                     CLKFX    => OPEN,
348
                     CLKFX180 => OPEN,
349
                     LOCKED   => user_clock_2_lock,
350
                     PSDONE   => OPEN,
351
                     STATUS   => OPEN,
352
                     CLKFB    => user_clock_2_fb,
353
                     CLKIN    => user_clock_2,
354
                     DSSEN    => '1',
355
                     PSCLK    => '0',
356
                     PSEN     => '0',
357
                     PSINCDEC => '0',
358
                     RST           => s_user_clock_2_reset);
359
   buf2 : BUFG
360
          PORT MAP ( I  => s_user_clock_2_out_ub,
361
                     O  => user_clock_2_out );
362
END xilinx;

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