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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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ARCHITECTURE no_platform_specific OF hexswitch IS
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TYPE HEX_STATE_TYPE IS ( IDLE , SEND_SIZE , SEND_VALUE , SEND_END , GET_VALUE ,
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SIGNAL_DONE , SIGNAL_ERROR );
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SIGNAL s_override_reg : std_logic;
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SIGNAL s_hexswitch_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_hex_state_reg : HEX_STATE_TYPE;
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SIGNAL s_push : std_logic;
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SIGNAL s_fetched_value : std_logic_vector( 4 DOWNTO 0 );
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SIGNAL s_pop : std_logic;
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SIGNAL s_update : std_logic;
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BEGIN
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--------------------------------------------------------------------------------
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--- Here the outputs are defined ---
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--------------------------------------------------------------------------------
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hex_value <= s_hexswitch_reg;
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done <= '1' WHEN s_hex_state_reg = SIGNAL_DONE ELSE '0';
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command_error <= '1' WHEN s_hex_state_reg = SIGNAL_ERROR ELSE '0';
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push_size <= '1' WHEN s_hex_state_reg = SEND_SIZE ELSE '0';
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push <= s_push;
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pop <= s_pop;
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make_push_data : PROCESS( s_hex_state_reg , s_hexswitch_reg )
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BEGIN
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CASE (s_hex_state_reg) IS
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WHEN SEND_SIZE => push_data <= X"02";
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WHEN SEND_VALUE => CASE (s_hexswitch_reg) IS
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WHEN X"0" => push_data <= X"30";
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WHEN X"1" => push_data <= X"31";
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WHEN X"2" => push_data <= X"32";
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WHEN X"3" => push_data <= X"33";
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WHEN X"4" => push_data <= X"34";
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WHEN X"5" => push_data <= X"35";
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WHEN X"6" => push_data <= X"36";
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WHEN X"7" => push_data <= X"37";
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WHEN X"8" => push_data <= X"38";
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WHEN X"9" => push_data <= X"39";
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WHEN X"A" => push_data <= X"41";
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WHEN X"B" => push_data <= X"42";
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WHEN X"C" => push_data <= X"43";
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WHEN X"D" => push_data <= X"44";
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WHEN X"E" => push_data <= X"45";
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WHEN OTHERS => push_data <= X"46";
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END CASE;
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WHEN SEND_END => push_data <= X"0A";
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WHEN OTHERS => push_data <= X"00";
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END CASE;
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END PROCESS make_push_data;
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--------------------------------------------------------------------------------
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--- Here the control signals are defined ---
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--------------------------------------------------------------------------------
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s_push <= '1' WHEN push_full = '0' AND
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(s_hex_state_reg = SEND_SIZE OR
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s_hex_state_reg = SEND_VALUE OR
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s_hex_state_reg = SEND_END) ELSE '0';
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s_pop <= '1' WHEN pop_empty = '0' AND
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s_hex_state_reg = GET_VALUE ELSE '0';
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s_update <= s_pop AND s_fetched_value(4);
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make_fetched_value : PROCESS( pop_data )
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BEGIN
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CASE (pop_data) IS
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WHEN X"30" => s_fetched_value <= "1"&X"0";
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WHEN X"31" => s_fetched_value <= "1"&X"1";
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WHEN X"32" => s_fetched_value <= "1"&X"2";
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WHEN X"33" => s_fetched_value <= "1"&X"3";
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WHEN X"34" => s_fetched_value <= "1"&X"4";
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WHEN X"35" => s_fetched_value <= "1"&X"5";
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WHEN X"36" => s_fetched_value <= "1"&X"6";
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WHEN X"37" => s_fetched_value <= "1"&X"7";
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WHEN X"38" => s_fetched_value <= "1"&X"8";
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WHEN X"39" => s_fetched_value <= "1"&X"9";
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WHEN X"41" => s_fetched_value <= "1"&X"A";
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WHEN X"42" => s_fetched_value <= "1"&X"B";
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WHEN X"43" => s_fetched_value <= "1"&X"C";
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WHEN X"44" => s_fetched_value <= "1"&X"D";
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WHEN X"45" => s_fetched_value <= "1"&X"E";
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WHEN X"46" => s_fetched_value <= "1"&X"F";
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WHEN X"61" => s_fetched_value <= "1"&X"A";
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WHEN X"62" => s_fetched_value <= "1"&X"B";
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WHEN X"63" => s_fetched_value <= "1"&X"C";
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WHEN X"64" => s_fetched_value <= "1"&X"D";
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WHEN X"65" => s_fetched_value <= "1"&X"E";
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WHEN X"66" => s_fetched_value <= "1"&X"F";
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WHEN OTHERS => s_fetched_value <= "0"&X"0";
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END CASE;
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END PROCESS make_fetched_value;
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--------------------------------------------------------------------------------
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--- Here the state machine is defined ---
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--------------------------------------------------------------------------------
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make_state_machine : PROCESS( clock , reset , s_hex_state_reg , start ,
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command , s_push )
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VARIABLE v_next_state : HEX_STATE_TYPE;
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BEGIN
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CASE (s_hex_state_reg) IS
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WHEN IDLE => IF (start = '1') THEN
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CASE (command) IS
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WHEN "0100011" => v_next_state := GET_VALUE;
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WHEN "0100100" => v_next_state := SEND_SIZE;
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WHEN OTHERS => v_next_state := IDLE;
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END CASE;
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ELSE
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v_next_state := IDLE;
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END IF;
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WHEN SEND_SIZE => IF (s_push = '1') THEN
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v_next_state := SEND_VALUE;
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ELSE
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v_next_state := SEND_SIZE;
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END IF;
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WHEN SEND_VALUE => IF (s_push = '1') THEN
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v_next_state := SEND_END;
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ELSE
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v_next_state := SEND_VALUE;
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END IF;
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WHEN SEND_END => IF (s_push = '1') THEN
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v_next_state := SIGNAL_DONE;
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ELSE
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v_next_state := SEND_END;
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END IF;
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WHEN GET_VALUE => IF (s_pop = '1') THEN
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IF (s_fetched_value(4) = '1') THEN
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v_next_state := SIGNAL_DONE;
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ELSIF (pop_data = X"20" AND
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pop_last = '0') THEN
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v_next_state := GET_VALUE;
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ELSE
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v_next_state := SIGNAL_ERROR;
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END IF;
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ELSE
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v_next_state := GET_VALUE;
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END IF;
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WHEN OTHERS => v_next_state := IDLE;
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END CASE;
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_hex_state_reg <= IDLE;
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ELSE s_hex_state_reg <= v_next_state;
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END IF;
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END IF;
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END PROCESS make_state_machine;
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--------------------------------------------------------------------------------
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--- Here the base registers are defined ---
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--------------------------------------------------------------------------------
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make_override_reg : PROCESS( clock , reset )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_override_reg <= '0';
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ELSIF (s_update = '1') THEN s_override_reg <= '1';
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END IF;
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END IF;
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END PROCESS make_override_reg;
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make_hexswitch_reg : PROCESS( clock , s_override_reg , n_hex_sw )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_update = '1') THEN
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s_hexswitch_reg <= s_fetched_value( 3 DOWNTO 0 );
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ELSIF (s_override_reg = '0') THEN s_hexswitch_reg <= NOT(n_hex_sw);
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END IF;
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END IF;
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END PROCESS make_hexswitch_reg;
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END no_platform_specific;
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