| 1 |
5 |
ktt1 |
--------------------------------------------------------------------------------
|
| 2 |
|
|
-- _ _ __ ____ --
|
| 3 |
|
|
-- / / | | / _| | __| --
|
| 4 |
|
|
-- | |_| | _ _ / / | |_ --
|
| 5 |
|
|
-- | _ | | | | | | | | _| --
|
| 6 |
|
|
-- | | | | | |_| | \ \_ | |__ --
|
| 7 |
|
|
-- |_| |_| \_____| \__| |____| microLab --
|
| 8 |
|
|
-- --
|
| 9 |
|
|
-- Bern University of Applied Sciences (BFH) --
|
| 10 |
|
|
-- Quellgasse 21 --
|
| 11 |
|
|
-- Room HG 4.33 --
|
| 12 |
|
|
-- 2501 Biel/Bienne --
|
| 13 |
|
|
-- Switzerland --
|
| 14 |
|
|
-- --
|
| 15 |
|
|
-- http://www.microlab.ch --
|
| 16 |
|
|
--------------------------------------------------------------------------------
|
| 17 |
|
|
-- GECKO4com
|
| 18 |
|
|
--
|
| 19 |
|
|
-- 2010/2011 Dr. Theo Kluter
|
| 20 |
|
|
--
|
| 21 |
|
|
-- This VHDL code is free code: you can redistribute it and/or modify
|
| 22 |
|
|
-- it under the terms of the GNU General Public License as published by
|
| 23 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
| 24 |
|
|
-- (at your option) any later version.
|
| 25 |
|
|
--
|
| 26 |
|
|
-- This VHDL code is distributed in the hope that it will be useful,
|
| 27 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 28 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 29 |
|
|
-- GNU General Public License for more details.
|
| 30 |
|
|
-- You should have received a copy of the GNU General Public License
|
| 31 |
|
|
-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
|
| 32 |
|
|
--
|
| 33 |
|
|
|
| 34 |
|
|
ARCHITECTURE no_platform_specific OF identify_handler IS
|
| 35 |
|
|
|
| 36 |
|
|
SIGNAL s_real_start : std_logic;
|
| 37 |
|
|
SIGNAL s_active_reg : std_logic;
|
| 38 |
|
|
SIGNAL s_down_count_reg : std_logic_vector( 5 DOWNTO 0 );
|
| 39 |
|
|
SIGNAL s_shift_tick : std_logic;
|
| 40 |
|
|
SIGNAL s_shift_dir_reg : std_logic;
|
| 41 |
|
|
SIGNAL s_shift_a_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 42 |
|
|
SIGNAL s_shift_k_reg : std_logic_vector( 8 DOWNTO 0 );
|
| 43 |
|
|
SIGNAL s_stop : std_logic;
|
| 44 |
|
|
|
| 45 |
|
|
BEGIN
|
| 46 |
|
|
-- Assign outputs
|
| 47 |
|
|
done <= s_stop;
|
| 48 |
|
|
leds_a <= X"80" WHEN flash_idle = '0' ELSE
|
| 49 |
|
|
s_shift_a_reg WHEN s_active_reg = '1' ELSE leds_a_in;
|
| 50 |
|
|
leds_k <= (OTHERS => '0') WHEN flash_idle = '0' ELSE
|
| 51 |
|
|
s_shift_k_reg(8 DOWNTO 1) WHEN s_active_reg = '1' ELSE leds_k_in;
|
| 52 |
|
|
|
| 53 |
|
|
-- Assign control signals
|
| 54 |
|
|
s_real_start <= '1' WHEN (start = '1' AND command = "0100101") OR
|
| 55 |
|
|
indicator = '1' ELSE '0';
|
| 56 |
|
|
s_shift_tick <= '1' WHEN msec_tick = '1' AND
|
| 57 |
|
|
s_down_count_reg = "000000" ELSE '0';
|
| 58 |
|
|
s_stop <= '1' WHEN s_shift_tick = '1' AND
|
| 59 |
|
|
s_shift_k_reg(1) = '0' AND
|
| 60 |
|
|
s_shift_k_reg(0) = '1' ELSE '0';
|
| 61 |
|
|
|
| 62 |
|
|
-- make processes
|
| 63 |
|
|
make_active_reg : PROCESS( clock , reset , s_real_start , s_stop )
|
| 64 |
|
|
BEGIN
|
| 65 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 66 |
|
|
IF (reset = '1' OR
|
| 67 |
|
|
s_stop = '1') THEN s_active_reg <= '0';
|
| 68 |
|
|
ELSIF (s_real_start = '1') THEN s_active_reg <= '1';
|
| 69 |
|
|
END IF;
|
| 70 |
|
|
END IF;
|
| 71 |
|
|
END PROCESS make_active_reg;
|
| 72 |
|
|
|
| 73 |
|
|
make_shift_dir_reg : PROCESS( clock , s_active_reg , s_shift_a_reg )
|
| 74 |
|
|
BEGIN
|
| 75 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 76 |
|
|
IF (s_active_reg = '0') THEN s_shift_dir_reg <= '1';
|
| 77 |
|
|
ELSIF (s_shift_a_reg(7) = '1') THEN s_shift_dir_reg <= '0';
|
| 78 |
|
|
END IF;
|
| 79 |
|
|
END IF;
|
| 80 |
|
|
END PROCESS make_shift_dir_reg;
|
| 81 |
|
|
|
| 82 |
|
|
make_shift_a_reg : PROCESS( clock , s_active_reg , s_shift_dir_reg ,
|
| 83 |
|
|
s_shift_tick )
|
| 84 |
|
|
BEGIN
|
| 85 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 86 |
|
|
IF (s_active_reg = '0') THEN s_shift_a_reg <= (OTHERS => '0');
|
| 87 |
|
|
ELSIF (s_shift_tick = '1') THEN
|
| 88 |
|
|
IF (s_shift_dir_reg = '1') THEN
|
| 89 |
|
|
s_shift_a_reg <= s_shift_a_reg(6 DOWNTO 0)&'1';
|
| 90 |
|
|
ELSE
|
| 91 |
|
|
s_shift_a_reg <= '0'&s_shift_a_reg(7 DOWNTO 1);
|
| 92 |
|
|
END IF;
|
| 93 |
|
|
END IF;
|
| 94 |
|
|
END IF;
|
| 95 |
|
|
END PROCESS make_shift_a_reg;
|
| 96 |
|
|
|
| 97 |
|
|
make_shift_k_reg : PROCESS( clock , s_active_reg , s_shift_dir_reg ,
|
| 98 |
|
|
s_shift_tick , s_shift_a_reg )
|
| 99 |
|
|
BEGIN
|
| 100 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 101 |
|
|
IF (s_active_reg = '0') THEN s_shift_k_reg <= (OTHERS => '0');
|
| 102 |
|
|
ELSIF (s_shift_tick = '1' AND s_shift_dir_reg = '0') THEN
|
| 103 |
|
|
s_shift_k_reg <= s_shift_a_reg(0)&s_shift_k_reg(8 DOWNTO 1);
|
| 104 |
|
|
END IF;
|
| 105 |
|
|
END IF;
|
| 106 |
|
|
END PROCESS make_shift_k_reg;
|
| 107 |
|
|
|
| 108 |
|
|
make_down_count_reg : PROCESS( clock , reset , s_active_reg ,
|
| 109 |
|
|
msec_tick , s_shift_tick )
|
| 110 |
|
|
BEGIN
|
| 111 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 112 |
|
|
IF (s_shift_tick = '1' OR
|
| 113 |
|
|
(s_active_reg = '0' AND
|
| 114 |
|
|
flash_idle = '1') OR
|
| 115 |
|
|
reset = '1') THEN s_down_count_reg <= "100111";
|
| 116 |
|
|
ELSIF (msec_tick = '1') THEN
|
| 117 |
|
|
s_down_count_reg <= unsigned(s_down_count_reg) - 1;
|
| 118 |
|
|
END IF;
|
| 119 |
|
|
END IF;
|
| 120 |
|
|
END PROCESS make_down_count_reg;
|
| 121 |
|
|
|
| 122 |
|
|
END no_platform_specific;
|
