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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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ARCHITECTURE no_platform_specific OF bitfile_interpreter IS
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TYPE INTERPRETER_STATES IS (IDLE , SIGNAL_DONE , INIT_GET_LENGTH , GET_LENGTH ,
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MAKE_FIELD_DESC , INIT_DUMMY_READ , DUMMY_READ ,
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GET_FIELD_CHAR , UPDATE_FIELD_ID ,
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CHECK_FIELD_CHAR , FLUSH_FIFO , INIT_GET_B_LENGTH ,
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GET_B_LENGTH , CHECK_B_LENGTH , INIT_WRITE_STR ,
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WRITE_STR , COPY_BITSTREAM , SIGNAL_ERROR ,
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EXECUTE_FLUSH_FIFO );
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TYPE FIELD_TYPES IS (FIELD_1,FIELD_2,FIELD_3,FIELD_4,FIELD_5,FIELD_6,
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FIELD_7,RAW_DATA,HEADER_ERROR);
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SIGNAL s_interpreter_state_reg : INTERPRETER_STATES;
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SIGNAL s_current_field_reg : FIELD_TYPES;
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SIGNAL s_down_counter_reg : std_logic_vector( 16 DOWNTO 0 );
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SIGNAL s_down_counter_load : std_logic;
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SIGNAL s_down_counter_ena : std_logic;
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SIGNAL s_down_counter_load_value : std_logic_vector( 16 DOWNTO 0 );
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SIGNAL s_field_length_reg : std_logic_vector( 15 DOWNTO 0 );
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SIGNAL s_pop_a_byte : std_logic;
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SIGNAL s_data_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_ena_data_reg : std_logic;
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SIGNAL s_we_char_reg : std_logic;
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SIGNAL s_bitstream_length_reg : std_logic_vector( 31 DOWNTO 0 );
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SIGNAL s_push_reg : std_logic;
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SIGNAL s_bitstream_count_reg : std_logic_vector( 32 DOWNTO 0 );
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SIGNAL s_bitstream_count_next : std_logic_vector( 32 DOWNTO 0 );
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SIGNAL s_bitstream_count_ena : std_logic;
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SIGNAL s_error_reg : std_logic;
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SIGNAL s_watchdog_timer_reg : std_logic_vector( 11 DOWNTO 0 );
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SIGNAL s_bitstream_size_reg : std_logic_vector( 31 DOWNTO 0 );
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SIGNAL s_write_flash_reg : std_logic;
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BEGIN
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--------------------------------------------------------------------------------
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--- Here the outputs are defined ---
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--------------------------------------------------------------------------------
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pop <= s_pop_a_byte;
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done <= '1' WHEN s_interpreter_state_reg = SIGNAL_DONE ELSE '0';
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ascii_data <= s_data_reg WHEN s_we_char_reg = '1' ELSE (OTHERS => '0');
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we_char <= s_we_char_reg;
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push <= s_push_reg AND NOT(s_write_flash_reg);
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push_data <= s_data_reg WHEN s_push_reg = '1' ELSE (OTHERS => '0');
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last_byte <= s_bitstream_count_reg(32);
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error_detected <= s_error_reg WHEN s_interpreter_state_reg = SIGNAL_DONE ELSE '0';
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reset_fpga_if <= reset OR s_error_reg;
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bitfile_size <= s_bitstream_size_reg;
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we_data <= s_data_reg;
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we_fifo <= s_push_reg AND s_write_flash_reg;
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we_last <= s_bitstream_count_reg(32) WHEN
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s_interpreter_state_reg = COPY_BITSTREAM ELSE '0';
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start_write <= '1' WHEN s_interpreter_state_reg = CHECK_B_LENGTH AND
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s_write_flash_reg = '1' ELSE '0';
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--------------------------------------------------------------------------------
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--- Here the control signals are defined ---
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--------------------------------------------------------------------------------
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s_pop_a_byte <= '1' WHEN
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((s_interpreter_state_reg = GET_LENGTH OR
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s_interpreter_state_reg = DUMMY_READ OR
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s_interpreter_state_reg = WRITE_STR OR
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s_interpreter_state_reg = GET_B_LENGTH) AND
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fifo_empty = '0' AND
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we_fifo_full = '0' AND
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s_down_counter_reg(16) = '0') OR
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(s_interpreter_state_reg = GET_FIELD_CHAR AND
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fifo_empty = '0' AND
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we_fifo_full = '0') OR
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(s_interpreter_state_reg = COPY_BITSTREAM AND
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fifo_empty = '0' AND
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fifo_full = '0' AND
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we_fifo_full = '0' AND
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s_bitstream_count_reg(32) = '0') OR
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(s_interpreter_state_reg = EXECUTE_FLUSH_FIFO AND
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fifo_empty = '0' AND
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s_bitstream_count_reg(32) = '0')
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ELSE '0';
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--------------------------------------------------------------------------------
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--- Here the intermediate data buffer is defined ---
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--------------------------------------------------------------------------------
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s_ena_data_reg <= s_pop_a_byte;
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make_data_reg : PROCESS( clock , reset , s_ena_data_reg , pop_data )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_data_reg <= X"FF";
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ELSIF (s_ena_data_reg = '1') THEN s_data_reg <= pop_data;
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END IF;
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END IF;
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END PROCESS make_data_reg;
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make_we_char : PROCESS( clock , s_interpreter_state_reg , s_pop_a_byte )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_interpreter_state_reg = WRITE_STR) THEN
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s_we_char_reg <= s_pop_a_byte;
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ELSE
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s_we_char_reg <= '0';
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END IF;
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END IF;
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END PROCESS make_we_char;
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make_push_reg : PROCESS( clock , s_interpreter_state_reg , s_pop_a_byte )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_interpreter_state_reg = COPY_BITSTREAM OR
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(s_interpreter_state_reg /= EXECUTE_FLUSH_FIFO AND
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s_write_flash_reg = '1')) THEN
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s_push_reg <= s_pop_a_byte;
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ELSE
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s_push_reg <= '0';
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END IF;
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END IF;
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END PROCESS make_push_reg;
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--------------------------------------------------------------------------------
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--- Here the general purpose down counter is defined ---
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--------------------------------------------------------------------------------
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s_down_counter_load <= '1' WHEN
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s_interpreter_state_reg = INIT_GET_LENGTH OR
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s_interpreter_state_reg = INIT_DUMMY_READ OR
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s_interpreter_state_reg = INIT_WRITE_STR OR
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s_interpreter_state_reg = INIT_GET_B_LENGTH
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ELSE '0';
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s_down_counter_ena <= '1' WHEN
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((s_interpreter_state_reg = GET_LENGTH OR
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s_interpreter_state_reg = DUMMY_READ OR
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s_interpreter_state_reg = WRITE_STR OR
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s_interpreter_state_reg = GET_B_LENGTH) AND
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s_pop_a_byte = '1')
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ELSE '0';
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make_down_counter_load_value : PROCESS( s_interpreter_state_reg ,
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s_field_length_reg )
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VARIABLE v_length : std_logic_vector( 16 DOWNTO 0 );
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BEGIN
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CASE (s_interpreter_state_reg) IS
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WHEN INIT_GET_LENGTH => s_down_counter_load_value <= "0"&X"0001";
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WHEN INIT_GET_B_LENGTH => s_down_counter_load_value <= "0"&X"0003";
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WHEN OTHERS => v_length := "0"&s_field_length_reg;
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s_down_counter_load_value <=
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unsigned(v_length) - 1;
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END CASE;
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END PROCESS make_down_counter_load_value;
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make_down_counter : PROCESS( clock , s_down_counter_reg ,
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s_down_counter_load , s_down_counter_ena ,
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s_down_counter_load_value )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_down_counter_load = '1') THEN
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s_down_counter_reg <= s_down_counter_load_value;
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ELSIF (s_down_counter_ena = '1') THEN
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s_down_counter_reg <= unsigned(s_down_counter_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_down_counter;
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--------------------------------------------------------------------------------
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--- Here the field length reg is defined ---
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--------------------------------------------------------------------------------
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make_field_reg : PROCESS( clock , reset , s_interpreter_state_reg , pop_data ,
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s_down_counter_reg , s_pop_a_byte )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_field_length_reg <= (OTHERS => '0');
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ELSIF (s_interpreter_state_reg = GET_LENGTH AND
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s_pop_a_byte = '1') THEN
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IF (s_down_counter_reg(0) = '1') THEN
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s_field_length_reg(15 DOWNTO 8) <= pop_data;
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ELSE
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s_field_length_reg( 7 DOWNTO 0) <= pop_data;
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END IF;
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END IF;
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END IF;
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END PROCESS make_field_reg;
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--------------------------------------------------------------------------------
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--- Here the state machine is defined ---
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--------------------------------------------------------------------------------
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make_state_machine : PROCESS( clock , reset , s_interpreter_state_reg ,
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start , s_down_counter_reg ,
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s_current_field_reg ,
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s_bitstream_count_reg , s_watchdog_timer_reg )
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VARIABLE v_next_state : INTERPRETER_STATES;
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BEGIN
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CASE (s_interpreter_state_reg) IS
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WHEN IDLE => IF (start = '1') THEN
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v_next_state := INIT_GET_LENGTH;
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ELSE
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v_next_state := IDLE;
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END IF;
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WHEN INIT_GET_LENGTH => v_next_state := GET_LENGTH;
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WHEN GET_LENGTH => IF (s_down_counter_reg(16) = '1') THEN
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v_next_state := MAKE_FIELD_DESC;
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ELSE
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v_next_state := GET_LENGTH;
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END IF;
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WHEN MAKE_FIELD_DESC => CASE (s_current_field_reg) IS
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WHEN FIELD_1 => v_next_state := INIT_DUMMY_READ;
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WHEN FIELD_2 => v_next_state := GET_FIELD_CHAR;
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WHEN FIELD_3 |
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FIELD_4 |
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FIELD_5 |
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FIELD_6 => v_next_state := INIT_WRITE_STR;
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WHEN OTHERS => v_next_state := FLUSH_FIFO;
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END CASE;
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WHEN INIT_DUMMY_READ => v_next_state := DUMMY_READ;
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WHEN DUMMY_READ => IF (s_down_counter_reg(16) = '1') THEN
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v_next_state := INIT_GET_LENGTH;
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ELSE
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v_next_state := DUMMY_READ;
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END IF;
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WHEN GET_FIELD_CHAR => IF (s_pop_a_byte = '1') THEN
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v_next_state := UPDATE_FIELD_ID;
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ELSE
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v_next_state := GET_FIELD_CHAR;
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END IF;
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WHEN UPDATE_FIELD_ID => v_next_state := CHECK_FIELD_CHAR;
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WHEN CHECK_FIELD_CHAR => CASE (s_current_field_reg) IS
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WHEN HEADER_ERROR => v_next_state := FLUSH_FIFO;
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WHEN FIELD_7 => v_next_state := INIT_GET_B_LENGTH;
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WHEN OTHERS => v_next_state := INIT_GET_LENGTH;
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END CASE;
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WHEN INIT_GET_B_LENGTH => v_next_state := GET_B_LENGTH;
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WHEN GET_B_LENGTH => IF(s_down_counter_reg(16) = '1') THEN
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v_next_state := CHECK_B_LENGTH;
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ELSE
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v_next_state := GET_B_LENGTH;
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END IF;
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WHEN CHECK_B_LENGTH => v_next_state := COPY_BITSTREAM;
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WHEN COPY_BITSTREAM => IF (size_error = '1') THEN
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v_next_state := IDLE;
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ELSIF (s_bitstream_count_reg(32) = '1') THEN
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v_next_state := SIGNAL_DONE;
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ELSE
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v_next_state := COPY_BITSTREAM;
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END IF;
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WHEN INIT_WRITE_STR => v_next_state := WRITE_STR;
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WHEN WRITE_STR => IF (s_down_counter_reg(16) = '1') THEN
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v_next_state := GET_FIELD_CHAR;
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ELSE
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v_next_state := WRITE_STR;
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END IF;
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WHEN FLUSH_FIFO => v_next_state := EXECUTE_FLUSH_FIFO;
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WHEN SIGNAL_ERROR => v_next_state := SIGNAL_DONE;
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WHEN EXECUTE_FLUSH_FIFO => IF (pop_last = '1' AND
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s_pop_a_byte = '1') THEN
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v_next_state := SIGNAL_ERROR;
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ELSE
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v_next_state := EXECUTE_FLUSH_FIFO;
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END IF;
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WHEN OTHERS => v_next_state := IDLE;
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END CASE;
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_interpreter_state_reg <= IDLE;
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ELSIF (s_watchdog_timer_reg(11) = '1') THEN
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s_interpreter_state_reg <= SIGNAL_ERROR;
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ELSE
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s_interpreter_state_reg <= v_next_state;
|
| 295 |
|
|
END IF;
|
| 296 |
|
|
END IF;
|
| 297 |
|
|
END PROCESS make_state_machine;
|
| 298 |
|
|
|
| 299 |
|
|
--------------------------------------------------------------------------------
|
| 300 |
|
|
--- Here the current field identifier is defined ---
|
| 301 |
|
|
--------------------------------------------------------------------------------
|
| 302 |
|
|
make_field_id : PROCESS( clock , s_interpreter_state_reg , s_data_reg )
|
| 303 |
|
|
BEGIN
|
| 304 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 305 |
|
|
CASE (s_interpreter_state_reg) IS
|
| 306 |
|
|
WHEN IDLE => s_current_field_reg <= FIELD_1;
|
| 307 |
|
|
WHEN INIT_DUMMY_READ => s_current_field_reg <= FIELD_2;
|
| 308 |
|
|
WHEN UPDATE_FIELD_ID => CASE (s_data_reg) IS
|
| 309 |
|
|
WHEN X"61" => s_current_field_reg <= FIELD_3;
|
| 310 |
|
|
WHEN X"62" => s_current_field_reg <= FIELD_4;
|
| 311 |
|
|
WHEN X"63" => s_current_field_reg <= FIELD_5;
|
| 312 |
|
|
WHEN X"64" => s_current_field_reg <= FIELD_6;
|
| 313 |
|
|
WHEN X"65" => s_current_field_reg <= FIELD_7;
|
| 314 |
|
|
WHEN OTHERS=> s_current_field_reg <= HEADER_ERROR;
|
| 315 |
|
|
END CASE;
|
| 316 |
|
|
WHEN OTHERS => NULL;
|
| 317 |
|
|
END CASE;
|
| 318 |
|
|
END IF;
|
| 319 |
|
|
END PROCESS make_field_id;
|
| 320 |
|
|
|
| 321 |
|
|
--------------------------------------------------------------------------------
|
| 322 |
|
|
--- Here the bitstream length reg is defined ---
|
| 323 |
|
|
--------------------------------------------------------------------------------
|
| 324 |
|
|
make_bitstream_length_reg : PROCESS( clock , s_interpreter_state_reg ,
|
| 325 |
|
|
s_pop_a_byte , s_down_counter_reg ,
|
| 326 |
|
|
pop_data )
|
| 327 |
|
|
BEGIN
|
| 328 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 329 |
|
|
IF (s_interpreter_state_reg = GET_B_LENGTH AND
|
| 330 |
|
|
s_pop_a_byte = '1') THEN
|
| 331 |
|
|
CASE (s_down_counter_reg(1 DOWNTO 0)) IS
|
| 332 |
|
|
WHEN "11" => s_bitstream_length_reg( 31 DOWNTO 24 ) <= pop_data;
|
| 333 |
|
|
WHEN "10" => s_bitstream_length_reg( 23 DOWNTO 16 ) <= pop_data;
|
| 334 |
|
|
WHEN "01" => s_bitstream_length_reg( 15 DOWNTO 8 ) <= pop_data;
|
| 335 |
|
|
WHEN OTHERS => s_bitstream_length_reg( 7 DOWNTO 0 ) <= pop_data;
|
| 336 |
|
|
END CASE;
|
| 337 |
|
|
END IF;
|
| 338 |
|
|
END IF;
|
| 339 |
|
|
END PROCESS make_bitstream_length_reg;
|
| 340 |
|
|
|
| 341 |
|
|
--------------------------------------------------------------------------------
|
| 342 |
|
|
--- Here the bitstream counter is defined ---
|
| 343 |
|
|
--------------------------------------------------------------------------------
|
| 344 |
|
|
s_bitstream_count_ena <= '1' WHEN (s_interpreter_state_reg = COPY_BITSTREAM OR
|
| 345 |
|
|
s_interpreter_state_reg = EXECUTE_FLUSH_FIFO) AND
|
| 346 |
|
|
s_pop_a_byte = '1' ELSE '0';
|
| 347 |
|
|
|
| 348 |
|
|
s_bitstream_count_next <= unsigned(s_bitstream_count_reg) - 1;
|
| 349 |
|
|
|
| 350 |
|
|
make_bitstream_count_reg : PROCESS( clock , s_interpreter_state_reg ,
|
| 351 |
|
|
s_bitstream_count_ena ,
|
| 352 |
|
|
s_bitstream_count_next )
|
| 353 |
|
|
VARIABLE v_length : std_logic_vector( 32 DOWNTO 0 );
|
| 354 |
|
|
BEGIN
|
| 355 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 356 |
|
|
IF (s_interpreter_state_reg = GET_B_LENGTH AND
|
| 357 |
|
|
s_pop_a_byte = '1') THEN
|
| 358 |
|
|
CASE (s_down_counter_reg(1 DOWNTO 0)) IS
|
| 359 |
|
|
WHEN "11" => s_bitstream_count_reg( 32 DOWNTO 24 ) <= "0"&pop_data;
|
| 360 |
|
|
WHEN "10" => s_bitstream_count_reg( 23 DOWNTO 16 ) <= pop_data;
|
| 361 |
|
|
WHEN "01" => s_bitstream_count_reg( 15 DOWNTO 8 ) <= pop_data;
|
| 362 |
|
|
WHEN OTHERS => s_bitstream_count_reg( 7 DOWNTO 0 ) <= pop_data;
|
| 363 |
|
|
END CASE;
|
| 364 |
|
|
ELSIF (s_bitstream_count_ena = '1' OR
|
| 365 |
|
|
s_interpreter_state_reg = CHECK_B_LENGTH) THEN
|
| 366 |
|
|
s_bitstream_count_reg <= s_bitstream_count_next;
|
| 367 |
|
|
END IF;
|
| 368 |
|
|
END IF;
|
| 369 |
|
|
END PROCESS make_bitstream_count_reg;
|
| 370 |
|
|
|
| 371 |
|
|
--------------------------------------------------------------------------------
|
| 372 |
|
|
--- Here the error reg is defined ---
|
| 373 |
|
|
--------------------------------------------------------------------------------
|
| 374 |
|
|
make_error_reg : PROCESS( clock , s_interpreter_state_reg )
|
| 375 |
|
|
BEGIN
|
| 376 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 377 |
|
|
IF (s_interpreter_state_reg = IDLE) THEN s_error_reg <= '0';
|
| 378 |
|
|
ELSIF (s_interpreter_state_reg = SIGNAL_ERROR) THEN s_error_reg <= '1';
|
| 379 |
|
|
END IF;
|
| 380 |
|
|
END IF;
|
| 381 |
|
|
END PROCESS make_error_reg;
|
| 382 |
|
|
|
| 383 |
|
|
--------------------------------------------------------------------------------
|
| 384 |
|
|
--- Here the watchdog timer is defined ---
|
| 385 |
|
|
--------------------------------------------------------------------------------
|
| 386 |
|
|
make_watchdog_timer_reg : PROCESS( clock , s_interpreter_state_reg ,
|
| 387 |
|
|
s_pop_a_byte , s_watchdog_timer_reg )
|
| 388 |
|
|
BEGIN
|
| 389 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 390 |
|
|
IF (s_interpreter_state_reg = IDLE OR
|
| 391 |
|
|
s_interpreter_state_reg = SIGNAL_ERROR OR
|
| 392 |
|
|
s_pop_a_byte = '1') THEN
|
| 393 |
|
|
s_watchdog_timer_reg <= (11=>'0' , OTHERS => '1');
|
| 394 |
|
|
ELSIF (s_watchdog_timer_reg(11) = '0' AND
|
| 395 |
|
|
msec_tick = '1') THEN
|
| 396 |
|
|
s_watchdog_timer_reg <= unsigned(s_watchdog_timer_reg) - 1;
|
| 397 |
|
|
END IF;
|
| 398 |
|
|
END IF;
|
| 399 |
|
|
END PROCESS make_watchdog_timer_reg;
|
| 400 |
|
|
|
| 401 |
|
|
--------------------------------------------------------------------------------
|
| 402 |
|
|
--- Here the bitstream size count reg is defined ---
|
| 403 |
|
|
--------------------------------------------------------------------------------
|
| 404 |
|
|
make_bitstream_size_reg : PROCESS( clock , s_pop_a_byte ,
|
| 405 |
|
|
s_interpreter_state_reg )
|
| 406 |
|
|
BEGIN
|
| 407 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 408 |
|
|
IF (s_interpreter_state_reg = IDLE) THEN
|
| 409 |
|
|
s_bitstream_size_reg <= (OTHERS => '0');
|
| 410 |
|
|
ELSIF (s_interpreter_state_reg /= COPY_BITSTREAM AND
|
| 411 |
|
|
s_interpreter_state_reg /= FLUSH_FIFO AND
|
| 412 |
|
|
s_pop_a_byte = '1') THEN
|
| 413 |
|
|
s_bitstream_size_reg <= unsigned(s_bitstream_size_reg) + 1;
|
| 414 |
|
|
ELSIF (s_interpreter_state_reg = CHECK_B_LENGTH) THEN
|
| 415 |
|
|
s_bitstream_size_reg <= unsigned(s_bitstream_size_reg) +
|
| 416 |
|
|
unsigned(s_bitstream_length_reg);
|
| 417 |
|
|
END IF;
|
| 418 |
|
|
END IF;
|
| 419 |
|
|
END PROCESS make_bitstream_size_reg;
|
| 420 |
|
|
|
| 421 |
|
|
make_write_flash_reg : PROCESS( clock , reset , start , write_flash )
|
| 422 |
|
|
BEGIN
|
| 423 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 424 |
|
|
IF (reset = '1') THEN s_write_flash_reg <= '0';
|
| 425 |
|
|
ELSIF (start = '1') THEN s_write_flash_reg <= write_flash;
|
| 426 |
|
|
END IF;
|
| 427 |
|
|
END IF;
|
| 428 |
|
|
END PROCESS make_write_flash_reg;
|
| 429 |
|
|
|
| 430 |
|
|
END no_platform_specific;
|
