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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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-- The unisim library is used for simulation of the xilinx specific components
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-- For generic usage please use:
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-- LIBRARY work;
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-- USE work.xilinx_generic.all;
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-- And use the xilinx generic package found in the xilinx generic module
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LIBRARY unisim;
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USE unisim.all;
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ARCHITECTURE no_platform_specific OF fpga_if IS
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COMPONENT FDE
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GENERIC( INIT : bit );
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PORT ( Q : OUT std_logic;
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C : IN std_logic;
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CE : IN std_logic;
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D : IN std_logic );
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END COMPONENT;
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COMPONENT FD
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GENERIC( INIT : bit );
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PORT ( Q : OUT std_logic;
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C : IN std_logic;
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D : IN std_logic );
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END COMPONENT;
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COMPONENT idreg_rom
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PORT( index : IN std_logic_vector( 4 DOWNTO 0 );
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data : OUT std_logic_vector( 7 DOWNTO 0 ) );
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END COMPONENT;
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COMPONENT fifo_2kb
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PORT ( clock : IN std_logic;
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reset : IN std_logic;
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-- push port
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push : IN std_logic;
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push_data : IN std_logic_vector( 7 DOWNTO 0 );
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push_size : IN std_logic;
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-- pop port
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pop : IN std_logic;
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pop_data : OUT std_logic_vector( 7 DOWNTO 0 );
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pop_size : OUT std_logic;
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-- control port
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fifo_full : OUT std_logic;
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fifo_empty : OUT std_logic );
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END COMPONENT;
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TYPE FPGA_STATE_TYPE IS (IDLE , RESET_STATE , GENERATE_N_PROG ,
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WAIT_N_INIT_HI , WAIT_AFTER_N_INIT , SET_RDNWR_LO ,
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WAIT_RDNWR_LO , SET_N_CS_LO_WRITE , DO_WRITE ,
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WAIT_DONE , SET_CS_HI_WRITE , WAIT_CS_HI_WRITE ,
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SET_RDNWR_HI , WAIT_RDNWR_HI , SET_CS_LO_READ ,
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DO_READ , SET_CS_HI_READ , WAIT_AFTER_DONE ,
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DO_FLUSH , SIGNAL_ERROR );
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SIGNAL s_fpga_state_reg : FPGA_STATE_TYPE;
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SIGNAL s_data_to_fpga : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_data_from_fpga : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_cclk_reg : std_logic;
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SIGNAL s_n_prog_reg : std_logic;
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SIGNAL s_n_cs_reg : std_logic;
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SIGNAL s_rd_n_wr_reg : std_logic;
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SIGNAL s_n_init : std_logic;
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SIGNAL s_busy : std_logic;
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SIGNAL s_done : std_logic;
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SIGNAL s_ena_in_ffs : std_logic;
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SIGNAL s_ena_out_ffs : std_logic;
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SIGNAL s_wait_counter_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_wait_counter_load : std_logic;
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SIGNAL s_wait_counter_ena : std_logic;
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SIGNAL s_last_byte : std_logic;
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SIGNAL s_next_idx_byte : std_logic;
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SIGNAL s_last_idx_byte : std_logic;
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SIGNAL s_idx_index_reg : std_logic_vector( 4 DOWNTO 0 );
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SIGNAL s_idx_data : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_idx_count_reg : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL s_idx_valid_reg : std_logic;
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SIGNAL s_idx_valid : std_logic;
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SIGNAL s_first_time_reg : std_logic;
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SIGNAL s_fpga_rev_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_fpga_type_reg : std_logic_vector( 2 DOWNTO 0 );
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SIGNAL s_valid_out_byte : std_logic;
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SIGNAL s_n_cs_next : std_logic;
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SIGNAL s_fifo_pop : std_logic;
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SIGNAL s_fifo_data : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_fifo_last_byte : std_logic;
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SIGNAL s_fifo_empty : std_logic;
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SIGNAL s_ena_fpga_data_in : std_logic;
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SIGNAL s_ena_data_to_fpga : std_logic;
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BEGIN
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fpga_revision <= s_fpga_rev_reg;
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fpga_configured <= s_done;
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fpga_idle <= '1' WHEN s_fpga_state_reg = IDLE ELSE '0';
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fpga_type <= s_fpga_type_reg;
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s_data_to_fpga <= (OTHERS => '1') WHEN
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s_fpga_state_reg = GENERATE_N_PROG
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ELSE
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s_idx_data WHEN s_first_time_reg = '1' ELSE
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s_fifo_data;
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fpga_n_tri <= X"00" WHEN s_rd_n_wr_reg = '0' ELSE (OTHERS => '1');
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fpga_data_in_ena <= s_ena_fpga_data_in;
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fpga_data_out_ena <= s_ena_data_to_fpga;
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swap: FOR n IN 7 DOWNTO 0 GENERATE
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fpga_data_out(7-n) <= s_data_to_fpga(n);
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s_data_from_fpga(7-n) <= fpga_data_in(n);
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-- For simulation mask above and unmask below
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-- in_ff : FDE
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-- GENERIC MAP (INIT => '1')
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-- PORT MAP ( Q => s_data_from_fpga(n),
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-- CE => s_ena_fpga_data_in,
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-- C => clock,
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-- D => fpga_data_in(n));
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-- one_ff : FDE
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-- GENERIC MAP ( INIT => '1' )
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-- PORT MAP ( Q => fpga_data_out(n),
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-- CE => s_ena_data_to_fpga,
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-- C => clock,
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-- D => s_data_to_fpga(n) );
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END GENERATE swap;
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-------------------------------------------------------------------------------
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--- here all control signals are defined ---
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-------------------------------------------------------------------------------
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s_ena_in_ffs <= s_cclk_reg;
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s_ena_out_ffs <= NOT(s_cclk_reg);
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s_last_byte <= s_last_idx_byte WHEN s_first_time_reg = '1' ELSE
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s_fifo_last_byte;
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s_valid_out_byte <= s_ena_out_ffs
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WHEN
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s_fpga_state_reg = DO_WRITE AND
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NOT (s_n_cs_reg = '0' AND
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s_busy = '1') AND
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(s_first_time_reg = '1' OR
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s_fifo_empty = '0')
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ELSE '0';
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s_n_cs_next <= '0' WHEN s_fpga_state_reg = DO_READ OR
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(s_fpga_state_reg = DO_WRITE AND
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s_valid_out_byte = '1') OR
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(s_n_cs_reg = '0' AND
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s_busy = '1') ELSE '1';
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s_ena_fpga_data_in <= s_ena_in_ffs WHEN
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s_fpga_state_reg = DO_READ
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ELSE '0';
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s_ena_data_to_fpga <= '1' WHEN
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s_valid_out_byte = '1' OR
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s_fpga_state_reg = GENERATE_N_PROG
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ELSE '0';
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-------------------------------------------------------------------------------
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--- Here the IOB intermediate flipflops are defined ---
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-------------------------------------------------------------------------------
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make_cclk_reg : PROCESS( clock , reset , s_fpga_state_reg )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1' OR
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s_fpga_state_reg = IDLE) THEN s_cclk_reg <= '1';
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ELSE s_cclk_reg <= NOT(s_cclk_reg);
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END IF;
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END IF;
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END PROCESS make_cclk_reg;
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make_n_prog_reg : PROCESS( clock , s_fpga_state_reg )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_fpga_state_reg = GENERATE_N_PROG) THEN s_n_prog_reg <= '0';
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ELSE s_n_prog_reg <= '1';
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END IF;
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END IF;
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END PROCESS make_n_prog_reg;
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make_n_cs_reg : PROCESS( clock , s_ena_out_ffs )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_ena_out_ffs = '1') THEN
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s_n_cs_reg <= s_n_cs_next;
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END IF;
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END IF;
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END PROCESS make_n_cs_reg;
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make_rd_n_wr_reg : PROCESS( clock , reset , s_fpga_state_reg )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1' OR
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s_fpga_state_reg = RESET_STATE OR
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s_fpga_state_reg = SET_RDNWR_HI OR
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s_fpga_state_reg = DO_FLUSH) THEN s_rd_n_wr_reg <= '1';
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ELSIF (s_fpga_state_reg = SET_RDNWR_LO) THEN s_rd_n_wr_reg <= '0';
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END IF;
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END IF;
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END PROCESS make_rd_n_wr_reg;
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make_crc_error : PROCESS( clock , s_fpga_state_reg )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_fpga_state_reg = RESET_STATE) THEN fpga_crc_error <= '0';
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ELSIF (s_fpga_state_reg = SIGNAL_ERROR) THEN fpga_crc_error <= '1';
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END IF;
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END IF;
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END PROCESS make_crc_error;
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-------------------------------------------------------------------------------
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--- Here the state machine is defined ---
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-------------------------------------------------------------------------------
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fpga_state_machine : PROCESS( clock , reset , s_fpga_state_reg ,
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s_wait_counter_reg , s_n_init , s_idx_valid ,
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s_idx_count_reg )
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VARIABLE v_next_state : FPGA_STATE_TYPE;
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BEGIN
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CASE (s_fpga_state_reg) IS
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WHEN RESET_STATE => v_next_state := GENERATE_N_PROG;
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WHEN GENERATE_N_PROG => IF (s_wait_counter_reg(7) = '1' AND
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s_n_init = '0') THEN
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v_next_state := WAIT_N_INIT_HI;
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ELSE
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v_next_state := GENERATE_N_PROG;
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END IF;
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WHEN WAIT_N_INIT_HI => IF (s_n_init = '1') THEN
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v_next_state := WAIT_AFTER_N_INIT;
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ELSE
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v_next_state := WAIT_N_INIT_HI;
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END IF;
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WHEN WAIT_AFTER_N_INIT => IF (s_wait_counter_reg(7) = '1') THEN
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v_next_state := SET_RDNWR_LO;
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ELSE
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v_next_state := WAIT_AFTER_N_INIT;
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END IF;
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WHEN SET_RDNWR_LO => v_next_state := WAIT_RDNWR_LO;
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WHEN WAIT_RDNWR_LO => IF (s_wait_counter_reg(7) = '1' AND
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s_ena_out_ffs = '1') THEN
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v_next_state := SET_N_CS_LO_WRITE;
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ELSE
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v_next_state := WAIT_RDNWR_LO;
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END IF;
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WHEN SET_N_CS_LO_WRITE => v_next_state := DO_WRITE;
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WHEN DO_WRITE => IF (s_last_byte = '1' AND
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s_valid_out_byte = '1') THEN
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v_next_state := SET_CS_HI_WRITE;
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ELSIF (s_n_init = '0') THEN
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v_next_state := DO_FLUSH;
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ELSE
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v_next_state := DO_WRITE;
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END IF;
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WHEN SET_CS_HI_WRITE => IF (s_n_cs_reg = '1') THEN
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v_next_state := WAIT_CS_HI_WRITE;
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ELSE
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v_next_state := SET_CS_HI_WRITE;
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END IF;
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WHEN WAIT_CS_HI_WRITE => IF (s_wait_counter_reg(7) = '1') THEN
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v_next_state := SET_RDNWR_HI;
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ELSE
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v_next_state := WAIT_CS_HI_WRITE;
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END IF;
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WHEN SET_RDNWR_HI => v_next_state := WAIT_RDNWR_HI;
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WHEN WAIT_RDNWR_HI => IF (s_wait_counter_reg(7) = '1' AND
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s_ena_out_ffs = '1') THEN
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IF (s_first_time_reg = '1') THEN
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v_next_state := SET_CS_LO_READ;
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ELSE
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v_next_state := WAIT_DONE;
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END IF;
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ELSE
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| 303 |
|
|
v_next_state := WAIT_RDNWR_HI;
|
| 304 |
|
|
END IF;
|
| 305 |
|
|
WHEN SET_CS_LO_READ => v_next_state := DO_READ;
|
| 306 |
|
|
WHEN DO_READ => IF (s_idx_valid = '1' AND
|
| 307 |
|
|
s_idx_count_reg = "11") THEN
|
| 308 |
|
|
v_next_state := SET_CS_HI_READ;
|
| 309 |
|
|
ELSE
|
| 310 |
|
|
v_next_state := DO_READ;
|
| 311 |
|
|
END IF;
|
| 312 |
|
|
WHEN WAIT_DONE => IF (s_done = '1') THEN
|
| 313 |
|
|
v_next_state := WAIT_AFTER_DONE;
|
| 314 |
|
|
ELSE
|
| 315 |
|
|
v_next_state := WAIT_DONE;
|
| 316 |
|
|
END IF;
|
| 317 |
|
|
WHEN WAIT_AFTER_DONE => IF (s_wait_counter_reg(7) = '1') THEN
|
| 318 |
|
|
v_next_state := IDLE;
|
| 319 |
|
|
ELSE
|
| 320 |
|
|
v_next_state := WAIT_AFTER_DONE;
|
| 321 |
|
|
END IF;
|
| 322 |
|
|
WHEN IDLE => IF (s_fifo_empty = '0') THEN
|
| 323 |
|
|
v_next_state := RESET_STATE;
|
| 324 |
|
|
ELSE
|
| 325 |
|
|
v_next_state := IDLE;
|
| 326 |
|
|
END IF;
|
| 327 |
|
|
WHEN DO_FLUSH => IF (s_last_byte = '1' OR
|
| 328 |
|
|
s_first_time_reg = '1') THEN
|
| 329 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 330 |
|
|
ELSE
|
| 331 |
|
|
v_next_state := DO_FLUSH;
|
| 332 |
|
|
END IF;
|
| 333 |
|
|
WHEN OTHERS => v_next_state := IDLE;
|
| 334 |
|
|
END CASE;
|
| 335 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 336 |
|
|
IF (reset = '1') THEN s_fpga_state_reg <= RESET_STATE;
|
| 337 |
|
|
ELSE s_fpga_state_reg <= v_next_state;
|
| 338 |
|
|
END IF;
|
| 339 |
|
|
END IF;
|
| 340 |
|
|
END PROCESS fpga_state_machine;
|
| 341 |
|
|
|
| 342 |
|
|
-------------------------------------------------------------------------------
|
| 343 |
|
|
--- Here the identification signals are defined ---
|
| 344 |
|
|
-------------------------------------------------------------------------------
|
| 345 |
|
|
|
| 346 |
|
|
s_next_idx_byte <= '1' WHEN
|
| 347 |
|
|
s_fpga_state_reg = DO_WRITE AND
|
| 348 |
|
|
s_ena_out_ffs = '1' AND
|
| 349 |
|
|
NOT( s_n_cs_reg = '0' AND
|
| 350 |
|
|
s_busy = '1' ) AND
|
| 351 |
|
|
s_first_time_reg = '1'
|
| 352 |
|
|
ELSE '0';
|
| 353 |
|
|
s_last_idx_byte <= '1' WHEN
|
| 354 |
|
|
s_idx_index_reg = "00000"
|
| 355 |
|
|
ELSE '0';
|
| 356 |
|
|
s_idx_valid <= '1' WHEN
|
| 357 |
|
|
s_idx_valid_reg = '1' AND
|
| 358 |
|
|
s_first_time_reg = '1' AND
|
| 359 |
|
|
s_busy = '0'
|
| 360 |
|
|
ELSE '0';
|
| 361 |
|
|
|
| 362 |
|
|
make_idx_valid : PROCESS( clock , s_fpga_state_reg ,
|
| 363 |
|
|
s_ena_in_ffs )
|
| 364 |
|
|
BEGIN
|
| 365 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 366 |
|
|
IF (s_fpga_state_reg = DO_READ) THEN
|
| 367 |
|
|
s_idx_valid_reg <= s_ena_in_ffs;
|
| 368 |
|
|
ELSE
|
| 369 |
|
|
s_idx_valid_reg <= '0';
|
| 370 |
|
|
END IF;
|
| 371 |
|
|
END IF;
|
| 372 |
|
|
END PROCESS make_idx_valid;
|
| 373 |
|
|
|
| 374 |
|
|
make_idx_count_reg : PROCESS( clock , reset , s_idx_valid )
|
| 375 |
|
|
BEGIN
|
| 376 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 377 |
|
|
IF (reset = '1') THEN s_idx_count_reg <= "00";
|
| 378 |
|
|
ELSIF (s_idx_valid = '1') THEN
|
| 379 |
|
|
s_idx_count_reg <= unsigned(s_idx_count_reg) + 1;
|
| 380 |
|
|
END IF;
|
| 381 |
|
|
END IF;
|
| 382 |
|
|
END PROCESS make_idx_count_reg;
|
| 383 |
|
|
|
| 384 |
|
|
make_idx_index_reg : PROCESS( clock , reset , s_next_idx_byte )
|
| 385 |
|
|
BEGIN
|
| 386 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 387 |
|
|
IF (reset = '1') THEN s_idx_index_reg <= "10011";
|
| 388 |
|
|
ELSIF (s_next_idx_byte = '1') THEN
|
| 389 |
|
|
s_idx_index_reg <= unsigned(s_idx_index_reg) - 1;
|
| 390 |
|
|
END IF;
|
| 391 |
|
|
END IF;
|
| 392 |
|
|
END PROCESS make_idx_index_reg;
|
| 393 |
|
|
|
| 394 |
|
|
make_fpga_rev_reg : PROCESS( clock , reset , s_idx_valid ,
|
| 395 |
|
|
s_idx_count_reg , s_data_from_fpga )
|
| 396 |
|
|
BEGIN
|
| 397 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 398 |
|
|
IF (reset = '1') THEN s_fpga_rev_reg <= X"F";
|
| 399 |
|
|
ELSIF (s_idx_valid = '1' AND
|
| 400 |
|
|
s_idx_count_reg = "00") THEN
|
| 401 |
|
|
s_fpga_rev_reg <= s_data_from_fpga( 7 DOWNTO 4 );
|
| 402 |
|
|
END IF;
|
| 403 |
|
|
END IF;
|
| 404 |
|
|
END PROCESS make_fpga_rev_reg;
|
| 405 |
|
|
|
| 406 |
|
|
make_fpga_type_reg : PROCESS( clock , reset , s_idx_valid ,
|
| 407 |
|
|
s_idx_count_reg , s_data_from_fpga )
|
| 408 |
|
|
BEGIN
|
| 409 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 410 |
|
|
IF (reset = '1') THEN s_fpga_type_reg <= "111";
|
| 411 |
|
|
ELSIF (s_idx_valid = '1') THEN
|
| 412 |
|
|
CASE (s_idx_count_reg) IS
|
| 413 |
|
|
WHEN "00" => IF (s_data_from_fpga(3 DOWNTO 0) = X"1") THEN
|
| 414 |
|
|
s_fpga_type_reg <= "000";
|
| 415 |
|
|
ELSE
|
| 416 |
|
|
s_fpga_type_reg <= "111";
|
| 417 |
|
|
END IF;
|
| 418 |
|
|
WHEN "01" => CASE (s_data_from_fpga) IS
|
| 419 |
|
|
WHEN X"42" => NULL;
|
| 420 |
|
|
WHEN X"43" => s_fpga_type_reg(0) <= '1';
|
| 421 |
|
|
WHEN X"44" => s_fpga_type_reg(1) <= '1';
|
| 422 |
|
|
WHEN X"45" => s_fpga_type_reg(2) <= '1';
|
| 423 |
|
|
WHEN OTHERS=> s_fpga_type_reg <= "111";
|
| 424 |
|
|
END CASE;
|
| 425 |
|
|
WHEN "10" => CASE (s_data_from_fpga) IS
|
| 426 |
|
|
WHEN X"00" |
|
| 427 |
|
|
X"40" => NULL;
|
| 428 |
|
|
WHEN X"80" => s_fpga_type_reg(0) <=
|
| 429 |
|
|
s_fpga_type_reg(1);
|
| 430 |
|
|
WHEN OTHERS => s_fpga_type_reg <= "111";
|
| 431 |
|
|
END CASE;
|
| 432 |
|
|
WHEN OTHERS => IF (s_data_from_fpga /= X"93") THEN
|
| 433 |
|
|
s_fpga_type_reg <= "111";
|
| 434 |
|
|
END IF;
|
| 435 |
|
|
END CASE;
|
| 436 |
|
|
END IF;
|
| 437 |
|
|
END IF;
|
| 438 |
|
|
END PROCESS make_fpga_type_reg;
|
| 439 |
|
|
|
| 440 |
|
|
make_first_time_reg : PROCESS( clock , reset , s_fpga_state_reg )
|
| 441 |
|
|
BEGIN
|
| 442 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 443 |
|
|
IF (reset = '1') THEN s_first_time_reg <= '1';
|
| 444 |
|
|
ELSIF (s_fpga_state_reg = SET_CS_HI_READ) THEN s_first_time_reg <= '0';
|
| 445 |
|
|
END IF;
|
| 446 |
|
|
END IF;
|
| 447 |
|
|
END PROCESS make_first_time_reg;
|
| 448 |
|
|
|
| 449 |
|
|
idx_rom : idreg_rom
|
| 450 |
|
|
PORT MAP ( index => s_idx_index_reg,
|
| 451 |
|
|
data => s_idx_data );
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
-------------------------------------------------------------------------------
|
| 455 |
|
|
--- Here the wait counter is defined ---
|
| 456 |
|
|
-------------------------------------------------------------------------------
|
| 457 |
|
|
|
| 458 |
|
|
s_wait_counter_load <= '1' WHEN
|
| 459 |
|
|
s_fpga_state_reg = RESET_STATE OR
|
| 460 |
|
|
s_fpga_state_reg = WAIT_N_INIT_HI OR
|
| 461 |
|
|
s_fpga_state_reg = SET_RDNWR_LO OR
|
| 462 |
|
|
s_fpga_state_reg = SET_CS_HI_WRITE OR
|
| 463 |
|
|
s_fpga_state_reg = SET_RDNWR_HI OR
|
| 464 |
|
|
s_fpga_state_reg = WAIT_DONE
|
| 465 |
|
|
ELSE '0';
|
| 466 |
|
|
s_wait_counter_ena <= NOT(s_wait_counter_reg(7))
|
| 467 |
|
|
WHEN
|
| 468 |
|
|
s_fpga_state_reg = GENERATE_N_PROG OR
|
| 469 |
|
|
s_fpga_state_reg = WAIT_AFTER_N_INIT OR
|
| 470 |
|
|
s_fpga_state_reg = WAIT_RDNWR_LO OR
|
| 471 |
|
|
s_fpga_state_reg = WAIT_CS_HI_WRITE OR
|
| 472 |
|
|
s_fpga_state_reg = WAIT_RDNWR_HI OR
|
| 473 |
|
|
s_fpga_state_reg = WAIT_AFTER_DONE
|
| 474 |
|
|
ELSE '0';
|
| 475 |
|
|
|
| 476 |
|
|
make_wait_counter_reg : PROCESS( clock , s_wait_counter_load ,
|
| 477 |
|
|
s_wait_counter_ena )
|
| 478 |
|
|
BEGIN
|
| 479 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 480 |
|
|
IF (s_wait_counter_load = '1') THEN
|
| 481 |
|
|
s_wait_counter_reg <= X"7F";
|
| 482 |
|
|
ELSIF (s_wait_counter_ena = '1') THEN
|
| 483 |
|
|
s_wait_counter_reg <= unsigned(s_wait_counter_reg) - 1;
|
| 484 |
|
|
END IF;
|
| 485 |
|
|
END IF;
|
| 486 |
|
|
END PROCESS make_wait_counter_reg;
|
| 487 |
|
|
|
| 488 |
|
|
-------------------------------------------------------------------------------
|
| 489 |
|
|
--- Here the bitfile handling is defined ---
|
| 490 |
|
|
-------------------------------------------------------------------------------
|
| 491 |
|
|
s_fifo_pop <= '1' WHEN s_first_time_reg = '0' AND
|
| 492 |
|
|
(s_valid_out_byte = '1' OR
|
| 493 |
|
|
s_fpga_state_reg = DO_FLUSH ) ELSE '0';
|
| 494 |
|
|
|
| 495 |
|
|
bitfifo : fifo_2kb
|
| 496 |
|
|
PORT MAP ( clock => clock,
|
| 497 |
|
|
reset => reset,
|
| 498 |
|
|
-- push port
|
| 499 |
|
|
push => push,
|
| 500 |
|
|
push_data => push_data,
|
| 501 |
|
|
push_size => last_byte,
|
| 502 |
|
|
-- pop port
|
| 503 |
|
|
pop => s_fifo_pop,
|
| 504 |
|
|
pop_data => s_fifo_data,
|
| 505 |
|
|
pop_size => s_fifo_last_byte,
|
| 506 |
|
|
-- control port
|
| 507 |
|
|
fifo_full => fifo_full,
|
| 508 |
|
|
fifo_empty => s_fifo_empty );
|
| 509 |
|
|
|
| 510 |
|
|
|
| 511 |
|
|
-------------------------------------------------------------------------------
|
| 512 |
|
|
--- Here the IOB flipflops are defined ---
|
| 513 |
|
|
-------------------------------------------------------------------------------
|
| 514 |
|
|
cclk_ff : FD
|
| 515 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 516 |
|
|
PORT MAP ( Q => fpga_cclk,
|
| 517 |
|
|
C => clock,
|
| 518 |
|
|
D => s_cclk_reg );
|
| 519 |
|
|
n_prog_ff : FD
|
| 520 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 521 |
|
|
PORT MAP ( Q => fpga_n_prog,
|
| 522 |
|
|
C => clock,
|
| 523 |
|
|
D => s_n_prog_reg );
|
| 524 |
|
|
n_cs_ff : FDE
|
| 525 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 526 |
|
|
PORT MAP ( Q => fpga_n_cs,
|
| 527 |
|
|
C => clock,
|
| 528 |
|
|
CE => s_ena_out_ffs,
|
| 529 |
|
|
D => s_n_cs_next );
|
| 530 |
|
|
rd_n_wr_ff : FDE
|
| 531 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 532 |
|
|
PORT MAP ( Q => fpga_rd_n_wr,
|
| 533 |
|
|
C => clock,
|
| 534 |
|
|
CE => s_ena_out_ffs,
|
| 535 |
|
|
D => s_rd_n_wr_reg );
|
| 536 |
|
|
n_init_ff : FDE
|
| 537 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 538 |
|
|
PORT MAP ( Q => s_n_init,
|
| 539 |
|
|
C => clock,
|
| 540 |
|
|
CE => s_ena_in_ffs,
|
| 541 |
|
|
D => fpga_n_init );
|
| 542 |
|
|
busy_ff : FDE
|
| 543 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 544 |
|
|
PORT MAP ( Q => s_busy,
|
| 545 |
|
|
C => clock,
|
| 546 |
|
|
CE => s_ena_in_ffs,
|
| 547 |
|
|
D => fpga_busy );
|
| 548 |
|
|
done_ff : FDE
|
| 549 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 550 |
|
|
PORT MAP ( Q => s_done,
|
| 551 |
|
|
C => clock,
|
| 552 |
|
|
CE => s_ena_in_ffs,
|
| 553 |
|
|
D => fpga_done );
|
| 554 |
|
|
|
| 555 |
|
|
END no_platform_specific;
|
