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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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ARCHITECTURE xilinx OF eeprom_emu IS
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COMPONENT edge_detector
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PORT ( clock : IN std_logic;
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reset : IN std_logic;
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data_in : IN std_logic;
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pos_edge : OUT std_logic;
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neg_edge : OUT std_logic;
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data_out : OUT std_logic );
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END COMPONENT;
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COMPONENT spi_if
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PORT ( clock : IN std_logic;
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reset : IN std_logic;
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read_request : IN std_logic;
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write_request : IN std_logic;
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i2c_write_done : IN std_logic;
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address : IN std_logic_vector( 11 DOWNTO 0 );
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data_in : IN std_logic_vector( 7 DOWNTO 0 );
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data_out : OUT std_logic_vector( 7 DOWNTO 0 );
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done : OUT std_logic;
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busy : OUT std_logic );
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END COMPONENT;
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TYPE state_type IS (IDLE,GET_CONTROL,CHECK_CONTROL,SEND_CONTROL_ACK,
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GET_HI_ADDRESS,SEND_HI_ADDR_ACK,GET_LO_ADDRESS,
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SEND_LO_ADDR_ACK,GET_DATA,SEND_DATA_ACK,
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LATCH_DATA_OUT,WRITE_DATA, SAMPLE_DATA_ACK );
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SIGNAL s_scl_neg_edge : std_logic;
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SIGNAL s_scl_pos_edge : std_logic;
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SIGNAL s_scl_value : std_logic;
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SIGNAL s_sda_neg_edge : std_logic;
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SIGNAL s_sda_pos_edge : std_logic;
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SIGNAL s_sda_value : std_logic;
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SIGNAL s_start_condition : std_logic;
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SIGNAL s_stop_condition : std_logic;
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SIGNAL s_shift_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_bit_count_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_state_reg : state_type;
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SIGNAL s_next_state : state_type;
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SIGNAL s_sda_out_next : std_logic;
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SIGNAL s_address_reg : std_logic_vector(11 DOWNTO 0 );
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SIGNAL s_shift_next : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_spi_busy : std_logic;
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SIGNAL s_i2c_write_done : std_logic;
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SIGNAL s_read_request : std_logic;
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SIGNAL s_write_request : std_logic;
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SIGNAL s_read_request_reg : std_logic;
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SIGNAL s_write_request_reg: std_logic;
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BEGIN
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-- Assign outputs
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make_SDA_out : PROCESS( clock , reset , s_sda_out_next , s_scl_neg_edge )
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VARIABLE v_enable_reg : std_logic;
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN SDA_out <= '1';
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v_enable_reg := '0';
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ELSE
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IF (v_enable_reg = '1') THEN SDA_out <= s_sda_out_next;
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END IF;
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v_enable_reg := s_scl_neg_edge;
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END IF;
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END IF;
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END PROCESS make_SDA_out;
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-- Define control signals
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s_read_request <= '1' WHEN s_start_condition = '1' OR
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(s_state_reg = LATCH_DATA_OUT AND
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s_scl_neg_edge = '1') ELSE '0';
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s_write_request <= '1' WHEN (s_state_reg = SEND_DATA_ACK AND
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s_scl_pos_edge = '1') ELSE '0';
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s_i2c_write_done <= s_start_condition OR s_stop_condition;
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s_start_condition <= s_scl_value AND s_sda_neg_edge;
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s_stop_condition <= s_scl_value AND s_sda_pos_edge;
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s_sda_out_next <= '0'
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WHEN s_state_reg = SEND_CONTROL_ACK OR
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s_state_reg = SEND_HI_ADDR_ACK OR
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s_state_reg = SEND_LO_ADDR_ACK OR
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s_state_reg = SEND_DATA_ACK
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ELSE
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s_shift_reg(7) OR NOT(button)
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WHEN s_state_reg = WRITE_DATA
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ELSE '1';
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-- Define processes
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make_regs : PROCESS( clock , reset , s_read_request , s_write_request )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_read_request_reg <= '0';
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s_write_request_reg <= '0';
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ELSE s_read_request_reg <= s_read_request;
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s_write_request_reg <= s_write_request;
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END IF;
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END IF;
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END PROCESS make_regs;
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make_shift_reg : PROCESS( clock , s_state_reg , s_sda_value , s_scl_pos_edge )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_scl_pos_edge = '1' AND
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(s_state_reg = GET_CONTROL OR
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s_state_reg = GET_DATA)) THEN
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s_shift_reg <= s_shift_reg(6 DOWNTO 0)&s_sda_value;
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ELSIF (s_scl_neg_edge = '1' AND
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s_state_reg = LATCH_DATA_OUT) THEN
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s_shift_reg <= s_shift_next;
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ELSIF (s_scl_neg_edge = '1' AND
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s_state_reg = WRITE_DATA) THEN
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s_shift_reg <= s_shift_reg(6 DOWNTO 0)&"1";
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END IF;
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END IF;
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END PROCESS make_shift_reg;
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make_bit_count_reg : PROCESS( clock , s_state_reg , s_scl_pos_edge ,
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s_start_condition )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_state_reg = IDLE OR
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s_state_reg = SEND_CONTROL_ACK OR
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s_state_reg = SEND_HI_ADDR_ACK OR
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s_state_reg = SEND_LO_ADDR_ACK OR
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s_state_reg = SEND_DATA_ACK OR
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s_start_condition = '1') THEN s_bit_count_reg <= X"0";
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ELSIF (s_state_reg = LATCH_DATA_OUT) THEN s_bit_count_reg <= X"1";
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ELSIF (((s_state_reg = GET_CONTROL OR
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s_state_reg = GET_HI_ADDRESS OR
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s_state_reg = GET_LO_ADDRESS OR
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s_state_reg = GET_DATA)AND
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s_scl_pos_edge = '1') OR
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(s_state_reg = WRITE_DATA AND
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s_scl_neg_edge = '1')) THEN
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s_bit_count_reg <= unsigned(s_bit_count_reg) + 1;
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END IF;
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END IF;
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END PROCESS make_bit_count_reg;
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make_address_reg : PROCESS( clock , s_state_reg , s_sda_value ,
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s_scl_pos_edge , reset , s_scl_neg_edge )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_address_reg <= (OTHERS => '0');
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ELSIF (s_scl_pos_edge = '1') THEN
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CASE (s_state_reg) IS
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WHEN GET_HI_ADDRESS => s_address_reg <=
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s_address_reg(10 DOWNTO 8)&s_sda_value&
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s_address_reg( 7 DOWNTO 0);
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WHEN GET_LO_ADDRESS => s_address_reg <=
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s_address_reg(11 DOWNTO 8)&
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s_address_reg( 6 DOWNTO 0)&s_sda_value;
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WHEN OTHERS => NULL;
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END CASE;
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ELSIF (s_scl_pos_edge = '1' AND
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s_state_reg = SEND_DATA_ACK) OR
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(s_scl_neg_edge = '1' AND
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s_state_reg = LATCH_DATA_OUT) THEN
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s_address_reg <= unsigned(s_address_reg) + 1;
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END IF;
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END IF;
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END PROCESS make_address_reg;
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make_next_state : PROCESS( s_state_reg , s_stop_condition ,
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s_start_condition , s_bit_count_reg , s_shift_reg ,
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s_scl_neg_edge , s_scl_pos_edge , s_spi_busy )
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BEGIN
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CASE (s_state_reg) IS
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WHEN GET_CONTROL => IF (s_bit_count_reg(3) = '1') THEN
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s_next_state <= CHECK_CONTROL;
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ELSE
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s_next_state <= GET_CONTROL;
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END IF;
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WHEN CHECK_CONTROL => IF (s_shift_reg(7 DOWNTO 1) /= "1010001" OR
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s_spi_busy = '1') THEN
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s_next_state <= IDLE;
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ELSIF (s_scl_neg_edge = '1') THEN
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s_next_state <= SEND_CONTROL_ACK;
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ELSE
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s_next_state <= CHECK_CONTROL;
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END IF;
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WHEN SEND_CONTROL_ACK => IF (s_scl_pos_edge = '1') THEN
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IF (s_shift_reg(0) = '0') THEN
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s_next_state <= GET_HI_ADDRESS;
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ELSE
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s_next_state <= LATCH_DATA_OUT;
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END IF;
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ELSE
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s_next_state <= SEND_CONTROL_ACK;
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END IF;
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WHEN GET_HI_ADDRESS => IF (s_bit_count_reg(3) = '1') THEN
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s_next_state <= SEND_HI_ADDR_ACK;
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ELSE
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s_next_state <= GET_HI_ADDRESS;
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END IF;
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WHEN SEND_HI_ADDR_ACK => IF (s_scl_pos_edge = '1') THEN
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s_next_state <= GET_LO_ADDRESS;
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ELSE
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s_next_state <= SEND_HI_ADDR_ACK;
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END IF;
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WHEN GET_LO_ADDRESS => IF (s_bit_count_reg(3) = '1') THEN
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s_next_state <= SEND_LO_ADDR_ACK;
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ELSE
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s_next_state <= GET_LO_ADDRESS;
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END IF;
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WHEN SEND_LO_ADDR_ACK => IF (s_scl_pos_edge = '1') THEN
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s_next_state <= GET_DATA;
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ELSE
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s_next_state <= SEND_LO_ADDR_ACK;
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END IF;
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WHEN GET_DATA => IF (s_bit_count_reg(3) = '1') THEN
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s_next_state <= SEND_DATA_ACK;
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ELSE
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s_next_state <= GET_DATA;
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END IF;
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WHEN SEND_DATA_ACK => IF (s_scl_pos_edge = '1') THEN
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s_next_state <= GET_DATA;
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ELSE
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s_next_state <= SEND_DATA_ACK;
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END IF;
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WHEN LATCH_DATA_OUT => IF (s_scl_neg_edge = '1') THEN
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s_next_state <= WRITE_DATA;
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ELSE
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s_next_state <= LATCH_DATA_OUT;
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END IF;
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WHEN WRITE_DATA => IF (s_bit_count_reg(3) = '1' AND
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s_scl_pos_edge = '1') THEN
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s_next_state <= SAMPLE_DATA_ACK;
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ELSE
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s_next_state <= WRITE_DATA;
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END IF;
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WHEN SAMPLE_DATA_ACK => IF (s_scl_pos_edge = '1') THEN
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IF (s_sda_value = '0') THEN
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s_next_state <= LATCH_DATA_OUT;
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ELSE
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s_next_state <= IDLE;
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END IF;
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ELSE
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s_next_state <= SAMPLE_DATA_ACK;
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END IF;
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WHEN OTHERS => s_next_state <= IDLE;
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END CASE;
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END PROCESS make_next_state;
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make_state_reg : PROCESS( clock , reset , s_stop_condition ,
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s_start_condition , s_next_state )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1' OR
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s_stop_condition = '1') THEN s_state_reg <= IDLE;
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ELSIF (s_start_condition = '1') THEN s_state_reg <= GET_CONTROL;
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ELSE s_state_reg <= s_next_state;
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END IF;
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END IF;
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END PROCESS make_state_reg;
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-- Map components
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scl_det : edge_detector
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PORT MAP ( clock => clock,
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reset => reset,
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data_in => SCL_in,
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pos_edge => s_scl_pos_edge,
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neg_edge => s_scl_neg_edge,
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data_out => s_scl_value );
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sda_det : edge_detector
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PORT MAP ( clock => clock,
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reset => reset,
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data_in => SDA_in,
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pos_edge => s_sda_pos_edge,
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neg_edge => s_sda_neg_edge,
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data_out => s_sda_value );
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| 304 |
|
|
spi : spi_if
|
| 305 |
|
|
PORT MAP ( clock => clock,
|
| 306 |
|
|
reset => reset,
|
| 307 |
|
|
read_request => s_read_request_reg,
|
| 308 |
|
|
write_request => s_write_request_reg,
|
| 309 |
|
|
i2c_write_done => s_i2c_write_done,
|
| 310 |
|
|
address => s_address_reg,
|
| 311 |
|
|
data_in => s_shift_reg,
|
| 312 |
|
|
data_out => s_shift_next,
|
| 313 |
|
|
done => OPEN,
|
| 314 |
|
|
busy => s_spi_busy );
|
| 315 |
|
|
|
| 316 |
|
|
END xilinx;
|
