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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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ARCHITECTURE no_platform_specific OF edge_detector IS
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SIGNAL s_pipe_regs : std_logic_vector( 3 DOWNTO 0 );
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BEGIN
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make_pipe_regs : PROCESS( clock , reset , data_in )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_pipe_regs <= (OTHERS => '1');
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ELSE
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s_pipe_regs <= s_pipe_regs( 2 DOWNTO 0 )& data_in;
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END IF;
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END IF;
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END PROCESS make_pipe_regs;
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make_output_regs : PROCESS( clock , reset , s_pipe_regs )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN data_out <= '1';
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pos_edge <= '0';
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neg_edge <= '0';
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ELSE data_out <= s_pipe_regs(1);
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pos_edge <= NOT(s_pipe_regs(3)) AND
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NOT(s_pipe_regs(2)) AND
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s_pipe_regs(1) AND
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s_pipe_regs(0);
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neg_edge <= NOT(s_pipe_regs(0)) AND
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NOT(s_pipe_regs(1)) AND
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s_pipe_regs(2) AND
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s_pipe_regs(3);
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END IF;
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END IF;
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END PROCESS make_output_regs;
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END no_platform_specific;
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