| 1 |
5 |
ktt1 |
--------------------------------------------------------------------------------
|
| 2 |
|
|
-- _ _ __ ____ --
|
| 3 |
|
|
-- / / | | / _| | __| --
|
| 4 |
|
|
-- | |_| | _ _ / / | |_ --
|
| 5 |
|
|
-- | _ | | | | | | | | _| --
|
| 6 |
|
|
-- | | | | | |_| | \ \_ | |__ --
|
| 7 |
|
|
-- |_| |_| \_____| \__| |____| microLab --
|
| 8 |
|
|
-- --
|
| 9 |
|
|
-- Bern University of Applied Sciences (BFH) --
|
| 10 |
|
|
-- Quellgasse 21 --
|
| 11 |
|
|
-- Room HG 4.33 --
|
| 12 |
|
|
-- 2501 Biel/Bienne --
|
| 13 |
|
|
-- Switzerland --
|
| 14 |
|
|
-- --
|
| 15 |
|
|
-- http://www.microlab.ch --
|
| 16 |
|
|
--------------------------------------------------------------------------------
|
| 17 |
|
|
-- GECKO4com
|
| 18 |
|
|
--
|
| 19 |
|
|
-- 2010/2011 Dr. Theo Kluter
|
| 20 |
|
|
--
|
| 21 |
|
|
-- This VHDL code is free code: you can redistribute it and/or modify
|
| 22 |
|
|
-- it under the terms of the GNU General Public License as published by
|
| 23 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
| 24 |
|
|
-- (at your option) any later version.
|
| 25 |
|
|
--
|
| 26 |
|
|
-- This VHDL code is distributed in the hope that it will be useful,
|
| 27 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 28 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 29 |
|
|
-- GNU General Public License for more details.
|
| 30 |
|
|
-- You should have received a copy of the GNU General Public License
|
| 31 |
|
|
-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
|
| 32 |
|
|
--
|
| 33 |
|
|
|
| 34 |
|
|
ARCHITECTURE no_target_specific OF status_controller IS
|
| 35 |
|
|
|
| 36 |
|
|
TYPE STATUS_STATE_TYPE IS (IDLE,SIGNAL_DONE,SIGNAL_ERROR,CLEAR,
|
| 37 |
|
|
GET_VALUE,STORE_VALUE,LATCH_RESULT,SET_OPC,
|
| 38 |
|
|
CALC_100,CALC_10,INIT_SEND,DO_SEND,
|
| 39 |
|
|
SET_TRANSPARENT);
|
| 40 |
|
|
|
| 41 |
|
|
CONSTANT c_100 : std_logic_vector( 6 DOWNTO 0 ) := "1100100";
|
| 42 |
|
|
CONSTANT c_10 : std_logic_vector( 3 DOWNTO 0 ) := X"A";
|
| 43 |
|
|
|
| 44 |
|
|
SIGNAL s_command_state_reg : STATUS_STATE_TYPE;
|
| 45 |
|
|
SIGNAL s_standard_event_status_register : std_logic_vector( 7 DOWNTO 0 );
|
| 46 |
|
|
SIGNAL s_standard_event_status_next : std_logic_vector( 7 DOWNTO 0 );
|
| 47 |
|
|
SIGNAL s_standard_event_status_enable_register : std_logic_vector( 7 DOWNTO 0 );
|
| 48 |
|
|
SIGNAL s_service_request_enable_register : std_logic_vector( 7 DOWNTO 0 );
|
| 49 |
|
|
SIGNAL s_status_byte_register : std_logic_vector( 7 DOWNTO 0 );
|
| 50 |
|
|
SIGNAL s_transparent_reg : std_logic;
|
| 51 |
|
|
SIGNAL s_pop : std_logic;
|
| 52 |
|
|
SIGNAL s_valid_data : std_logic;
|
| 53 |
|
|
SIGNAL s_value_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 54 |
|
|
SIGNAL s_overflow : std_logic;
|
| 55 |
|
|
SIGNAL s_result_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 56 |
|
|
SIGNAL s_100_remain_reg : std_logic_vector( 6 DOWNTO 0 );
|
| 57 |
|
|
SIGNAL s_100_div_reg : std_logic_vector( 1 DOWNTO 0 );
|
| 58 |
|
|
SIGNAL s_10_remain_reg : std_logic_vector( 3 DOWNTO 0 );
|
| 59 |
|
|
SIGNAL s_10_div_reg : std_logic_vector( 3 DOWNTO 0 );
|
| 60 |
|
|
SIGNAL s_send_cnt_reg : std_logic_vector( 3 DOWNTO 0 );
|
| 61 |
|
|
SIGNAL s_push : std_logic;
|
| 62 |
|
|
|
| 63 |
|
|
BEGIN
|
| 64 |
|
|
--------------------------------------------------------------------------------
|
| 65 |
|
|
--- Here the outputs are defined ---
|
| 66 |
|
|
--------------------------------------------------------------------------------
|
| 67 |
|
|
cmd_error <= '1' WHEN s_command_state_reg = SIGNAL_ERROR ELSE '0';
|
| 68 |
|
|
done <= '1' WHEN s_command_state_reg = SIGNAL_DONE ELSE '0';
|
| 69 |
|
|
pop <= s_pop;
|
| 70 |
|
|
push <= s_push;
|
| 71 |
|
|
push_size <= '1' WHEN s_send_cnt_reg = X"4" ELSE '0';
|
| 72 |
|
|
transparent <= s_transparent_reg;
|
| 73 |
|
|
status_nibble <= s_status_byte_register( 5 DOWNTO 2 );
|
| 74 |
|
|
|
| 75 |
|
|
make_push_data : PROCESS( s_send_cnt_reg , s_10_div_reg , s_100_div_reg ,
|
| 76 |
|
|
s_10_remain_reg )
|
| 77 |
|
|
BEGIN
|
| 78 |
|
|
CASE (s_send_cnt_reg) IS
|
| 79 |
|
|
WHEN X"4" => IF (s_10_div_reg = X"0" AND
|
| 80 |
|
|
s_100_div_reg = "00") THEN
|
| 81 |
|
|
push_data <= X"02";
|
| 82 |
|
|
ELSIF (s_100_div_reg = "00") THEN
|
| 83 |
|
|
push_data <= X"03";
|
| 84 |
|
|
ELSE
|
| 85 |
|
|
push_data <= X"04";
|
| 86 |
|
|
END IF;
|
| 87 |
|
|
WHEN X"3" => push_data <= X"3"&"00"&s_100_div_reg;
|
| 88 |
|
|
WHEN X"2" => push_data <= X"3"&s_10_div_reg;
|
| 89 |
|
|
WHEN X"1" => push_data <= X"3"&s_10_remain_reg;
|
| 90 |
|
|
WHEN X"0" => push_data <= X"0A";
|
| 91 |
|
|
WHEN OTHERS => push_data <= X"00";
|
| 92 |
|
|
END CASE;
|
| 93 |
|
|
END PROCESS make_push_data;
|
| 94 |
|
|
|
| 95 |
|
|
--------------------------------------------------------------------------------
|
| 96 |
|
|
--- Here the control signals are defined ---
|
| 97 |
|
|
--------------------------------------------------------------------------------
|
| 98 |
|
|
s_pop <= '1' WHEN s_command_state_reg = GET_VALUE AND
|
| 99 |
|
|
pop_empty = '0' ELSE '0';
|
| 100 |
|
|
s_push <= '1' WHEN s_send_cnt_reg(3) = '0' AND
|
| 101 |
|
|
push_full = '0' ELSE '0';
|
| 102 |
|
|
s_valid_data <= '1' WHEN (pop_data = X"30" OR
|
| 103 |
|
|
pop_data = X"31" OR
|
| 104 |
|
|
pop_data = X"32" OR
|
| 105 |
|
|
pop_data = X"33" OR
|
| 106 |
|
|
pop_data = X"34" OR
|
| 107 |
|
|
pop_data = X"35" OR
|
| 108 |
|
|
pop_data = X"36" OR
|
| 109 |
|
|
pop_data = X"37" OR
|
| 110 |
|
|
pop_data = X"38" OR
|
| 111 |
|
|
pop_data = X"39") AND
|
| 112 |
|
|
s_pop = '1' ELSE '0';
|
| 113 |
|
|
|
| 114 |
|
|
s_status_byte_register(7) <= '0';
|
| 115 |
|
|
s_status_byte_register(6) <= (s_service_request_enable_register(7) AND
|
| 116 |
|
|
s_status_byte_register(7))
|
| 117 |
|
|
OR
|
| 118 |
|
|
(s_service_request_enable_register(5) AND
|
| 119 |
|
|
s_status_byte_register(5))
|
| 120 |
|
|
OR
|
| 121 |
|
|
(s_service_request_enable_register(4) AND
|
| 122 |
|
|
s_status_byte_register(4))
|
| 123 |
|
|
OR
|
| 124 |
|
|
(s_service_request_enable_register(3) AND
|
| 125 |
|
|
s_status_byte_register(3))
|
| 126 |
|
|
OR
|
| 127 |
|
|
(s_service_request_enable_register(2) AND
|
| 128 |
|
|
s_status_byte_register(2))
|
| 129 |
|
|
OR
|
| 130 |
|
|
(s_service_request_enable_register(1) AND
|
| 131 |
|
|
s_status_byte_register(1))
|
| 132 |
|
|
OR
|
| 133 |
|
|
(s_service_request_enable_register(0) AND
|
| 134 |
|
|
s_status_byte_register(0));
|
| 135 |
|
|
s_status_byte_register(5) <= ((s_standard_event_status_register(0) AND
|
| 136 |
|
|
s_standard_event_status_enable_register(0))
|
| 137 |
|
|
OR
|
| 138 |
|
|
(s_standard_event_status_register(1) AND
|
| 139 |
|
|
s_standard_event_status_enable_register(1))
|
| 140 |
|
|
OR
|
| 141 |
|
|
(s_standard_event_status_register(2) AND
|
| 142 |
|
|
s_standard_event_status_enable_register(2))
|
| 143 |
|
|
OR
|
| 144 |
|
|
(s_standard_event_status_register(3) AND
|
| 145 |
|
|
s_standard_event_status_enable_register(3))
|
| 146 |
|
|
OR
|
| 147 |
|
|
(s_standard_event_status_register(4) AND
|
| 148 |
|
|
s_standard_event_status_enable_register(4))
|
| 149 |
|
|
OR
|
| 150 |
|
|
(s_standard_event_status_register(5) AND
|
| 151 |
|
|
s_standard_event_status_enable_register(5))
|
| 152 |
|
|
OR
|
| 153 |
|
|
(s_standard_event_status_register(6) AND
|
| 154 |
|
|
s_standard_event_status_enable_register(6))
|
| 155 |
|
|
OR
|
| 156 |
|
|
(s_standard_event_status_register(7) AND
|
| 157 |
|
|
s_standard_event_status_enable_register(7)))
|
| 158 |
|
|
WHEN s_transparent_reg = '0' ELSE
|
| 159 |
|
|
ESB_bit;
|
| 160 |
|
|
s_status_byte_register(4) <= NOT(push_empty); -- MAV bit
|
| 161 |
|
|
s_status_byte_register(3) <= STATUS3_bit WHEN s_transparent_reg = '1' ELSE
|
| 162 |
|
|
fpga_configured;
|
| 163 |
|
|
s_status_byte_register(2) <= s_transparent_reg;
|
| 164 |
|
|
s_status_byte_register(1) <= '0';
|
| 165 |
|
|
s_status_byte_register(0) <= '0';
|
| 166 |
|
|
|
| 167 |
|
|
s_standard_event_status_next(0) <= '1' WHEN s_command_state_reg = SET_OPC ELSE
|
| 168 |
|
|
s_standard_event_status_register(0);
|
| 169 |
|
|
s_standard_event_status_next(1) <= s_standard_event_status_register(1);
|
| 170 |
|
|
s_standard_event_status_next(2) <= s_standard_event_status_register(2);
|
| 171 |
|
|
s_standard_event_status_next(3) <= s_standard_event_status_register(3);
|
| 172 |
|
|
s_standard_event_status_next(4) <= s_standard_event_status_register(4) OR
|
| 173 |
|
|
execution_error;
|
| 174 |
|
|
s_standard_event_status_next(5) <= s_standard_event_status_register(5) OR
|
| 175 |
|
|
command_error;
|
| 176 |
|
|
s_standard_event_status_next(6) <= s_standard_event_status_register(6);
|
| 177 |
|
|
s_standard_event_status_next(7) <= s_standard_event_status_register(7);
|
| 178 |
|
|
--------------------------------------------------------------------------------
|
| 179 |
|
|
--- Here the state machine is defined ---
|
| 180 |
|
|
--------------------------------------------------------------------------------
|
| 181 |
|
|
make_state_machine : PROCESS( clock , reset , s_command_state_reg , start ,
|
| 182 |
|
|
command )
|
| 183 |
|
|
VARIABLE v_next_state : STATUS_STATE_TYPE;
|
| 184 |
|
|
BEGIN
|
| 185 |
|
|
CASE (s_command_state_reg) IS
|
| 186 |
|
|
WHEN IDLE => IF (start = '1') THEN
|
| 187 |
|
|
CASE (command) IS
|
| 188 |
|
|
WHEN "0000010" => v_next_state := CLEAR;
|
| 189 |
|
|
WHEN "0000110" |
|
| 190 |
|
|
"0010000" => v_next_state := GET_VALUE;
|
| 191 |
|
|
WHEN "0000111" |
|
| 192 |
|
|
"0001000" |
|
| 193 |
|
|
"0010001" |
|
| 194 |
|
|
"0010010" |
|
| 195 |
|
|
"0001100" |
|
| 196 |
|
|
"0010100" |
|
| 197 |
|
|
"0001010" => v_next_state := LATCH_RESULT;
|
| 198 |
|
|
WHEN "0001011" => v_next_state := SET_OPC;
|
| 199 |
|
|
WHEN "0010101" => v_next_state := SIGNAL_DONE;
|
| 200 |
|
|
WHEN "0110011" => v_next_state := SET_TRANSPARENT;
|
| 201 |
|
|
WHEN OTHERS => v_next_state := IDLE;
|
| 202 |
|
|
END CASE;
|
| 203 |
|
|
ELSE
|
| 204 |
|
|
v_next_state := IDLE;
|
| 205 |
|
|
END IF;
|
| 206 |
|
|
WHEN CLEAR => v_next_state := SIGNAL_DONE;
|
| 207 |
|
|
WHEN GET_VALUE => IF (s_overflow = '1') THEN
|
| 208 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 209 |
|
|
ELSIF (s_pop = '1') THEN
|
| 210 |
|
|
IF (pop_data = X"0A" OR
|
| 211 |
|
|
pop_data = X"3B" OR
|
| 212 |
|
|
(pop_last = '1' AND
|
| 213 |
|
|
(s_valid_data = '1' OR
|
| 214 |
|
|
pop_data = X"20"))) THEN
|
| 215 |
|
|
v_next_state := STORE_VALUE;
|
| 216 |
|
|
ELSIF (pop_last = '0' AND
|
| 217 |
|
|
(s_valid_data = '1' OR
|
| 218 |
|
|
pop_data = X"20")) THEN
|
| 219 |
|
|
v_next_state := GET_VALUE;
|
| 220 |
|
|
ELSE
|
| 221 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 222 |
|
|
END IF;
|
| 223 |
|
|
ELSE
|
| 224 |
|
|
v_next_state := GET_VALUE;
|
| 225 |
|
|
END IF;
|
| 226 |
|
|
WHEN STORE_VALUE => v_next_state := SIGNAL_DONE;
|
| 227 |
|
|
WHEN LATCH_RESULT => v_next_state := CALC_100;
|
| 228 |
|
|
WHEN CALC_100 => v_next_state := CALC_10;
|
| 229 |
|
|
WHEN CALC_10 => v_next_state := INIT_SEND;
|
| 230 |
|
|
WHEN INIT_SEND => v_next_state := DO_SEND;
|
| 231 |
|
|
WHEN DO_SEND => IF (s_send_cnt_reg(3) = '1') THEN
|
| 232 |
|
|
v_next_state := SIGNAL_DONE;
|
| 233 |
|
|
ELSE
|
| 234 |
|
|
v_next_state := DO_SEND;
|
| 235 |
|
|
END IF;
|
| 236 |
|
|
WHEN SET_OPC => v_next_state := SIGNAL_DONE;
|
| 237 |
|
|
WHEN SET_TRANSPARENT => IF (fpga_configured = '1') THEN
|
| 238 |
|
|
v_next_state := SIGNAL_DONE;
|
| 239 |
|
|
ELSE
|
| 240 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 241 |
|
|
END IF;
|
| 242 |
|
|
WHEN OTHERS => v_next_state := IDLE;
|
| 243 |
|
|
END CASE;
|
| 244 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 245 |
|
|
IF (reset = '1') THEN s_command_state_reg <= IDLE;
|
| 246 |
|
|
ELSE s_command_state_reg <= v_next_state;
|
| 247 |
|
|
END IF;
|
| 248 |
|
|
END IF;
|
| 249 |
|
|
END PROCESS make_state_machine;
|
| 250 |
|
|
|
| 251 |
|
|
--------------------------------------------------------------------------------
|
| 252 |
|
|
--- Here the value handling is defined ---
|
| 253 |
|
|
--------------------------------------------------------------------------------
|
| 254 |
|
|
make_value_reg : PROCESS( clock , s_command_state_reg , pop_data ,
|
| 255 |
|
|
s_valid_data )
|
| 256 |
|
|
VARIABLE v_add_1 : std_logic_vector(11 DOWNTO 0 );
|
| 257 |
|
|
VARIABLE v_add_2 : std_logic_vector(11 DOWNTO 0 );
|
| 258 |
|
|
VARIABLE v_add_3 : std_logic_vector(11 DOWNTO 0 );
|
| 259 |
|
|
VARIABLE v_sum : std_logic_vector(11 DOWNTO 0 );
|
| 260 |
|
|
BEGIN
|
| 261 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 262 |
|
|
IF (s_command_state_reg = IDLE) THEN
|
| 263 |
|
|
s_value_reg <= X"00";
|
| 264 |
|
|
s_overflow <= '0';
|
| 265 |
|
|
ELSIF (s_valid_data = '1') THEN
|
| 266 |
|
|
v_add_1 := X"00"&pop_data( 3 DOWNTO 0 );
|
| 267 |
|
|
v_add_2 := "000"&s_value_reg&"0";
|
| 268 |
|
|
v_add_3 := "0"&s_value_reg&"000";
|
| 269 |
|
|
v_sum := unsigned(v_add_1) + unsigned(v_add_2) + unsigned(v_add_3);
|
| 270 |
|
|
s_value_reg <= v_sum( 7 DOWNTO 0 );
|
| 271 |
|
|
s_overflow <= v_sum(8) OR v_sum(9) OR v_sum(10) OR v_sum(11);
|
| 272 |
|
|
END IF;
|
| 273 |
|
|
END IF;
|
| 274 |
|
|
END PROCESS make_value_reg;
|
| 275 |
|
|
|
| 276 |
|
|
--------------------------------------------------------------------------------
|
| 277 |
|
|
--- Here the query handling is defined ---
|
| 278 |
|
|
--------------------------------------------------------------------------------
|
| 279 |
|
|
make_result_reg : PROCESS( clock , s_command_state_reg , reset )
|
| 280 |
|
|
BEGIN
|
| 281 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 282 |
|
|
IF (reset = '1') THEN s_result_reg <= X"00";
|
| 283 |
|
|
ELSIF (s_command_state_reg = LATCH_RESULT) THEN
|
| 284 |
|
|
CASE (command) IS
|
| 285 |
|
|
WHEN "0000111" => s_result_reg <= s_standard_event_status_enable_register;
|
| 286 |
|
|
WHEN "0001000" => s_result_reg <= s_standard_event_status_register;
|
| 287 |
|
|
WHEN "0010001" => s_result_reg <= s_service_request_enable_register;
|
| 288 |
|
|
WHEN "0010010" => s_result_reg <= s_status_byte_register;
|
| 289 |
|
|
WHEN "0001100" => s_result_reg <= X"01";
|
| 290 |
|
|
WHEN OTHERS => s_result_reg <= X"00";
|
| 291 |
|
|
END CASE;
|
| 292 |
|
|
END IF;
|
| 293 |
|
|
END IF;
|
| 294 |
|
|
END PROCESS make_result_reg;
|
| 295 |
|
|
|
| 296 |
|
|
make_100_regs : PROCESS( clock , s_result_reg )
|
| 297 |
|
|
VARIABLE v_sub_1_1 : std_logic_vector( 8 DOWNTO 0 );
|
| 298 |
|
|
VARIABLE v_sub_1_2 : std_logic_vector( 8 DOWNTO 0 );
|
| 299 |
|
|
VARIABLE v_sub_1 : std_logic_vector( 8 DOWNTO 0 );
|
| 300 |
|
|
VARIABLE v_sub_2_1 : std_logic_vector( 7 DOWNTO 0 );
|
| 301 |
|
|
VARIABLE v_sub_2_2 : std_logic_vector( 7 DOWNTO 0 );
|
| 302 |
|
|
VARIABLE v_sub_2 : std_logic_vector( 7 DOWNTO 0 );
|
| 303 |
|
|
BEGIN
|
| 304 |
|
|
v_sub_1_1 := "0"&s_result_reg;
|
| 305 |
|
|
v_sub_1_2 := "0"&c_100&"0";
|
| 306 |
|
|
v_sub_1 := unsigned(v_sub_1_1)-unsigned(v_sub_1_2);
|
| 307 |
|
|
IF (v_sub_1(8) = '0') THEN v_sub_2_1 := v_sub_1( 7 DOWNTO 0 );
|
| 308 |
|
|
ELSE v_sub_2_1 := s_result_reg;
|
| 309 |
|
|
END IF;
|
| 310 |
|
|
v_sub_2_2 := "0"&c_100;
|
| 311 |
|
|
v_sub_2 := unsigned(v_sub_2_1) - unsigned(v_sub_2_2);
|
| 312 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 313 |
|
|
IF (v_sub_2(7) = '0') THEN s_100_remain_reg <= v_sub_2( 6 DOWNTO 0 );
|
| 314 |
|
|
ELSE s_100_remain_reg <= v_sub_2_1( 6 DOWNTO 0 );
|
| 315 |
|
|
END IF;
|
| 316 |
|
|
s_100_div_reg(1) <= NOT(v_sub_1(8));
|
| 317 |
|
|
s_100_div_reg(0) <= NOT(v_sub_2(7));
|
| 318 |
|
|
END IF;
|
| 319 |
|
|
END PROCESS make_100_regs;
|
| 320 |
|
|
|
| 321 |
|
|
make_10_regs : PROCESS( clock , s_100_remain_reg )
|
| 322 |
|
|
VARIABLE v_sub_1 : std_logic_vector( 4 DOWNTO 0 );
|
| 323 |
|
|
VARIABLE v_remain_1 : std_logic_vector( 4 DOWNTO 0 );
|
| 324 |
|
|
VARIABLE v_sub_2 : std_logic_vector( 4 DOWNTO 0 );
|
| 325 |
|
|
VARIABLE v_remain_2 : std_logic_vector( 4 DOWNTO 0 );
|
| 326 |
|
|
VARIABLE v_sub_3 : std_logic_vector( 4 DOWNTO 0 );
|
| 327 |
|
|
VARIABLE v_remain_3 : std_logic_vector( 4 DOWNTO 0 );
|
| 328 |
|
|
VARIABLE v_sub_4 : std_logic_vector( 4 DOWNTO 0 );
|
| 329 |
|
|
BEGIN
|
| 330 |
|
|
v_sub_1 := unsigned("0"&s_100_remain_reg(6 DOWNTO 3)) -
|
| 331 |
|
|
unsigned("0"&c_10);
|
| 332 |
|
|
IF (v_sub_1(4) = '0') THEN
|
| 333 |
|
|
v_remain_1 := v_sub_1(3 DOWNTO 0)&s_100_remain_reg(2);
|
| 334 |
|
|
ELSE
|
| 335 |
|
|
v_remain_1 := s_100_remain_reg(6 DOWNTO 2);
|
| 336 |
|
|
END IF;
|
| 337 |
|
|
v_sub_2 := unsigned(v_remain_1) - unsigned("0"&c_10);
|
| 338 |
|
|
IF (v_sub_2(4) = '0') THEN
|
| 339 |
|
|
v_remain_2 := v_sub_2(3 DOWNTO 0)&s_100_remain_reg(1);
|
| 340 |
|
|
ELSE
|
| 341 |
|
|
v_remain_2 := v_remain_1(3 DOWNTO 0)&s_100_remain_reg(1);
|
| 342 |
|
|
END IF;
|
| 343 |
|
|
v_sub_3 := unsigned(v_remain_2) - unsigned("0"&c_10);
|
| 344 |
|
|
IF (v_sub_3(4) = '0') THEN
|
| 345 |
|
|
v_remain_3 := v_sub_3(3 DOWNTO 0)&s_100_remain_reg(0);
|
| 346 |
|
|
ELSE
|
| 347 |
|
|
v_remain_3 := v_remain_2(3 DOWNTO 0)&s_100_remain_reg(0);
|
| 348 |
|
|
END IF;
|
| 349 |
|
|
v_sub_4 := unsigned(v_remain_3) - unsigned("0"&c_10);
|
| 350 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 351 |
|
|
IF (v_sub_4(4) = '0') THEN s_10_remain_reg <= v_sub_4(3 DOWNTO 0);
|
| 352 |
|
|
ELSE s_10_remain_reg <= v_remain_3(3 DOWNTO 0);
|
| 353 |
|
|
END IF;
|
| 354 |
|
|
s_10_div_reg(3) <= NOT(v_sub_1(4));
|
| 355 |
|
|
s_10_div_reg(2) <= NOT(v_sub_2(4));
|
| 356 |
|
|
s_10_div_reg(1) <= NOT(v_sub_3(4));
|
| 357 |
|
|
s_10_div_reg(0) <= NOT(v_sub_4(4));
|
| 358 |
|
|
END IF;
|
| 359 |
|
|
END PROCESS make_10_regs;
|
| 360 |
|
|
|
| 361 |
|
|
--------------------------------------------------------------------------------
|
| 362 |
|
|
--- Here the data sending is defined ---
|
| 363 |
|
|
--------------------------------------------------------------------------------
|
| 364 |
|
|
make_send_cnt_reg : PROCESS( clock , reset , s_command_state_reg , s_push )
|
| 365 |
|
|
BEGIN
|
| 366 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 367 |
|
|
IF (reset = '1') THEN s_send_cnt_reg <= (OTHERS => '1');
|
| 368 |
|
|
ELSIF (s_command_state_reg = INIT_SEND) THEN
|
| 369 |
|
|
s_send_cnt_reg <= X"4";
|
| 370 |
|
|
ELSIF (s_push = '1') THEN
|
| 371 |
|
|
CASE (s_send_cnt_reg) IS
|
| 372 |
|
|
WHEN X"4" => IF (s_10_div_reg = X"0" AND
|
| 373 |
|
|
s_100_div_reg = "00") THEN
|
| 374 |
|
|
s_send_cnt_reg <= X"1";
|
| 375 |
|
|
ELSIF (s_100_div_reg = "00") THEN
|
| 376 |
|
|
s_send_cnt_reg <= X"2";
|
| 377 |
|
|
ELSE
|
| 378 |
|
|
s_send_cnt_reg <= X"3";
|
| 379 |
|
|
END IF;
|
| 380 |
|
|
WHEN OTHERS => s_send_cnt_reg <= unsigned(s_send_cnt_reg) - 1;
|
| 381 |
|
|
END CASE;
|
| 382 |
|
|
END IF;
|
| 383 |
|
|
END IF;
|
| 384 |
|
|
END PROCESS make_send_cnt_reg;
|
| 385 |
|
|
|
| 386 |
|
|
--------------------------------------------------------------------------------
|
| 387 |
|
|
--- Here all registers are defined ---
|
| 388 |
|
|
--------------------------------------------------------------------------------
|
| 389 |
|
|
make_seser : PROCESS( clock , reset , s_command_state_reg ,
|
| 390 |
|
|
command , s_value_reg)
|
| 391 |
|
|
BEGIN
|
| 392 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 393 |
|
|
IF (reset = '1') THEN s_standard_event_status_enable_register <= X"00";
|
| 394 |
|
|
ELSIF (s_command_state_reg = STORE_VALUE AND
|
| 395 |
|
|
command = "0000110" ) THEN
|
| 396 |
|
|
s_standard_event_status_enable_register <= s_value_reg;
|
| 397 |
|
|
END IF;
|
| 398 |
|
|
END IF;
|
| 399 |
|
|
END PROCESS make_seser;
|
| 400 |
|
|
|
| 401 |
|
|
make_sesr : PROCESS( clock , reset , s_command_state_reg ,
|
| 402 |
|
|
s_standard_event_status_next )
|
| 403 |
|
|
BEGIN
|
| 404 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 405 |
|
|
IF (reset = '1') THEN s_standard_event_status_register <= X"80";
|
| 406 |
|
|
ELSIF (s_command_state_reg = CLEAR OR
|
| 407 |
|
|
(s_command_state_reg = LATCH_RESULT AND
|
| 408 |
|
|
command = "0001000")) THEN
|
| 409 |
|
|
s_standard_event_status_register <= X"00";
|
| 410 |
|
|
ELSE
|
| 411 |
|
|
s_standard_event_status_register <= s_standard_event_status_next;
|
| 412 |
|
|
END IF;
|
| 413 |
|
|
END IF;
|
| 414 |
|
|
END PROCESS make_sesr;
|
| 415 |
|
|
|
| 416 |
|
|
make_srer : PROCESS( clock , reset , s_command_state_reg ,
|
| 417 |
|
|
command , s_value_reg)
|
| 418 |
|
|
BEGIN
|
| 419 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 420 |
|
|
IF (reset = '1') THEN s_service_request_enable_register <= X"00";
|
| 421 |
|
|
ELSIF (s_command_state_reg = STORE_VALUE AND
|
| 422 |
|
|
command = "0010000" ) THEN
|
| 423 |
|
|
s_service_request_enable_register <= s_value_reg;
|
| 424 |
|
|
END IF;
|
| 425 |
|
|
END IF;
|
| 426 |
|
|
END PROCESS make_srer;
|
| 427 |
|
|
|
| 428 |
|
|
make_transparent_reg : PROCESS( clock , reset , s_command_state_reg )
|
| 429 |
|
|
BEGIN
|
| 430 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 431 |
|
|
IF (s_command_state_reg = CLEAR OR
|
| 432 |
|
|
reset = '1') THEN s_transparent_reg <= '0';
|
| 433 |
|
|
ELSIF (s_command_state_reg = SET_TRANSPARENT AND
|
| 434 |
|
|
fpga_configured = '1') THEN
|
| 435 |
|
|
s_transparent_reg <= '1';
|
| 436 |
|
|
END IF;
|
| 437 |
|
|
END IF;
|
| 438 |
|
|
END PROCESS make_transparent_reg;
|
| 439 |
|
|
|
| 440 |
|
|
END no_target_specific;
|
