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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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ARCHITECTURE no_target_specific OF reset_if IS
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SIGNAL s_reset_count_reg : std_logic_vector( 4 DOWNTO 0 );
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SIGNAL s_user_count_reg : std_logic_vector( 4 DOWNTO 0 );
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SIGNAL s_done_pending_reg: std_logic;
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BEGIN
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n_reset_system <= '0' WHEN s_reset_count_reg(4) = '0' ELSE 'Z';
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user_n_reset <= '0' WHEN s_user_count_reg(4) = '0' ELSE '1';
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command_done <= '1' WHEN (s_done_pending_reg = '1' AND
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s_reset_count_reg(4) = '1' AND
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s_user_count_reg(4) = '1') OR
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(start_command = '1' AND
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(command_id = "0001111" OR
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command_id = "0111010") AND
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fpga_configured = '0') ELSE '0';
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--------------------------------------------------------------------------------
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--- Here the reset counter is defined ---
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--------------------------------------------------------------------------------
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make_reset_count_reg : PROCESS( clock , reset , start_command , command_id ,
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fpga_configured )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF ((start_command = '1' AND
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command_id = "0001111") OR
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fpga_configured = '0' OR
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reset = '1') THEN s_reset_count_reg <= "0"&X"A";
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ELSIF (msec_tick = '1' AND
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s_reset_count_reg(4) = '0') THEN
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s_reset_count_reg <= unsigned(s_reset_count_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_reset_count_reg;
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make_user_count_reg : PROCESS( clock , reset , start_command , command_id ,
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fpga_configured )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF ((start_command = '1' AND
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command_id = "0111010") OR
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fpga_configured = '0' OR
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reset = '1') THEN s_user_count_reg <= "0"&X"A";
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ELSIF (msec_tick = '1' AND
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s_user_count_reg(4) = '0') THEN
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s_user_count_reg <= unsigned(s_user_count_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_user_count_reg;
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make_done_pending_reg : PROCESS( clock , reset , start_command , command_id ,
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s_reset_count_reg )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (start_command = '1' AND
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(command_id = "0001111" OR
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command_id = "0111010") AND
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fpga_configured = '1') THEN s_done_pending_reg <= '1';
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ELSIF (reset = '1' OR
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(s_reset_count_reg(4) = '1' AND
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s_user_count_reg(4) = '1')) THEN s_done_pending_reg <= '0';
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END IF;
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END IF;
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END PROCESS make_done_pending_reg;
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END no_target_specific;
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