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[/] [gecko4/] [trunk/] [GECKO4com/] [spartan200_an/] [vhdl/] [toplevel/] [xc3s200an_top-behavior.vhdl] - Blame information for rev 5

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1 5 ktt1 
--------------------------------------------------------------------------------
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--            _   _            __   ____                                      --
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--           / / | |          / _| |  __|                                     --
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--           | |_| |  _   _  / /   | |_                                       --
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--           |  _  | | | | | | |   |  _|                                      --
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--           | | | | | |_| | \ \_  | |__                                      --
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--           |_| |_| \_____|  \__| |____| microLab                            --
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--                                                                            --
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--           Bern University of Applied Sciences (BFH)                        --
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--           Quellgasse 21                                                    --
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--           Room HG 4.33                                                     --
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--           2501 Biel/Bienne                                                 --
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--           Switzerland                                                      --
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--                                                                            --
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--           http://www.microlab.ch                                           --
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--------------------------------------------------------------------------------
17 
--   GECKO4com
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--
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--   2010/2011 Dr. Theo Kluter
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--
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--   This VHDL code is free code: you can redistribute it and/or modify
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--   it under the terms of the GNU General Public License as published by
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--   the Free Software Foundation, either version 3 of the License, or
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--   (at your option) any later version.
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--
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--   This VHDL code is distributed in the hope that it will be useful,
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--   but WITHOUT ANY WARRANTY; without even the implied warranty of
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--   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--   GNU General Public License for more details.
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--   You should have received a copy of the GNU General Public License
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--   along with these sources.  If not, see <http://www.gnu.org/licenses/>.
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--
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34 
ARCHITECTURE behave OF xc3s200an_top IS
35 
 
36 
   COMPONENT clocks
37 
      PORT ( system_n_reset    : IN  std_logic;
38 
             clock_25MHz       : IN  std_logic;
39 
             clock_16MHz       : IN  std_logic;
40 
             user_clock_1      : IN  std_logic;
41 
             user_clock_2      : IN  std_logic;
42 
             -- Here the compensated clocks are defined
43 
             user_clock_1_out  : OUT std_logic;
44 
             user_clock_1_fb   : IN  std_logic;
45 
             user_clock_1_lock : OUT std_logic;
46 
             user_clock_2_out  : OUT std_logic;
47 
             user_clock_2_fb   : IN  std_logic;
48 
             user_clock_2_lock : OUT std_logic;
49 
             -- Here the master clocks are defined
50 
             clock_25MHz_out   : OUT std_logic;
51 
             clock_48MHz_out   : OUT std_logic;
52 
             -- Here the FPGA internal clocks are defined
53 
             clk_48MHz         : OUT std_logic;
54 
             clk_96MHz         : OUT std_logic;
55 
             clk_75MHz         : OUT std_logic;
56 
             reset_out         : OUT std_logic;
57 
             msec_tick         : OUT std_logic );
58 
   END COMPONENT;
59 
 
60 
   COMPONENT eeprom_emu
61 
      PORT ( clock     : IN  std_logic;
62 
             reset     : IN  std_logic;
63 
             button    : IN  std_logic;
64 
             SDA_in    : IN  std_logic;
65 
             SCL_in    : IN  std_logic;
66 
             SDA_out   : OUT std_logic );
67 
   END COMPONENT;
68 
 
69 
   COMPONENT USBTMC
70 
      PORT ( clock_96MHz      : IN  std_logic;
71 
             clock_48MHz      : IN  std_logic;
72 
             cpu_reset        : IN  std_logic;
73 
             sync_reset_out   : OUT std_logic;
74 
             -- FX2 control interface
75 
             FX2_n_ready      : IN  std_logic;
76 
             FX2_hi_speed     : IN  std_logic;
77 
             -- SCPI command interpretor interface
78 
             pending_message  : IN  std_logic;
79 
             transfer_in_prog : OUT std_logic;
80 
             -- read fifo interface
81 
             rf_pop           : IN  std_logic;
82 
             rf_pop_data      : OUT std_logic_vector( 7 DOWNTO 0 );
83 
             rf_last_data_byte: OUT std_logic;
84 
             rf_fifo_empty    : OUT std_logic;
85 
             -- Write fifo interface
86 
             wf_push          : IN  std_logic;
87 
             wf_push_data     : IN  std_logic_vector( 7 DOWNTO 0 );
88 
             wf_push_size_bit : IN  std_logic;
89 
             wf_fifo_full     : OUT std_logic;
90 
             wf_fifo_empty    : OUT std_logic;
91 
             -- status interface
92 
             status_nibble    : IN  std_logic_vector( 3 DOWNTO 0 );
93 
             indicator_pulse  : OUT std_logic;
94 
             -- FX2 port D interface
95 
             data_nibble      : OUT std_logic_vector( 3 DOWNTO 0 );
96 
             data_select      : IN  std_logic_vector( 3 DOWNTO 0 );
97 
             -- FX2 FIFO interface
98 
             EP8_n_empty      : IN  std_logic;
99 
             EP6_n_full       : IN  std_logic;
100 
             EP_data_in       : IN  std_logic_vector( 7 DOWNTO 0 );
101 
             EP_address       : OUT std_logic_vector( 1 DOWNTO 0 );
102 
             EP_IFCLOCK       : OUT std_logic;
103 
             EP_n_PKTEND      : OUT std_logic;
104 
             EP_n_OE          : OUT std_logic;
105 
             EP_n_RE          : OUT std_logic;
106 
             EP_n_WE          : OUT std_logic;
107 
             EP_data_out      : OUT std_logic_vector( 7 DOWNTO 0 );
108 
             EP_n_tri_out     : OUT std_logic_vector( 7 DOWNTO 0 ) );
109 
   END COMPONENT;
110 
 
111 
   COMPONENT vga_controller
112 
      PORT ( clock_75MHz         : IN  std_logic;
113 
             reset               : IN  std_logic;
114 
             vga_off             : IN  std_logic;
115 
             clock               : IN  std_logic;
116 
             -- Here the scpi interface is defined
117 
             start_command       : IN  std_logic;
118 
             command_id          : IN  std_logic_vector( 6 DOWNTO 0 );
119 
             command_done        : OUT std_logic;
120 
             command_error       : OUT std_logic;
121 
             -- Here the usbtmc fifo interface is defined
122 
             pop                 : OUT std_logic;
123 
             pop_data            : IN  std_logic_vector(  7 DOWNTO 0 );
124 
             pop_last            : IN  std_logic;
125 
             pop_empty           : IN  std_logic;
126 
             push                : OUT std_logic;
127 
             push_data           : OUT std_logic_vector(  7 DOWNTO 0 );
128 
             push_size           : OUT std_logic;
129 
             push_full           : IN  std_logic;
130 
             -- Here the PUD interface is defined
131 
             we_char             : IN  std_logic;
132 
             we_ascii            : IN  std_logic_vector(  7 DOWNTO 0 );
133 
             we_addr             : IN  std_logic_vector( 10 DOWNTO 0 );
134 
             -- Here the fpga interface is defined
135 
             cursor_pos          : IN  std_logic_vector( 10 DOWNTO 0 );
136 
             screen_offset       : IN  std_logic_vector(  4 DOWNTO 0 );
137 
             fg_color            : IN  std_logic_vector(  2 DOWNTO 0 );
138 
             bg_color            : IN  std_logic_vector(  2 DOWNTO 0 );
139 
             write_address       : IN  std_logic_vector( 10 DOWNTO 0 );
140 
             ascii_data          : IN  std_logic_vector(  7 DOWNTO 0 );
141 
             we                  : IN  std_logic;
142 
             vga_red             : OUT std_logic;
143 
             vga_green           : OUT std_logic;
144 
             vga_blue            : OUT std_logic;
145 
             vga_hsync           : OUT std_logic;
146 
             vga_vsync           : OUT std_logic );
147 
   END COMPONENT;
148 
 
149 
   COMPONENT SCPI_INTERFACE
150 
      PORT ( clock            : IN  std_logic;
151 
             reset            : IN  std_logic;
152 
             -- The command interface
153 
             transparent_mode : IN  std_logic;
154 
             start_command    : OUT std_logic;
155 
             command_id       : OUT std_logic_vector( 6 DOWNTO 0 );
156 
             cmd_gen_respons  : OUT std_logic;
157 
             command_done     : IN  std_logic;
158 
             command_error    : IN  std_logic;
159 
             unknown_command  : OUT std_logic;
160 
             slave_pop        : IN  std_logic;
161 
             -- USBTMC fifo interface
162 
             pop              : OUT std_logic;
163 
             pop_data         : IN  std_logic_vector( 7 DOWNTO 0 );
164 
             pop_empty        : IN  std_logic;
165 
             pop_last         : IN  std_logic);
166 
   END COMPONENT;
167 
 
168 
   COMPONENT IDN_handler
169 
      PORT ( clock     : IN  std_logic;
170 
             reset     : IN  std_logic;
171 
             start     : IN  std_logic;
172 
             command   : IN  std_logic_vector( 6 DOWNTO 0 );
173 
             fifo_full : IN  std_logic;
174 
             done      : OUT std_logic;
175 
             push      : OUT std_logic;
176 
             size_bit  : OUT std_logic;
177 
             push_data : OUT std_logic_vector( 7 DOWNTO 0 ) );
178 
   END COMPONENT;
179 
 
180 
   COMPONENT identify_handler
181 
      PORT ( clock       : IN  std_logic;
182 
             reset       : IN  std_logic;
183 
             start       : IN  std_logic;
184 
             command     : IN  std_logic_vector( 6 DOWNTO 0 );
185 
             indicator   : IN  std_logic;
186 
             done        : OUT std_logic;
187 
             flash_idle  : IN  std_logic;
188 
             msec_tick   : IN  std_logic;
189 
             leds_a_in   : IN  std_logic_vector( 7 DOWNTO 0 );
190 
             leds_k_in   : IN  std_logic_vector( 7 DOWNTO 0 );
191 
             leds_a      : OUT std_logic_vector( 7 DOWNTO 0 );
192 
             leds_k      : OUT std_logic_vector( 7 DOWNTO 0 ));
193 
   END COMPONENT;
194 
 
195 
   COMPONENT fpga_if
196 
      PORT ( clock             : IN  std_logic;
197 
             reset             : IN  std_logic;
198 
             -- Here the FPGA info is provided
199 
             fpga_idle         : OUT std_logic;
200 
             fpga_revision     : OUT std_logic_vector( 3 DOWNTO 0 );
201 
             fpga_type         : OUT std_logic_vector( 2 DOWNTO 0 );
202 
             fpga_configured   : OUT std_logic;
203 
             fpga_crc_error    : OUT std_logic;
204 
             -- Here the bitfile fifo if is defined
205 
             push              : IN  std_logic;
206 
             push_data         : IN  std_logic_vector( 7 DOWNTO 0 );
207 
             last_byte         : IN  std_logic;
208 
             fifo_full         : OUT std_logic;
209 
             -- Here the select map pins are defined
210 
             fpga_done         : IN  std_logic;
211 
             fpga_busy         : IN  std_logic;
212 
             fpga_n_init       : IN  std_logic;
213 
             fpga_n_prog       : OUT std_logic;
214 
             fpga_rd_n_wr      : OUT std_logic;
215 
             fpga_n_cs         : OUT std_logic;
216 
             fpga_cclk         : OUT std_logic;
217 
             fpga_data_in      : IN  std_logic_vector( 7 DOWNTO 0 );
218 
             fpga_data_out     : OUT std_logic_vector( 7 DOWNTO 0 );
219 
             fpga_n_tri        : OUT std_logic_vector( 7 DOWNTO 0 );
220 
             fpga_data_in_ena  : OUT std_logic;
221 
             fpga_data_out_ena : OUT std_logic);
222 
   END COMPONENT;
223 
 
224 
   COMPONENT bitfile_interpreter
225 
      PORT ( clock                 : IN  std_logic;
226 
             reset                 : IN  std_logic;
227 
             msec_tick             : IN  std_logic;
228 
             -- Here the handshake interface is defined
229 
             start                 : IN  std_logic;
230 
             write_flash           : IN  std_logic;
231 
             done                  : OUT std_logic;
232 
             error_detected        : OUT std_logic;
233 
             -- Here the FX2 fifo interface is defined
234 
             pop                   : OUT std_logic;
235 
             pop_data              : IN  std_logic_vector( 7 DOWNTO 0 );
236 
             pop_last              : IN  std_logic;
237 
             fifo_empty            : IN  std_logic;
238 
             -- Here the FPGA_IF fifo interface is defined
239 
             push                  : OUT std_logic;
240 
             push_data             : OUT std_logic_vector( 7 DOWNTO 0 );
241 
             last_byte             : OUT std_logic;
242 
             fifo_full             : IN  std_logic;
243 
             reset_fpga_if         : OUT std_logic;
244 
             -- Here the flash write fifo interface is defined
245 
             bitfile_size          : OUT std_logic_vector(31 DOWNTO 0 );
246 
             we_fifo               : OUT std_logic;
247 
             we_data               : OUT std_logic_vector( 7 DOWNTO 0 );
248 
             we_last               : OUT std_logic;
249 
             we_fifo_full          : IN  std_logic;
250 
             start_write           : OUT std_logic;
251 
             size_error            : IN  std_logic;
252 
             -- Here the debug vga interface is defined
253 
             we_char               : OUT std_logic;
254 
             ascii_data            : OUT std_logic_vector( 7 DOWNTO 0 ));
255 
   END COMPONENT;
256 
 
257 
   COMPONENT flash_if
258 
      PORT ( clock                : IN  std_logic;
259 
             reset                : IN  std_logic;
260 
             msec_tick            : IN  std_logic;
261 
             -- here the control interface is defined
262 
             start_erase          : IN  std_logic;
263 
             start_read           : IN  std_logic;
264 
             start_write          : IN  std_logic;
265 
             done                 : OUT std_logic;
266 
             flash_present        : OUT std_logic;
267 
             flash_s1_empty       : OUT std_logic;
268 
             flash_idle           : OUT std_logic;
269 
             size_error           : OUT std_logic;
270 
             flash_n_busy         : OUT std_logic;
271 
             start_config         : OUT std_logic;
272 
             -- here the push fifo interface is defined
273 
             push                 : OUT std_logic;
274 
             push_data            : OUT std_logic_vector( 7 DOWNTO 0 );
275 
             push_size            : OUT std_logic;
276 
             push_last            : OUT std_logic;
277 
             fifo_full            : IN  std_logic;
278 
             -- here the write fifo is defined
279 
             bitfile_size         : IN  std_logic_vector( 31 DOWNTO 0 );
280 
             we_fifo              : IN  std_logic;
281 
             we_data              : IN  std_logic_vector(  7 DOWNTO 0 );
282 
             we_last              : IN  std_logic;
283 
             we_fifo_full         : OUT std_logic;
284 
             -- Here the scpi interface is defined
285 
             start_command        : IN  std_logic;
286 
             command_id           : IN  std_logic_vector( 6 DOWNTO 0 );
287 
             scpi_pop             : OUT std_logic;
288 
             scpi_pop_data        : IN  std_logic_vector( 7 DOWNTO 0 );
289 
             scpi_pop_last        : IN  std_logic;
290 
             scpi_empty           : IN  std_logic;
291 
             scpi_push            : OUT std_logic;
292 
             scpi_push_data       : OUT std_logic_vector( 7 DOWNTO 0 );
293 
             scpi_push_size       : OUT std_logic;
294 
             scpi_full            : IN  std_logic;
295 
             -- Here the vga interface is defined
296 
             we_char              : OUT std_logic;
297 
             we_ascii             : OUT std_logic_vector(  7 DOWNTO 0 );
298 
             we_addr              : OUT std_logic_vector( 10 DOWNTO 0 );
299 
             -- define the flash interface
300 
             flash_address        : OUT std_logic_vector( 19 DOWNTO 0 );
301 
             flash_data_in        : IN  std_logic_vector( 15 DOWNTO 0 );
302 
             flash_data_out       : OUT std_logic_vector( 15 DOWNTO 0 );
303 
             flash_data_oe        : OUT std_logic_vector( 15 DOWNTO 0 );
304 
             flash_n_byte         : OUT std_logic;
305 
             flash_n_ce           : OUT std_logic;
306 
             flash_n_oe           : OUT std_logic;
307 
             flash_n_we           : OUT std_logic;
308 
             flash_ready_n_busy   : IN  std_logic);
309 
   END COMPONENT;
310 
 
311 
   COMPONENT cmd_18_1e_if
312 
      PORT ( clock           : IN  std_logic;
313 
             reset           : IN  std_logic;
314 
             -- Here the scpi interface is defined
315 
             start_command   : IN  std_logic;
316 
             command_id      : IN  std_logic_vector( 6 DOWNTO 0 );
317 
             command_done    : OUT std_logic;
318 
             -- Here the tx_fifo is defined
319 
             push            : OUT std_logic;
320 
             push_size       : OUT std_logic;
321 
             push_data       : OUT std_logic_vector( 7 DOWNTO 0 );
322 
             fifo_full       : IN  std_logic;
323 
             -- Here the fpga_if is defined
324 
             fpga_type       : IN  std_logic_vector( 2 DOWNTO 0 );
325 
             fpga_configured : IN  std_logic;
326 
             flash_empty     : IN  std_logic;
327 
             -- Here the board interface is defined
328 
             n_usb_power     : IN  std_logic;
329 
             n_bus_power     : IN  std_logic;
330 
             n_usb_charge    : IN  std_logic);
331 
   END COMPONENT;
332 
 
333 
   COMPONENT reset_if
334 
      PORT ( clock          : IN  std_logic;
335 
             reset          : IN  std_logic;
336 
             msec_tick      : IN  std_logic;
337 
             -- Here the fpga_interface is defined
338 
             fpga_configured: IN  std_logic;
339 
             -- Here the scpi interface is defined
340 
             start_command  : IN  std_logic;
341 
             command_id     : IN  std_logic_vector( 6 DOWNTO 0 );
342 
             command_done   : OUT std_logic;
343 
             -- Here the system reset is defined
344 
             n_reset_system : OUT std_logic;
345 
             user_n_reset   : OUT std_logic);
346 
   END COMPONENT;
347 
 
348 
   COMPONENT hexswitch
349 
      PORT ( clock         : IN  std_logic;
350 
             reset         : IN  std_logic;
351 
             n_hex_sw      : IN  std_logic_vector( 3 DOWNTO 0 );
352 
             hex_value     : OUT std_logic_vector( 3 DOWNTO 0 );
353 
             -- here the scpi interface is defined
354 
             start         : IN  std_logic;
355 
             command       : IN  std_logic_vector( 6 DOWNTO 0 );
356 
             command_error : OUT std_logic;
357 
             done          : OUT std_logic;
358 
             pop           : OUT std_logic;
359 
             pop_data      : IN  std_logic_vector( 7 DOWNTO 0 );
360 
             pop_last      : IN  std_logic;
361 
             pop_empty     : IN  std_logic;
362 
             push          : OUT std_logic;
363 
             push_data     : OUT std_logic_vector( 7 DOWNTO 0 );
364 
             push_size     : OUT std_logic;
365 
             push_full     : IN  std_logic );
366 
   END COMPONENT;
367 
 
368 
   COMPONENT config_if
369 
      PORT ( clock                  : IN  std_logic;
370 
             reset                  : IN  std_logic;
371 
             -- here the flash interface is defined
372 
             start_config           : IN  std_logic;
373 
             flash_start_read       : OUT std_logic;
374 
             flash_done             : IN  std_logic;
375 
             flash_present          : IN  std_logic;
376 
             flash_s1_empty         : IN  std_logic;
377 
             flash_idle             : IN  std_logic;
378 
             flash_push             : IN  std_logic;
379 
             flash_push_data        : IN  std_logic_vector( 7 DOWNTO 0 );
380 
             flash_push_size        : IN  std_logic;
381 
             flash_push_last        : IN  std_logic;
382 
             flash_fifo_full        : OUT std_logic;
383 
             -- here the flash usbtmc interface is defined
384 
             flash_u_start_read     : IN  std_logic;
385 
             flash_u_done           : OUT std_logic;
386 
             flash_u_push           : OUT std_logic;
387 
             flash_u_push_data      : OUT std_logic_vector( 7 DOWNTO 0 );
388 
             flash_u_push_size      : OUT std_logic;
389 
             flash_u_fifo_full      : IN  std_logic;
390 
             -- here the bitfile interface is defined
391 
             bitfile_start          : OUT std_logic;
392 
             bitfile_pop            : IN  std_logic;
393 
             bitfile_pop_data       : OUT std_logic_vector( 7 DOWNTO 0 );
394 
             bitfile_last           : OUT std_logic;
395 
             bitfile_fifo_empty     : OUT std_logic;
396 
             -- here the bitfile usbtmc interface is defined
397 
             bitfile_u_start        : IN  std_logic;
398 
             bitfile_u_pop          : OUT std_logic;
399 
             bitfile_u_pop_data     : IN  std_logic_vector( 7 DOWNTO 0 );
400 
             bitfile_u_last         : IN  std_logic;
401 
             bitfile_u_fifo_empty   : IN  std_logic;
402 
             -- here the fpga interface is defined
403 
             fpga_idle              : IN  std_logic;
404 
             fpga_type              : IN  std_logic_vector( 2 DOWNTO 0 );
405 
             -- here the power interface is defined
406 
             n_bus_power            : IN  std_logic;
407 
             -- here the scpi interface is defined
408 
             start_command          : IN  std_logic;
409 
             command_id             : IN  std_logic_vector( 6 DOWNTO 0 );
410 
             command_error          : OUT std_logic );
411 
   END COMPONENT;
412 
 
413 
   COMPONENT status_controller
414 
      PORT ( clock           : IN  std_logic;
415 
             reset           : IN  std_logic;
416 
             fpga_configured : IN  std_logic;
417 
             -- Here the fx2 interface is defined
418 
             status_nibble   : OUT std_logic_vector( 3 DOWNTO 0 );
419 
             -- Here the external status if is defined
420 
             ESB_bit         : IN  std_logic;
421 
             STATUS3_bit     : IN  std_logic;
422 
             -- Here the scpi interface is defined
423 
             start           : IN  std_logic;
424 
             command         : IN  std_logic_vector( 6 DOWNTO 0 );
425 
             cmd_error       : OUT std_logic;
426 
             command_error   : IN  std_logic;
427 
             execution_error : IN  std_logic;
428 
             done            : OUT std_logic;
429 
             transparent     : OUT std_logic;
430 
             pop             : OUT std_logic;
431 
             pop_data        : IN  std_logic_vector( 7 DOWNTO 0 );
432 
             pop_last        : IN  std_logic;
433 
             pop_empty       : IN  std_logic;
434 
             push            : OUT std_logic;
435 
             push_data       : OUT std_logic_vector( 7 DOWNTO 0 );
436 
             push_size       : OUT std_logic;
437 
             push_full       : IN  std_logic;
438 
             push_empty      : IN  std_logic );
439 
   END COMPONENT;
440 
 
441 
   COMPONENT bus_if
442 
      PORT ( clock                    : IN    std_logic;
443 
             reset                    : IN    std_logic;
444 
             -- Here the IOB interface is defined
445 
             bus_reset                : IN    std_logic;
446 
             bus_n_start_transmission : IN    std_logic;
447 
             bus_n_end_transmission   : INOUT std_logic;
448 
             bus_n_data_valid         : INOUT std_logic_vector( 1 DOWNTO 0 );
449 
             bus_data_addr_cntrl      : INOUT std_logic_vector(15 DOWNTO 0 );
450 
             bus_n_start_send         : OUT   std_logic;
451 
             bus_n_error              : OUT   std_logic;
452 
             -- Here the FPGA internal interface is defined
453 
             b_n_reset                : OUT   std_logic;
454 
             b_n_start_transmission   : OUT   std_logic;
455 
             b_n_end_transmission_out : OUT   std_logic;
456 
             b_n_end_transmission_in  : IN    std_logic;
457 
             b_n_data_valid_out       : OUT   std_logic_vector( 1 DOWNTO 0 );
458 
             b_n_data_valid_in        : IN    std_logic_vector( 1 DOWNTO 0 );
459 
             data_out                 : OUT   std_logic_vector(15 DOWNTO 0 );
460 
             data_in                  : IN    std_logic_vector(15 DOWNTO 0 );
461 
             read_n_write             : OUT   std_logic;
462 
             burst_size               : OUT   std_logic_vector( 8 DOWNTO 0 );
463 
             address                  : OUT   std_logic_vector( 5 DOWNTO 0 );
464 
             n_start_send             : IN    std_logic;
465 
             n_bus_error              : IN    std_logic);
466 
   END COMPONENT;
467 
 
468 
   COMPONENT vga_bus
469 
      PORT ( clock                  : IN  std_logic;
470 
             reset                  : IN  std_logic;
471 
             msec_tick              : IN  std_logic;
472 
             -- Here the bus signals are defined
473 
             n_bus_reset            : IN  std_logic;
474 
             n_start_transmission   : IN  std_logic;
475 
             n_end_transmission_in  : IN  std_logic;
476 
             n_end_transmission_out : OUT std_logic;
477 
             n_data_valid_in        : IN  std_logic; -- Only for low byte!
478 
             n_data_valid_out       : OUT std_logic_vector( 1 DOWNTO 0 );
479 
             data_in                : IN  std_logic_vector( 7 DOWNTO 0 );
480 
             data_out               : OUT std_logic_vector(15 DOWNTO 0 );
481 
             read_n_write           : IN  std_logic;
482 
             burst_size             : IN  std_logic_vector( 8 DOWNTO 0 );
483 
             bus_address            : IN  std_logic_vector( 5 DOWNTO 0 );
484 
             n_start_send           : OUT std_logic;
485 
             n_bus_error            : OUT std_logic;
486 
             -- Here the button interface is defined
487 
             n_button_1             : IN  std_logic;
488 
             n_button_2             : IN  std_logic;
489 
             n_button_3             : IN  std_logic;
490 
             hexswitch              : IN  std_logic_vector( 3 DOWNTO 0 );
491 
             -- Here the LED interface is defined
492 
             leds_a                 : OUT std_logic_vector( 7 DOWNTO 0 );
493 
             leds_k                 : OUT std_logic_vector( 7 DOWNTO 0 );
494 
             -- Here the VGA interface is defined
495 
             cursor_pos             : OUT std_logic_vector( 10 DOWNTO 0 );
496 
             screen_offset          : OUT std_logic_vector(  4 DOWNTO 0 );
497 
             fg_color               : OUT std_logic_vector(  2 DOWNTO 0 );
498 
             bg_color               : OUT std_logic_vector(  2 DOWNTO 0 );
499 
             write_address          : OUT std_logic_vector( 10 DOWNTO 0 );
500 
             ascii_data             : OUT std_logic_vector(  7 DOWNTO 0 );
501 
             we                     : OUT std_logic);
502 
   END COMPONENT;
503 
 
504 
   COMPONENT user_fifo
505 
      PORT ( clock                  : IN  std_logic;
506 
             reset                  : IN  std_logic;
507 
             -- Here the bus signals are defined
508 
             n_bus_reset            : IN  std_logic;
509 
             n_start_transmission   : IN  std_logic;
510 
             n_end_transmission_in  : IN  std_logic;
511 
             n_end_transmission_out : OUT std_logic;
512 
             n_data_valid_in        : IN  std_logic_vector( 1 DOWNTO 0 );
513 
             n_data_valid_out       : OUT std_logic_vector( 1 DOWNTO 0 );
514 
             data_in                : IN  std_logic_vector(15 DOWNTO 0 );
515 
             data_out               : OUT std_logic_vector(15 DOWNTO 0 );
516 
             read_n_write           : IN  std_logic;
517 
             burst_size             : IN  std_logic_vector( 8 DOWNTO 0 );
518 
             bus_address            : IN  std_logic_vector( 5 DOWNTO 0 );
519 
             n_start_send           : OUT std_logic;
520 
             n_bus_error            : OUT std_logic;
521 
             -- Here the scpi interface is defined
522 
             start_command          : IN  std_logic;
523 
             command_id             : IN  std_logic_vector( 6 DOWNTO 0 );
524 
             transparent_mode       : IN  std_logic;
525 
             command_done           : OUT std_logic;
526 
             command_error          : OUT std_logic;
527 
             message_available      : OUT std_logic;
528 
             -- Here the tx_fifo is defined
529 
             push                   : OUT std_logic;
530 
             push_size              : OUT std_logic;
531 
             push_data              : OUT std_logic_vector( 7 DOWNTO 0 );
532 
             fifo_full              : IN  std_logic;
533 
             -- Here the rx_fifo is defined
534 
             pop                    : OUT std_logic;
535 
             pop_last               : IN  std_logic;
536 
             pop_data               : IN  std_logic_vector( 7 DOWNTO 0 );
537 
             pop_empty              : IN  std_logic;
538 
             -- Here the big fpga interface is defined
539 
             data_request_irq       : OUT std_logic;
540 
             data_available_irq     : OUT std_logic;
541 
             error_irq              : OUT std_logic);
542 
   END COMPONENT;
543 
 
544 
   COMPONENT DFF
545 
      PORT ( clock  : IN  std_logic;
546 
             D      : IN  std_logic;
547 
             Q      : OUT std_logic );
548 
   END COMPONENT;
549 
 
550 
   COMPONENT FDE
551 
      PORT ( Q   : OUT std_logic;
552 
             CE  : IN  std_logic;
553 
             C   : IN  std_logic;
554 
             D   : IN  std_logic );
555 
   END COMPONENT;
556 
 
557 
   COMPONENT FD
558 
      PORT ( Q   : OUT std_logic;
559 
             C   : IN  std_logic;
560 
             D   : IN  std_logic );
561 
   END COMPONENT;
562 
 
563 
   SIGNAL s_clock_75MHz                : std_logic;
564 
   SIGNAL s_clock_96MHz                : std_logic;
565 
   SIGNAL s_reset                      : std_logic;
566 
   SIGNAL s_vga_red                    : std_logic;
567 
   SIGNAL s_vga_green                  : std_logic;
568 
   SIGNAL s_vga_blue                   : std_logic;
569 
   SIGNAL s_vga_hsync                  : std_logic;
570 
   SIGNAL s_vga_vsync                  : std_logic;
571 
   SIGNAL s_usb_clk                    : std_logic;
572 
   SIGNAL s_n_usb_clk                  : std_logic;
573 
   SIGNAL s_clk_48MHz                  : std_logic;
574 
   SIGNAL s_msec_tick                  : std_logic;
575 
   SIGNAL s_usb_reset                  : std_logic;
576 
 
577 
   SIGNAL s_SDA                        : std_logic;
578 
   SIGNAL s_SDA_pin                    : std_logic;
579 
   SIGNAL s_SDA_OE                     : std_logic;
580 
 
581 
   SIGNAL s_wf_push                    : std_logic;
582 
   SIGNAL s_wf_push_data               : std_logic_vector( 7 DOWNTO 0 );
583 
   SIGNAL s_wf_push_size_bit           : std_logic;
584 
   SIGNAL s_wf_fifo_full               : std_logic;
585 
   SIGNAL s_wf_fifo_empty              : std_logic;
586 
   SIGNAL s_fx2_data                   : std_logic_vector(  7 DOWNTO 0 );
587 
   SIGNAL s_fx2_n_tri                  : std_logic_vector(  7 DOWNTO 0 );
588 
   SIGNAL s_start_scpi_command         : std_logic;
589 
   SIGNAL s_scpi_command_id            : std_logic_vector(  6 DOWNTO 0 );
590 
   SIGNAL s_scpi_command_done          : std_logic;
591 
   SIGNAL s_cmd_09_done                : std_logic;
592 
   SIGNAL s_cmd_09_push                : std_logic;
593 
   SIGNAL s_cmd_09_push_data           : std_logic_vector(  7 DOWNTO 0 );
594 
   SIGNAL s_cmd_09_push_size           : std_logic;
595 
   SIGNAL s_cmd_25_done                : std_logic;
596 
   SIGNAL s_pending_message            : std_logic;
597 
 
598 
   SIGNAL s_leds_a                     : std_logic_vector(  7 DOWNTO 0 );
599 
   SIGNAL s_leds_k                     : std_logic_vector(  7 DOWNTO 0 );
600 
 
601 
   SIGNAL s_fifo_data                  : std_logic_vector(  7 DOWNTO 0 );
602 
   SIGNAL s_fifo_empty                 : std_logic;
603 
   SIGNAL s_fifo_pop                   : std_logic;
604 
   SIGNAL s_fifo_last                  : std_logic;
605 
 
606 
   SIGNAL s_fpga_revision              : std_logic_vector(  3 DOWNTO 0 );
607 
   SIGNAL s_fpga_type                  : std_logic_vector(  2 DOWNTO 0 );
608 
   SIGNAL s_fpga_configured            : std_logic;
609 
   SIGNAL s_reset_fpga_if              : std_logic;
610 
   SIGNAL s_fpga_data_in_ena           : std_logic;
611 
   SIGNAL s_fpga_data_out_ena          : std_logic;
612 
   SIGNAL s_fpga_data_in               : std_logic_vector(  7 DOWNTO 0 );
613 
   SIGNAL s_fpga_data_out              : std_logic_vector(  7 DOWNTO 0 );
614 
   SIGNAL s_fpga_n_tri                 : std_logic_vector(  7 DOWNTO 0 );
615 
   SIGNAL s_fpga_data_out_reg          : std_logic_vector(  7 DOWNTO 0 );
616 
   SIGNAL s_fpga_n_tri_reg             : std_logic_vector(  7 DOWNTO 0 );
617 
   SIGNAL s_fpga_crc_error             : std_logic;
618 
 
619 
   SIGNAL s_fpga_fifo_push             : std_logic;
620 
   SIGNAL s_fpga_fifo_push_data        : std_logic_vector(  7 DOWNTO 0 );
621 
   SIGNAL s_fpga_fifo_last_byte        : std_logic;
622 
   SIGNAL s_fpga_fifo_full             : std_logic;
623 
   SIGNAL s_fpga_idle                  : std_logic;
624 
 
625 
   SIGNAL s_bitfile_pop                : std_logic;
626 
   SIGNAL s_bitfile_u_pop              : std_logic;
627 
   SIGNAL s_bitfile_done               : std_logic;
628 
   SIGNAL s_bitfile_start              : std_logic;
629 
   SIGNAL s_bitfile_u_start            : std_logic;
630 
   SIGNAL s_bitfile_pop_data           : std_logic_vector( 7 DOWNTO 0 );
631 
   SIGNAL s_bitfile_last               : std_logic;
632 
   SIGNAL s_bitfile_fifo_empty         : std_logic;
633 
 
634 
   SIGNAL s_bitfile_error              : std_logic;
635 
 
636 
   SIGNAL s_bitfile_size               : std_logic_vector(31 DOWNTO 0 );
637 
   SIGNAL s_we_fifo                    : std_logic;
638 
   SIGNAL s_we_data                    : std_logic_vector( 7 DOWNTO 0 );
639 
   SIGNAL s_we_last                    : std_logic;
640 
   SIGNAL s_we_fifo_full               : std_logic;
641 
   SIGNAL s_start_write                : std_logic;
642 
   SIGNAL s_flash_data_out             : std_logic_vector(15 DOWNTO 0 );
643 
   SIGNAL s_flash_data_oe              : std_logic_vector(15 DOWNTO 0 );
644 
 
645 
   SIGNAL s_start_erase                : std_logic;
646 
   SIGNAL s_start_read                 : std_logic;
647 
   SIGNAL s_start_flash_read           : std_logic;
648 
   SIGNAL s_prog_flash                 : std_logic;
649 
   SIGNAL s_flash_present              : std_logic;
650 
   SIGNAL s_flash_s1_empty             : std_logic;
651 
   SIGNAL s_flash_idle                 : std_logic;
652 
   SIGNAL s_flash_n_busy               : std_logic;
653 
   SIGNAL s_size_error                 : std_logic;
654 
   SIGNAL s_flash_push                 : std_logic;
655 
   SIGNAL s_flash_push_data            : std_logic_vector( 7 DOWNTO 0 );
656 
   SIGNAL s_flash_push_size            : std_logic;
657 
   SIGNAL s_flash_push_last            : std_logic;
658 
   SIGNAL s_flash_fifo_full            : std_logic;
659 
   SIGNAL s_flash_u_push               : std_logic;
660 
   SIGNAL s_flash_u_push_data          : std_logic_vector( 7 DOWNTO 0 );
661 
   SIGNAL s_flash_u_push_size          : std_logic;
662 
   SIGNAL s_flash_done                 : std_logic;
663 
   SIGNAL s_flash_u_done               : std_logic;
664 
 
665 
   SIGNAL s_cmd_18_1e_done             : std_logic;
666 
   SIGNAL s_cmd_18_1e_push             : std_logic;
667 
   SIGNAL s_cmd_18_1e_size             : std_logic;
668 
   SIGNAL s_cmd_18_1e_data             : std_logic_vector( 7 DOWNTO 0 );
669 
 
670 
   SIGNAL s_system_reset_done          : std_logic;
671 
   SIGNAL s_vga_command_done           : std_logic;
672 
   SIGNAL s_vga_command_error          : std_logic;
673 
   SIGNAL s_scpi_command_error         : std_logic;
674 
   SIGNAL s_vga_pop                    : std_logic;
675 
   SIGNAL s_custom_pop                 : std_logic;
676 
   SIGNAL s_vga_push                   : std_logic;
677 
   SIGNAL s_vga_push_data              : std_logic_vector( 7 DOWNTO 0 );
678 
   SIGNAL s_vga_push_size              : std_logic;
679 
   SIGNAL s_config_error               : std_logic;
680 
   SIGNAL s_pud_pop                    : std_logic;
681 
   SIGNAL s_pud_push                   : std_logic;
682 
   SIGNAL s_pud_push_data              : std_logic_vector( 7 DOWNTO 0 );
683 
   SIGNAL s_pud_push_size              : std_logic;
684 
   SIGNAL s_hex_switch                 : std_logic_vector( 3 DOWNTO 0 );
685 
   SIGNAL s_hex_error                  : std_logic;
686 
   SIGNAL s_hex_done                   : std_logic;
687 
   SIGNAL s_hex_pop                    : std_logic;
688 
   SIGNAL s_hex_push                   : std_logic;
689 
   SIGNAL s_hex_push_data              : std_logic_vector( 7 DOWNTO 0 );
690 
   SIGNAL s_hex_push_size              : std_logic;
691 
   SIGNAL s_pud_we                     : std_logic;
692 
   SIGNAL s_pud_data                   : std_logic_vector( 7 DOWNTO 0 );
693 
   SIGNAL s_pud_addr                   : std_logic_vector(10 DOWNTO 0 );
694 
   SIGNAL s_status_error               : std_logic;
695 
   SIGNAL s_status_done                : std_logic;
696 
   SIGNAL s_trans_mode                 : std_logic;
697 
   SIGNAL s_status_pop                 : std_logic;
698 
   SIGNAL s_status_push                : std_logic;
699 
   SIGNAL s_status_push_data           : std_logic_vector( 7 DOWNTO 0 );
700 
   SIGNAL s_status_push_size           : std_logic;
701 
   SIGNAL s_unknown_command            : std_logic;
702 
 
703 
   SIGNAL s_status_nibble              : std_logic_vector( 3 DOWNTO 0 );
704 
   SIGNAL s_fx2_data_nibble            : std_logic_vector( 3 DOWNTO 0 );
705 
   SIGNAL s_indicator_pulse            : std_logic;
706 
 
707 
   SIGNAL s_b_n_reset                  : std_logic;
708 
   SIGNAL s_b_n_start_transmission     : std_logic;
709 
   SIGNAL s_b_n_end_transmission_out   : std_logic;
710 
   SIGNAL s_b_n_end_transmission_in    : std_logic;
711 
   SIGNAL s_b_n_data_valid_out         : std_logic_vector( 1 DOWNTO 0 );
712 
   SIGNAL s_b_n_data_valid_in          : std_logic_vector( 1 DOWNTO 0 );
713 
   SIGNAL s_b_data_out                 : std_logic_vector(15 DOWNTO 0 );
714 
   SIGNAL s_b_data_in                  : std_logic_vector(15 DOWNTO 0 );
715 
   SIGNAL s_b_read_n_write             : std_logic;
716 
   SIGNAL s_b_burst_size               : std_logic_vector( 8 DOWNTO 0 );
717 
   SIGNAL s_b_address                  : std_logic_vector( 5 DOWNTO 0 );
718 
   SIGNAL s_b_n_start_send             : std_logic;
719 
   SIGNAL s_b_n_bus_error              : std_logic;
720 
 
721 
   SIGNAL s_vga_cursor_pos             : std_logic_vector( 10 DOWNTO 0 );
722 
   SIGNAL s_vga_screen_offset          : std_logic_vector(  4 DOWNTO 0 );
723 
   SIGNAL s_vga_fg_color               : std_logic_vector(  2 DOWNTO 0 );
724 
   SIGNAL s_vga_bg_color               : std_logic_vector(  2 DOWNTO 0 );
725 
   SIGNAL s_vga_write_address          : std_logic_vector( 10 DOWNTO 0 );
726 
   SIGNAL s_vga_ascii_data             : std_logic_vector(  7 DOWNTO 0 );
727 
   SIGNAL s_vga_we                     : std_logic;
728 
   SIGNAL s_vga_n_end_transmission_out : std_logic;
729 
   SIGNAL s_vga_n_data_valid_out       : std_logic_vector(  1 DOWNTO 0 );
730 
   SIGNAL s_vga_data_out               : std_logic_vector( 15 DOWNTO 0 );
731 
   SIGNAL s_vga_n_start_send           : std_logic;
732 
   SIGNAL s_vga_n_bus_error            : std_logic;
733 
 
734 
   SIGNAL s_ufifo_push                 : std_logic;
735 
   SIGNAL s_ufifo_push_size            : std_logic;
736 
   SIGNAL s_ufifo_push_data            : std_logic_vector(  7 DOWNTO 0 );
737 
   SIGNAL s_ufifo_error                : std_logic;
738 
   SIGNAL s_ufifo_done                 : std_logic;
739 
   SIGNAL s_ufifo_n_error              : std_logic;
740 
   SIGNAL s_ufifo_n_start              : std_logic;
741 
   SIGNAL s_ufifo_data                 : std_logic_vector( 15 DOWNTO 0 );
742 
   SIGNAL s_ufifo_n_valid              : std_logic_vector(  1 DOWNTO 0 );
743 
   SIGNAL s_ufifo_n_end                : std_logic;
744 
   SIGNAL s_ufifo_pop                  : std_logic;
745 
   SIGNAL s_ufifo_msg_avail            : std_logic;
746 
   SIGNAL s_scpi_msg_avail             : std_logic;
747 
 
748 
   SIGNAL s_start_config               : std_logic;
749 
 
750 
BEGIN
751 
 
752 
-- Assign outputs
753 
   gen_fx_data : FOR n IN 7 DOWNTO 0 GENERATE
754 
      fx2_data(n) <= s_fx2_data(n) WHEN s_fx2_n_tri(n) = '0' ELSE 'Z';
755 
   END GENERATE gen_fx_data;
756 
 
757 
   fx2_data_nibble <= s_fx2_data_nibble WHEN fx2_pa1 = '0'
758 
                                             AND s_b_n_data_valid_out(1) = '1' -- DUMMY: REMOVE AFTERWARDS!
759 
                                             ELSE (OTHERS => 'Z');
760 
 
761 
   red           <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_red   ;
762 
   green         <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_green ;
763 
   blue          <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_blue  ;
764 
   hsync         <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_hsync ;
765 
   vsync         <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_vsync ;
766 
   SDA           <= s_SDA_pin WHEN s_SDA_OE = '0' ELSE 'Z';
767 
   fx2_n_int0    <= s_reset;
768 
   RxD_out       <= RxD_in;
769 
   TxD_out       <= 'Z' when jtag_ndet = '0' ELSE TxD_in ;
770 
   scpi_disabled <= s_trans_mode;
771 
 
772 
-- Assign control signals
773 
   s_n_usb_clk            <= NOT(s_usb_clk);
774 
   s_bitfile_u_start      <= '1' WHEN s_start_scpi_command = '1' AND
775 
                                      (s_scpi_command_id = "0011101" OR
776 
                                       s_scpi_command_id = "0010110") ELSE '0';
777 
   s_prog_flash           <= '1' WHEN s_scpi_command_id = "0010110" ELSE '0';
778 
   s_start_erase          <= '1' WHEN s_start_scpi_command = '1' AND
779 
                                      s_scpi_command_id = "0011010" ELSE '0';
780 
   s_start_read           <= '1' WHEN s_start_scpi_command = '1' AND
781 
                                      s_scpi_command_id = "0010111" ELSE '0';
782 
 
783 
   s_wf_push              <= s_flash_u_push OR s_cmd_09_push OR s_cmd_18_1e_push OR
784 
                             s_vga_push OR s_pud_push OR s_hex_push OR
785 
                             s_status_push OR s_ufifo_push;
786 
   s_wf_push_data         <= s_flash_u_push_data OR s_cmd_09_push_data OR
787 
                             s_cmd_18_1e_data OR s_vga_push_data OR
788 
                             s_pud_push_data OR s_hex_push_data OR
789 
                             s_status_push_data OR s_ufifo_push_data;
790 
   s_wf_push_size_bit     <= s_flash_u_push_size OR s_cmd_09_push_size OR
791 
                             s_cmd_18_1e_size OR s_vga_push_size OR
792 
                             s_pud_push_size OR s_hex_push_size OR
793 
                             s_status_push_size OR s_ufifo_push_size;
794 
 
795 
   s_scpi_command_done    <= s_cmd_09_done OR s_cmd_25_done OR s_bitfile_done OR
796 
                             s_flash_u_done OR s_cmd_18_1e_done OR s_hex_done OR
797 
                             s_system_reset_done OR s_vga_command_done OR
798 
                             s_status_done OR s_ufifo_done;
799 
   s_scpi_command_error   <= s_vga_command_error OR s_bitfile_error OR
800 
                             s_config_error OR s_hex_error OR s_status_error OR
801 
                             s_ufifo_error OR s_size_error;
802 
   s_custom_pop           <= s_vga_pop OR s_bitfile_u_pop OR s_pud_pop OR
803 
                             s_hex_pop OR s_status_pop OR s_ufifo_pop;
804 
 
805 
-- Map components
806 
   clockgen : clocks
807 
              PORT MAP ( system_n_reset    => n_reset_system,
808 
                         clock_25MHz       => clock_25MHz,
809 
                         clock_16MHz       => clock_16MHz,
810 
                         user_clock_1      => user_clock_1_in,
811 
                         user_clock_2      => user_clock_2_in,
812 
                         -- Here the compensated clocks are defined
813 
                         user_clock_1_out  => user_clock_1_out,
814 
                         user_clock_1_fb   => user_clock_1_fb,
815 
                         user_clock_1_lock => user_clock_1_lock,
816 
                         user_clock_2_out  => user_clock_2_out,
817 
                         user_clock_2_fb   => user_clock_2_fb,
818 
                         user_clock_2_lock => user_clock_2_lock,
819 
                         -- Here the master clocks are defined
820 
                         clock_25MHz_out   => clock_25MHz_out,
821 
                         clock_48MHz_out   => clock_48MHz_out,
822 
                         -- Here the FPGA internal clocks are defined
823 
                         clk_48MHz         => s_clk_48MHz,
824 
                         clk_96MHz         => s_clock_96MHz,
825 
                         clk_75MHz         => s_clock_75MHz,
826 
                         reset_out         => s_reset,
827 
                         msec_tick         => s_msec_tick );
828 
 
829 
   usb_dff_1 : DFF
830 
               PORT MAP ( clock => s_clk_48MHz,
831 
                          D     => s_n_usb_clk,
832 
                          Q     => s_usb_clk );
833 
   usb_dff_2 : DFF
834 
               PORT MAP ( clock => s_clk_48MHz,
835 
                          D     => s_usb_clk,
836 
                          Q     => fx2_clk );
837 
 
838 
   SDA_ff : DFF
839 
            PORT MAP ( clock => clock_16MHz,
840 
                       D     => s_SDA,
841 
                       Q     => s_SDA_pin );
842 
   SDA_oe_ff : DFF
843 
               PORT MAP ( clock => clock_16MHz,
844 
                          D     => s_SDA,
845 
                          Q     => s_SDA_OE );
846 
 
847 
   i2c : eeprom_emu
848 
         PORT MAP ( clock     => clock_16MHz,
849 
                    reset     => s_reset,
850 
                    button    => button3,
851 
                    SDA_in    => SDA,
852 
                    SCL_in    => SCL,
853 
                    SDA_out   => s_SDA );
854 
 
855 
 
856 
   s_b_n_end_transmission_in <= s_vga_n_end_transmission_out AND s_ufifo_n_end;
857 
   s_b_n_data_valid_in       <= s_vga_n_data_valid_out AND s_ufifo_n_valid;
858 
   s_b_data_in               <= s_vga_data_out OR s_ufifo_data;
859 
   s_b_n_start_send          <= s_vga_n_start_send AND s_ufifo_n_start;
860 
   s_b_n_bus_error           <= s_vga_n_bus_error AND s_ufifo_n_error;
861 
 
862 
   the_bus : bus_if
863 
             PORT MAP ( clock                    => s_clk_48MHz,
864 
                        reset                    => s_reset,
865 
                        -- Here the IOB interface is defined
866 
                        bus_reset                => bus_reset               ,
867 
                        bus_n_start_transmission => bus_n_start_transmission,
868 
                        bus_n_end_transmission   => bus_n_end_transmission  ,
869 
                        bus_n_data_valid         => bus_n_data_valid        ,
870 
                        bus_data_addr_cntrl      => bus_data_addr_cntrl     ,
871 
                        bus_n_start_send         => bus_n_start_send        ,
872 
                        bus_n_error              => bus_n_error             ,
873 
                        -- Here the FPGA internal interface is defined
874 
                        b_n_reset                => s_b_n_reset               ,
875 
                        b_n_start_transmission   => s_b_n_start_transmission  ,
876 
                        b_n_end_transmission_out => s_b_n_end_transmission_out,
877 
                        b_n_end_transmission_in  => s_b_n_end_transmission_in ,
878 
                        b_n_data_valid_out       => s_b_n_data_valid_out      ,
879 
                        b_n_data_valid_in        => s_b_n_data_valid_in       ,
880 
                        data_out                 => s_b_data_out              ,
881 
                        data_in                  => s_b_data_in               ,
882 
                        read_n_write             => s_b_read_n_write          ,
883 
                        burst_size               => s_b_burst_size            ,
884 
                        address                  => s_b_address               ,
885 
                        n_start_send             => s_b_n_start_send          ,
886 
                        n_bus_error              => s_b_n_bus_error           );
887 
   fifo_if : user_fifo
888 
             PORT MAP ( clock                  => s_clk_48MHz,
889 
                        reset                  => s_usb_reset,
890 
                        -- Here the bus signals are defined
891 
                        n_bus_reset            => s_b_n_reset,
892 
                        n_start_transmission   => s_b_n_start_transmission,
893 
                        n_end_transmission_in  => s_b_n_end_transmission_out,
894 
                        n_end_transmission_out => s_ufifo_n_end,
895 
                        n_data_valid_in        => s_b_n_data_valid_out,
896 
                        n_data_valid_out       => s_ufifo_n_valid,
897 
                        data_in                => s_b_data_out,
898 
                        data_out               => s_ufifo_data,
899 
                        read_n_write           => s_b_read_n_write,
900 
                        burst_size             => s_b_burst_size,
901 
                        bus_address            => s_b_address,
902 
                        n_start_send           => s_ufifo_n_start,
903 
                        n_bus_error            => s_ufifo_n_error,
904 
                        -- Here the scpi interface is defined
905 
                        start_command          => s_start_scpi_command,
906 
                        command_id             => s_scpi_command_id,
907 
                        transparent_mode       => s_trans_mode,
908 
                        command_done           => s_ufifo_done,
909 
                        command_error          => s_ufifo_error,
910 
                        message_available      => s_ufifo_msg_avail,
911 
                        -- Here the tx_fifo is defined
912 
                        push                   => s_ufifo_push,
913 
                        push_size              => s_ufifo_push_size,
914 
                        push_data              => s_ufifo_push_data,
915 
                        fifo_full              => s_wf_fifo_full,
916 
                        -- Here the rx_fifo is defined
917 
                        pop                    => s_ufifo_pop,
918 
                        pop_last               => s_fifo_last,
919 
                        pop_data               => s_fifo_data,
920 
                        pop_empty              => s_fifo_empty,
921 
                        -- Here the big fpga interface is defined
922 
                        data_request_irq       => data_request_irq,
923 
                        data_available_irq     => data_available_irq,
924 
                        error_irq              => error_irq);
925 
 
926 
   vga_bus_if : vga_bus
927 
                PORT MAP ( clock                  => s_clk_48MHz,
928 
                           reset                  => s_reset,
929 
                           msec_tick              => s_msec_tick,
930 
                           -- Here the bus signals are defined
931 
                           n_bus_reset            => s_b_n_reset,
932 
                           n_start_transmission   => s_b_n_start_transmission,
933 
                           n_end_transmission_in  => s_b_n_end_transmission_out,
934 
                           n_end_transmission_out => s_vga_n_end_transmission_out,
935 
                           n_data_valid_in        => s_b_n_data_valid_out(0),
936 
                           n_data_valid_out       => s_vga_n_data_valid_out,
937 
                           data_in                => s_b_data_out( 7 DOWNTO 0 ),
938 
                           data_out               => s_vga_data_out,
939 
                           read_n_write           => s_b_read_n_write,
940 
                           burst_size             => s_b_burst_size,
941 
                           bus_address            => s_b_address,
942 
                           n_start_send           => s_vga_n_start_send,
943 
                           n_bus_error            => s_vga_n_bus_error,
944 
                           -- Here the button interface is defined
945 
                           n_button_1             => button1,
946 
                           n_button_2             => button2,
947 
                           n_button_3             => button3,
948 
                           hexswitch              => s_hex_switch,
949 
                           -- Here the LED interface is defined
950 
                           leds_a                 => s_leds_a,
951 
                           leds_k                 => s_leds_k,
952 
                           -- Here the VGA interface is defined
953 
                           cursor_pos             => s_vga_cursor_pos   ,
954 
                           screen_offset          => s_vga_screen_offset,
955 
                           fg_color               => s_vga_fg_color     ,
956 
                           bg_color               => s_vga_bg_color     ,
957 
                           write_address          => s_vga_write_address,
958 
                           ascii_data             => s_vga_ascii_data   ,
959 
                           we                     => s_vga_we           );
960 
 
961 
 
962 
   status : status_controller
963 
            PORT MAP ( clock           => s_clk_48MHz,
964 
                       reset           => s_usb_reset,
965 
                       fpga_configured => s_fpga_configured,
966 
                       -- Here the fx2 interface is defined
967 
                       status_nibble   => s_status_nibble,
968 
                       -- Here the external status if is defined
969 
                       ESB_bit         => ESB_bit,
970 
                       STATUS3_bit     => STATUS3_bit,
971 
                       -- Here the scpi interface is defined
972 
                       start           => s_start_scpi_command,
973 
                       command         => s_scpi_command_id,
974 
                       cmd_error       => s_status_error,
975 
                       command_error   => s_unknown_command,
976 
                       execution_error => s_scpi_command_error,
977 
                       done            => s_status_done,
978 
                       transparent     => s_trans_mode,
979 
                       pop             => s_status_pop,
980 
                       pop_data        => s_fifo_data,
981 
                       pop_last        => s_fifo_last,
982 
                       pop_empty       => s_fifo_empty,
983 
                       push            => s_status_push,
984 
                       push_data       => s_status_push_data,
985 
                       push_size       => s_status_push_size,
986 
                       push_full       => s_wf_fifo_full,
987 
                       push_empty      => s_wf_fifo_empty );
988 
 
989 
   s_pending_message <= s_ufifo_msg_avail OR s_scpi_msg_avail;
990 
   fx2 : USBTMC
991 
         PORT MAP ( clock_96MHz      => s_clock_96MHz,
992 
                    clock_48MHz      => s_clk_48MHz,
993 
                    cpu_reset        => s_reset,
994 
                    sync_reset_out   => s_usb_reset,
995 
                    -- SCPI command interpretor interface
996 
                    pending_message  => s_pending_message,
997 
                    transfer_in_prog => OPEN,
998 
                    -- FX2 control interface
999 
                    FX2_n_ready      => fx2_pa1,
1000 
                    FX2_hi_speed     => fx2_pa3,
1001 
                    -- read fifo interface
1002 
                    rf_pop           => s_fifo_pop,
1003 
                    rf_pop_data      => s_fifo_data,
1004 
                    rf_last_data_byte=> s_fifo_last,
1005 
                    rf_fifo_empty    => s_fifo_empty,
1006 
                    -- Write fifo interface
1007 
                    wf_push          => s_wf_push         ,
1008 
                    wf_push_data     => s_wf_push_data    ,
1009 
                    wf_push_size_bit => s_wf_push_size_bit,
1010 
                    wf_fifo_full     => s_wf_fifo_full    ,
1011 
                    wf_fifo_empty    => s_wf_fifo_empty   ,
1012 
                    -- status interface
1013 
                    status_nibble    => s_status_nibble,
1014 
                    indicator_pulse  => s_indicator_pulse,
1015 
                    -- FX2 port D interface
1016 
                    data_nibble      => s_fx2_data_nibble,
1017 
                    data_select      => fx2_data_select,
1018 
                    -- FX2 FIFO interface
1019 
                    EP8_n_empty      => fx2_flaga,
1020 
                    EP6_n_full       => fx2_flagb,
1021 
                    EP_data_in       => fx2_data,
1022 
                    EP_address       => fx2_fifo_addr,
1023 
                    EP_IFCLOCK       => fx2_ifclock,
1024 
                    EP_n_PKTEND      => fx2_n_pkt_end,
1025 
                    EP_n_OE          => fx2_n_oe,
1026 
                    EP_n_RE          => fx2_n_re,
1027 
                    EP_n_WE          => fx2_n_we,
1028 
                    EP_data_out      => s_fx2_data,
1029 
                    EP_n_tri_out     => s_fx2_n_tri);
1030 
 
1031 
   vga : vga_controller
1032 
         PORT MAP ( clock_75MHz         => s_clock_75MHz,
1033 
                    reset               => s_reset,
1034 
                    vga_off             => s_reset,
1035 
                    clock               => s_clk_48MHz,
1036 
                    -- Here the scpi interface is defined
1037 
                    start_command       => s_start_scpi_command,
1038 
                    command_id          => s_scpi_command_id,
1039 
                    command_done        => s_vga_command_done,
1040 
                    command_error       => s_vga_command_error,
1041 
                    -- Here the usbtmc fifo interface is defined
1042 
                    pop                 => s_vga_pop,
1043 
                    pop_data            => s_fifo_data,
1044 
                    pop_last            => s_fifo_last,
1045 
                    pop_empty           => s_fifo_empty,
1046 
                    push                => s_vga_push,
1047 
                    push_data           => s_vga_push_data,
1048 
                    push_size           => s_vga_push_size,
1049 
                    push_full           => s_wf_fifo_full,
1050 
                    -- Here the PUD interface is defined
1051 
                    we_char             => s_pud_we,
1052 
                    we_ascii            => s_pud_data,
1053 
                    we_addr             => s_pud_addr,
1054 
                    -- Here the fpga interface is defined
1055 
                    cursor_pos          => s_vga_cursor_pos   ,
1056 
                    screen_offset       => s_vga_screen_offset,
1057 
                    fg_color            => s_vga_fg_color     ,
1058 
                    bg_color            => s_vga_bg_color     ,
1059 
                    write_address       => s_vga_write_address,
1060 
                    ascii_data          => s_vga_ascii_data   ,
1061 
                    we                  => s_vga_we           ,
1062 
                    vga_red             => s_vga_red   ,
1063 
                    vga_green           => s_vga_green ,
1064 
                    vga_blue            => s_vga_blue  ,
1065 
                    vga_hsync           => s_vga_hsync ,
1066 
                    vga_vsync           => s_vga_vsync );
1067 
 
1068 
   scpi : SCPI_INTERFACE
1069 
          PORT MAP ( clock            => s_clk_48MHz,
1070 
                     reset            => s_usb_reset,
1071 
                     -- The command interface
1072 
                     transparent_mode => s_trans_mode,
1073 
                     start_command    => s_start_scpi_command,
1074 
                     command_id       => s_scpi_command_id,
1075 
                     cmd_gen_respons  => s_scpi_msg_avail,
1076 
                     command_done     => s_scpi_command_done,
1077 
                     command_error    => s_scpi_command_error,
1078 
                     unknown_command  => s_unknown_command,
1079 
                     slave_pop        => s_custom_pop,
1080 
                     -- USBTMC fifo interface
1081 
                     pop              => s_fifo_pop,
1082 
                     pop_data         => s_fifo_data,
1083 
                     pop_empty        => s_fifo_empty,
1084 
                     pop_last         => s_fifo_last);
1085 
 
1086 
   cmd_18_1e : cmd_18_1e_if
1087 
               PORT MAP ( clock           => s_clk_48MHz,
1088 
                          reset           => s_usb_reset,
1089 
                          -- Here the scpi interface is defined
1090 
                          start_command   => s_start_scpi_command,
1091 
                          command_id      => s_scpi_command_id,
1092 
                          command_done    => s_cmd_18_1e_done,
1093 
                          -- Here the tx_fifo is defined
1094 
                          push            => s_cmd_18_1e_push,
1095 
                          push_size       => s_cmd_18_1e_size,
1096 
                          push_data       => s_cmd_18_1e_data,
1097 
                          fifo_full       => s_wf_fifo_full,
1098 
                          -- Here the fpga_if is defined
1099 
                          fpga_type       => s_fpga_type,
1100 
                          fpga_configured => s_fpga_configured,
1101 
                          flash_empty     => s_flash_s1_empty,
1102 
                          -- Here the board interface is defined
1103 
                          n_usb_power     => n_usb_power,
1104 
                          n_bus_power     => n_bus_power,
1105 
                          n_usb_charge    => n_usb_charge);
1106 
 
1107 
   cmd_09 : IDN_handler
1108 
            PORT MAP ( clock     => s_clk_48MHz,
1109 
                       reset     => s_usb_reset,
1110 
                       start     => s_start_scpi_command,
1111 
                       command   => s_scpi_command_id,
1112 
                       fifo_full => s_wf_fifo_full,
1113 
                       done      => s_cmd_09_done,
1114 
                       push      => s_cmd_09_push,
1115 
                       size_bit  => s_cmd_09_push_size,
1116 
                       push_data => s_cmd_09_push_data );
1117 
   cmd_25 : identify_handler
1118 
            PORT MAP ( clock       => s_clk_48MHz,
1119 
                       reset       => s_reset,
1120 
                       start       => s_start_scpi_command,
1121 
                       command     => s_scpi_command_id,
1122 
                       indicator   => s_indicator_pulse,
1123 
                       done        => s_cmd_25_done,
1124 
                       flash_idle  => s_flash_n_busy,
1125 
                       msec_tick   => s_msec_tick,
1126 
                       leds_a_in   => s_leds_a,
1127 
                       leds_k_in   => s_leds_k,
1128 
                       leds_a      => leds_a,
1129 
                       leds_k      => leds_k);
1130 
   cmd_23_24 : hexswitch
1131 
               PORT MAP ( clock         => s_clk_48MHz,
1132 
                          reset         => s_usb_reset,
1133 
                          n_hex_sw      => n_hex_switch,
1134 
                          hex_value     => s_hex_switch,
1135 
                          -- here the scpi interface is defined
1136 
                          start         => s_start_scpi_command,
1137 
                          command       => s_scpi_command_id,
1138 
                          command_error => s_hex_error,
1139 
                          done          => s_hex_done,
1140 
                          pop           => s_hex_pop,
1141 
                          pop_data      => s_fifo_data,
1142 
                          pop_last      => s_fifo_last,
1143 
                          pop_empty     => s_fifo_empty,
1144 
                          push          => s_hex_push,
1145 
                          push_data     => s_hex_push_data,
1146 
                          push_size     => s_hex_push_size,
1147 
                          push_full     => s_wf_fifo_full );
1148 
 
1149 
 
1150 
   system_reset : reset_if
1151 
                  PORT MAP ( clock          => s_clk_48MHz,
1152 
                             reset          => s_reset,
1153 
                             msec_tick      => s_msec_tick,
1154 
                             -- Here the fpga_interface is defined
1155 
                             fpga_configured=> s_fpga_configured,
1156 
                             -- Here the scpi interface is defined
1157 
                             start_command  => s_start_scpi_command,
1158 
                             command_id     => s_scpi_command_id,
1159 
                             command_done   => s_system_reset_done,
1160 
                             -- Here the system reset is defined
1161 
                             n_reset_system => n_reset_system,
1162 
                             user_n_reset   => user_n_reset );
1163 
 
1164 
 
1165 
--------------------------------------------------------------------------------
1166 
--- Here the FPGA interface is defined                                       ---
1167 
--- NOTE: The FPGA data pins have dual function; however the configuration   ---
1168 
---       Interface MUST have priority                                       ---
1169 
--------------------------------------------------------------------------------
1170 
   config : config_if
1171 
            PORT MAP ( clock                  => s_clk_48MHz,
1172 
                       reset                  => s_reset_fpga_if,
1173 
                       -- here the flash interface is defined
1174 
                       start_config           => s_start_config,
1175 
                       flash_start_read       => s_start_flash_read,
1176 
                       flash_done             => s_flash_done,
1177 
                       flash_present          => s_flash_present,
1178 
                       flash_s1_empty         => s_flash_s1_empty,
1179 
                       flash_idle             => s_flash_idle,
1180 
                       flash_push             => s_flash_push,
1181 
                       flash_push_data        => s_flash_push_data,
1182 
                       flash_push_size        => s_flash_push_size,
1183 
                       flash_push_last        => s_flash_push_last,
1184 
                       flash_fifo_full        => s_flash_fifo_full,
1185 
                       -- here the flash usbtmc interface is defined
1186 
                       flash_u_start_read     => s_start_read,
1187 
                       flash_u_done           => s_flash_u_done,
1188 
                       flash_u_push           => s_flash_u_push,
1189 
                       flash_u_push_data      => s_flash_u_push_data,
1190 
                       flash_u_push_size      => s_flash_u_push_size,
1191 
                       flash_u_fifo_full      => s_wf_fifo_full,
1192 
                       -- here the bitfile interface is defined
1193 
                       bitfile_start          => s_bitfile_start,
1194 
                       bitfile_pop            => s_bitfile_pop,
1195 
                       bitfile_pop_data       => s_bitfile_pop_data,
1196 
                       bitfile_last           => s_bitfile_last,
1197 
                       bitfile_fifo_empty     => s_bitfile_fifo_empty,
1198 
                       -- here the bitfile usbtmc interface is defined
1199 
                       bitfile_u_start        => s_bitfile_u_start,
1200 
                       bitfile_u_pop          => s_bitfile_u_pop,
1201 
                       bitfile_u_pop_data     => s_fifo_data,
1202 
                       bitfile_u_last         => s_fifo_last,
1203 
                       bitfile_u_fifo_empty   => s_fifo_empty,
1204 
                       -- here the fpga interface is defined
1205 
                       fpga_idle              => s_fpga_idle,
1206 
                       fpga_type              => s_fpga_type,
1207 
                       -- here the power interface is defined
1208 
                       n_bus_power            => n_bus_power,
1209 
                       -- here the scpi interface is defined
1210 
                       start_command          => s_start_scpi_command,
1211 
                       command_id             => s_scpi_command_id,
1212 
                       command_error          => s_config_error );
1213 
 
1214 
 
1215 
   fpga : fpga_if
1216 
          PORT MAP ( clock             => s_clk_48MHz,
1217 
                     reset             => s_reset_fpga_if,
1218 
                     -- Here the FPGA info is provided
1219 
                     fpga_idle         => s_fpga_idle,
1220 
                     fpga_revision     => s_fpga_revision,
1221 
                     fpga_type         => s_fpga_type,
1222 
                     fpga_configured   => s_fpga_configured,
1223 
                     fpga_crc_error    => s_fpga_crc_error,
1224 
                     -- Here the bitfile fifo if is defined
1225 
                     push              => s_fpga_fifo_push,
1226 
                     push_data         => s_fpga_fifo_push_data,
1227 
                     last_byte         => s_fpga_fifo_last_byte,
1228 
                     fifo_full         => s_fpga_fifo_full,
1229 
                     -- Here the select map pins are defined
1230 
                     fpga_done         => fpga_done,
1231 
                     fpga_busy         => fpga_busy,
1232 
                     fpga_n_init       => fpga_n_init,
1233 
                     fpga_n_prog       => fpga_n_prog,
1234 
                     fpga_rd_n_wr      => fpga_rd_n_wr,
1235 
                     fpga_n_cs         => fpga_n_cs,
1236 
                     fpga_cclk         => fpga_cclk,
1237 
                     fpga_data_in      => s_fpga_data_in,
1238 
                     fpga_data_out     => s_fpga_data_out,
1239 
                     fpga_n_tri        => s_fpga_n_tri,
1240 
                     fpga_data_in_ena  => s_fpga_data_in_ena,
1241 
                     fpga_data_out_ena => s_fpga_data_out_ena);
1242 
   bitfile : bitfile_interpreter
1243 
             PORT MAP ( clock                 => s_clk_48MHz,
1244 
                        reset                 => s_usb_reset,
1245 
                        msec_tick             => s_msec_tick,
1246 
                        -- Here the handshake interface is defined
1247 
                        start                 => s_bitfile_start,
1248 
                        write_flash           => s_prog_flash,
1249 
                        done                  => s_bitfile_done,
1250 
                        error_detected        => s_bitfile_error,
1251 
                        -- Here the FX2 fifo interface is defined
1252 
                        pop                   => s_bitfile_pop,
1253 
                        pop_data              => s_bitfile_pop_data,
1254 
                        pop_last              => s_bitfile_last,
1255 
                        fifo_empty            => s_bitfile_fifo_empty,
1256 
                        -- Here the FPGA_IF fifo interface is defined
1257 
                        push                  => s_fpga_fifo_push,
1258 
                        push_data             => s_fpga_fifo_push_data,
1259 
                        last_byte             => s_fpga_fifo_last_byte,
1260 
                        fifo_full             => s_fpga_fifo_full,
1261 
                        reset_fpga_if         => s_reset_fpga_if,
1262 
                        -- Here the flash write fifo interface is defined
1263 
                        bitfile_size          => s_bitfile_size,
1264 
                        we_fifo               => s_we_fifo     ,
1265 
                        we_data               => s_we_data     ,
1266 
                        we_last               => s_we_last     ,
1267 
                        we_fifo_full          => s_we_fifo_full,
1268 
                        start_write           => s_start_write ,
1269 
                        size_error            => s_size_error,
1270 
                        -- Here the debug vga interface is defined
1271 
                        we_char               => OPEN,
1272 
                        ascii_data            => OPEN );
1273 
   flash : flash_if
1274 
           PORT MAP ( clock                => s_clk_48MHz,
1275 
                      reset                => s_reset_fpga_if,
1276 
                      msec_tick            => s_msec_tick,
1277 
                      -- here the control interface is defined
1278 
                      start_erase          => s_start_erase,
1279 
                      start_read           => s_start_flash_read,
1280 
                      start_write          => s_start_write,
1281 
                      done                 => s_flash_done,
1282 
                      flash_present        => s_flash_present ,
1283 
                      flash_s1_empty       => s_flash_s1_empty,
1284 
                      flash_idle           => s_flash_idle    ,
1285 
                      size_error           => s_size_error    ,
1286 
                      flash_n_busy         => s_flash_n_busy ,
1287 
                      start_config         => s_start_config,
1288 
                      -- here the push fifo interface is defined
1289 
                      push                 => s_flash_push     ,
1290 
                      push_data            => s_flash_push_data,
1291 
                      push_size            => s_flash_push_size,
1292 
                      push_last            => s_flash_push_last,
1293 
                      fifo_full            => s_flash_fifo_full,
1294 
                      -- here the write fifo is defined
1295 
                      bitfile_size         => s_bitfile_size,
1296 
                      we_fifo              => s_we_fifo,
1297 
                      we_data              => s_we_data,
1298 
                      we_last              => s_we_last,
1299 
                      we_fifo_full         => s_we_fifo_full,
1300 
                      -- Here the scpi interface is defined
1301 
                      start_command        => s_start_scpi_command,
1302 
                      command_id           => s_scpi_command_id,
1303 
                      scpi_pop             => s_pud_pop,
1304 
                      scpi_pop_data        => s_fifo_data,
1305 
                      scpi_pop_last        => s_fifo_last,
1306 
                      scpi_empty           => s_fifo_empty,
1307 
                      scpi_push            => s_pud_push,
1308 
                      scpi_push_data       => s_pud_push_data,
1309 
                      scpi_push_size       => s_pud_push_size,
1310 
                      scpi_full            => s_wf_fifo_full,
1311 
                      -- Here the vga interface is defined
1312 
                      we_char              => s_pud_we,
1313 
                      we_ascii             => s_pud_data,
1314 
                      we_addr              => s_pud_addr,
1315 
                      -- define the flash interface
1316 
                      flash_address        => flash_address,
1317 
                      flash_data_in        => flash_data,
1318 
                      flash_data_out       => s_flash_data_out,
1319 
                      flash_data_oe        => s_flash_data_oe,
1320 
                      flash_n_byte         => flash_n_byte,
1321 
                      flash_n_ce           => flash_n_ce,
1322 
                      flash_n_oe           => flash_n_oe,
1323 
                      flash_n_we           => flash_n_we,
1324 
                      flash_ready_n_busy   => flash_ready_n_busy );
1325 
 
1326 
   make_flash_tri : FOR n IN 15 DOWNTO 0 GENERATE
1327 
      flash_data(n) <= s_flash_data_out(n) WHEN s_flash_data_oe(n) = '0'
1328 
                                           ELSE 'Z';
1329 
   END GENERATE make_flash_tri;
1330 
 
1331 
 
1332 
   make_fpga_data_ffs : FOR n IN 7 DOWNTO 0 GENERATE
1333 
      fpga_data(n) <= s_fpga_data_out_reg(n) WHEN s_fpga_n_tri_reg(n) = '0'
1334 
                                             ELSE 'Z';
1335 
      in_ff : FDE
1336 
              PORT MAP ( Q   => s_fpga_data_in(n),
1337 
                         CE  => s_fpga_data_in_ena,
1338 
                         C   => s_clock_96MHz,
1339 
                         D   => fpga_data(n) );
1340 
      tri_ff : FD
1341 
               PORT MAP ( Q  => s_fpga_n_tri_reg(n),
1342 
                          C  => s_clock_96MHz,
1343 
                          D  => s_fpga_n_tri(n) );
1344 
      out_ff : FDE
1345 
               PORT MAP ( Q   => s_fpga_data_out_reg(n),
1346 
                          CE  => s_fpga_data_out_ena,
1347 
                          C   => s_clock_96MHz,
1348 
                          D   => s_fpga_data_out(n) );
1349 
   END GENERATE make_fpga_data_ffs;
1350 
 
1351 
END behave;

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