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[/] [generic_booth_multipler/] [trunk/] [rtl/] [benches/] [TB_BoothDatapath.vhd] - Blame information for rev 3

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1 3 alimpk
 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity TB_BoothDatapath is
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end TB_BoothDatapath;
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architecture Behavioral of TB_BoothDatapath is
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  component BoothDatapath is
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    port(
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      clock :in std_logic;
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      reset :in std_logic;
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      load :in std_logic;
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      shift :in std_logic;
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      X :in std_logic_vector;
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      Y :in std_logic_vector;
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      P :out std_logic_vector);
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  end component;
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  signal clock: std_logic := '0';
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  signal load: std_logic := '0';
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  signal reset: std_logic := '0';
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  signal shift: std_logic := '0';
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  signal X4: std_logic_vector(3 downto 0);
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  signal Y4: std_logic_vector(3 downto 0);
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  signal P8: std_logic_vector(7 downto 0);
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  signal X8: std_logic_vector(7 downto 0);
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  signal Y8: std_logic_vector(7 downto 0);
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  signal P16: std_logic_vector(15 downto 0);
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begin
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  uut4: BoothDatapath
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  port map(
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    clock => clock,
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    reset => reset,
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    load => load,
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    shift => shift,
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    X => X4,
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    Y => Y4,
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    P => P8);
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  uut8: BoothDatapath
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  port map(
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    clock => clock,
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    reset => reset,
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    load => load,
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    shift => shift,
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    X => X8,
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    Y => Y8,
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    P => P16);
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  clock <= not clock after 5 ns;
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  reset<= '1' after 10 ns, '0' after 20 ns;
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  load <= '1' after 30 ns, '0' after 40 ns;
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  shift <= '1' after 40 ns;
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  Y4 <= X"B";
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  X4 <= X"A";
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  Y8 <= X"BA";
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  X8 <= X"A7";
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end Behavioral;

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