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[/] [generic_booth_multipler/] [trunk/] [rtl/] [benches/] [TB_BoothMultiplier.vhd] - Blame information for rev 3

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1 3 alimpk
-- TestBench Template 
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  LIBRARY ieee;
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  USE ieee.std_logic_1164.ALL;
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  USE ieee.numeric_std.ALL;
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  ENTITY TB_BoothMultiplier IS
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  END TB_BoothMultiplier;
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  ARCHITECTURE behavior OF TB_BoothMultiplier IS
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  -- Component Declaration
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  component BoothMultiplier is
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  generic(COUNTER_SIZE : positive := 2);
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  port(
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    clock : in  std_logic;
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    clear : in   std_logic;
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    start : in  std_logic;
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    X_data: in   std_logic_vector(2**COUNTER_SIZE-1 downto 0);
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    Y_data: in   std_logic_vector(2**COUNTER_SIZE-1 downto 0);
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    ready : out std_logic;
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    Result: out std_logic_vector(2*(2**COUNTER_SIZE)-1 downto 0));
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  end component;
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                signal  clock :std_logic := '0';
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                signal  reset :std_logic := '0';
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                signal  start :std_logic := '0';
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                signal  ready4 :std_logic := '0';
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                signal  ready8 :std_logic := '0';
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                signal  X_data4 :std_logic_vector(3 downto 0);
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                signal  Y_data4 :std_logic_vector(3 downto 0);
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                signal  Result8 :std_logic_vector(7 downto 0);
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    signal      X_data8 :std_logic_vector(7 downto 0);
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    signal  Y_data8 :std_logic_vector(7 downto 0);
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    signal  Result16 :std_logic_vector(15 downto 0);
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  begin
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        desing_under_test4bit: BoothMultiplier
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        generic map(
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    COUNTER_SIZE => 2)
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        port map(
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    clock => clock,
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    clear => reset,
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    start => start,
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    X_data => X_data4,
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    Y_data => Y_data4,
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    ready => ready4,
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    Result => Result8);
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        desing_under_test8bit: BoothMultiplier
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    generic map(
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      COUNTER_SIZE => 3)
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    port map(
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      clock => clock,
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      clear => reset,
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      start => start,
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      X_data => X_data8,
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      Y_data => Y_data8,
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      ready => ready8,
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      Result => Result16);
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         clock  <= not clock after 5 ns;
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         start  <= '1' after 10 ns ;
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  reset <=  '1' after 0010 ns ,'0' after 0020 ns;
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--            '1' after 0410 ns, '0' after 0420 ns,      
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--            '1' after 0810 ns, '0' after 0820 ns,      
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--            '1' after 1210 ns, '0' after 1220 ns;
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--               
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  X_data8 <=  X"23" , -- 35
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              X"03" after 0400 ns, -- 3
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              X"FA" after 0800 ns, -- -8
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              X"F5" after 1200 ns; -- -10
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  Y_data8 <=  X"03" , -- 3 
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              X"23" after 0400 ns, -- 35
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              X"F5" after 0800 ns, -- -10
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              X"FA" after 1200 ns;  -- -8
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  X_data4 <=  X"3" , -- 35
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              X"3" after 0400 ns, -- 3
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              X"A" after 0800 ns, -- -8
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              X"5" after 1200 ns; -- -10
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  Y_data4 <=  X"3" , -- 3 
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              X"3" after 0400 ns, -- 35
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              X"5" after 0800 ns, -- -10
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              X"A" after 1200 ns;  -- -8
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end;

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