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[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [00.FullAdder.vhd] - Blame information for rev 2

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1 2 alimpk
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity FullAdder is
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        port(
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                A        :in    std_logic;
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                B        :in    std_logic;
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                Cin :in std_logic;
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                Sum :out std_logic;
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                Cout:out std_logic);
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end FullAdder;
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architecture Behavioral of FullAdder is
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begin
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        Cout    <= (A AND B)OR(B AND Cin)OR(Cin AND A);
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        Sum     <= A XOR B XOR Cin;
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end Behavioral;

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