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[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [02.BoothMultiplier.vhd] - Blame information for rev 2

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1 2 alimpk
 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity BoothMultiplier is
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  generic(COUNTER_SIZE : positive := 2);
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        port(
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                clock : in      std_logic;
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                clear : in      std_logic;
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    start : in  std_logic;
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                X_data: in      std_logic_vector(2**COUNTER_SIZE-1 downto 0);
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                Y_data: in      std_logic_vector(2**COUNTER_SIZE-1 downto 0);
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                ready : out std_logic;
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                Result: out std_logic_vector(2*(2**COUNTER_SIZE)-1 downto 0));
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end BoothMultiplier;
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architecture Behavioral of BoothMultiplier is
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  component counter is
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    port(       clock : in      std_logic;
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          reset : in    std_logic;
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          value : out   std_logic_vector);
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  end component counter;
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  component BoothDatapath is
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        port(
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    clock :in  std_logic;
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    reset :in std_logic;
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    load :in std_logic;
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    shift :in std_logic;
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    X  :in std_logic_vector;
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    Y  :in std_logic_vector;
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    P  :out std_logic_vector);
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    end component BoothDatapath;
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        component BoothController is
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      Port (
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        clock : in  std_logic;
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        reset : in  std_logic;
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        start : in  std_logic;
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        interrupt : in std_logic;
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        load : out std_logic;
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        shift : out std_logic;
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        cnt_clear : out std_logic;
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        reg_clear : out std_logic;
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        ready : out std_logic);
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    end component BoothController;
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    signal load : std_logic;
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    signal counter_value : std_logic_vector(COUNTER_SIZE - 1 downto 0);
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    signal shift : std_logic;
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    signal counter_interrupt : std_logic;
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    signal cnt_clear : std_logic;
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    signal reg_clear : std_logic;
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    CONSTANT ONES : std_logic_vector(COUNTER_SIZE - 1 downto 0) := (others => '1');
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begin
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        datapath:  BoothDatapath
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        port map(
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           clock => clock,
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           reset => reg_clear,
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           load => load,
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           shift => shift,
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           X => X_data,
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           Y => Y_data,
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           P => Result);
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        counter_unit: counter
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    port map(
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       clock => clock,
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       reset => cnt_clear,
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       value => counter_value);
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  counter_interrupt <= '1' when (counter_value = ONES) else '0';
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        controller: BoothController
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       port map(
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          clock => clock,
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          reset => clear,
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          start => start,
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          interrupt => counter_interrupt,
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          load => load,
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          shift => shift,
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          cnt_clear => cnt_clear,
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          reg_clear => reg_clear,
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          ready => ready);
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end Behavioral;
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