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[/] [generic_fifos/] [trunk/] [rtl/] [verilog/] [generic_fifo_lfsr.v] - Blame information for rev 7

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  generic FIFO, uses LFSRs for read/write pointers           ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//
//  CVS Log
//
//  $Id: generic_fifo_lfsr.v,v 1.1 2002-10-29 19:45:07 rherveille Exp $
//
//  $Date: 2002-10-29 19:45:07 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
 
`include "timescale.v"
 
// set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO
//`define FIFO_RW_CHECK
 
// Long Pseudo Random Generators can generate (N^2 -1) combinations. This means
// 1 FIFO entry is unavailable. This might be a problem, especially for small
// FIFOs. Setting FIFO_ALL_ENTRIES creates additional logic that ensures that
// all FIFO entries are used at the expense of some additional logic.
`define FIFO_ALL_ENTRIES
 
module generic_fifo_lfsr (
        clk,
        nReset,
        rst,
        wreq,
        rreq,
        d,
        q,
        empty,
        full,
        aempty,
        afull
        );
 
        //
        // parameters
        //
        parameter aw =  3;                         // no.of entries (in bits; 2^7=128 entries)
        parameter dw =  8;                         // datawidth (in bits)
 
        //
        // inputs & outputs
        //
        input             clk;                     // master clock
        input nReset;                              // asynchronous active low reset
        input rst;                                 // synchronous active high reset
 
        input             wreq;                    // write request
        input             rreq;                    // read request
        input  [dw:1] d;                           // data-input
        output [dw:1] q;                           // data-output
 
        output            empty;                   // fifo empty
        output            full;                    // fifo full
 
        output            aempty;                  // fifo asynchronous/almost empty (1 entry left)
        output            afull;                   // fifo asynchronous/almost full (1 entry left)
 
        reg empty, full;
 
        //
        // Module body
        //
        reg  [aw:1] rp, wp;
        wire [dw:1] ramq;
        wire fwreq, frreq;
 
`ifdef FIFO_ALL_ENTRIES
        function lsb;
           input [aw:1] q;
           case (aw)
               2: lsb = ~q[2];
               3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
               4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
               5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
               6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
               7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
               8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
               9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
              10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
              11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
              12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
              13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
              14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
              15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
              16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
           endcase
        endfunction
`else
        function lsb;
           input [aw:1] q;
           case (aw)
               2: lsb = ~q[2];
               3: lsb = ~(q[3] ^ q[2]);
               4: lsb = ~(q[4] ^ q[3]);
               5: lsb = ~(q[5] ^ q[3]);
               6: lsb = ~(q[6] ^ q[5]);
               7: lsb = ~(q[7] ^ q[6]);
               8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
               9: lsb = ~(q[9] ^ q[5]);
              10: lsb = ~(q[10] ^ q[7]);
              11: lsb = ~(q[11] ^ q[9]);
              12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
              13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
              14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
              15: lsb = ~(q[15] ^ q[14]);
              16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
           endcase
        endfunction
`endif
 
`ifdef RW_CHECK
  assign fwreq = wreq & ~full;
  assign frreq = rreq & ~empty;
`else
  assign fwreq = wreq;
  assign frreq = rreq;
`endif
 
        // hookup read-pointer
        always @(posedge clk or negedge nReset)
          if (~nReset)    rp <= #1 0;
          else if (rst)   rp <= #1 0;
          else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};
 
        // hookup write-pointer
        always @(posedge clk or negedge nReset)
          if (~nReset)    wp <= #1 0;
          else if (rst)   wp <= #1 0;
          else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};
 
        // hookup RAM-block
        generic_dpram #(aw, dw)
        fiforam (
                // write section
                .wclk(clk),
                .wrst(1'b0),
                .wce(1'b1),
                .we(fwreq),
                .waddr(wp),
                .di(d),
 
                // read section
                .rclk(clk),
                .rrst(1'b0),
                .rce(1'b1),
                .oe(1'b1),
                .raddr(rp),
                .do(q)
        );
 
        // generate full/empty signals
        assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
        always @(posedge clk or negedge nReset)
          if (~nReset)
            empty <= #1 1'b1;
          else if (rst)
            empty <= #1 1'b1;
          else
            empty <= #1 aempty | (empty & (~fwreq + frreq));
 
        assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
        always @(posedge clk or negedge nReset)
          if (~nReset)
            full <= #1 1'b0;
          else if (rst)
            full <= #1 1'b0;
          else
            full <= #1 afull | ( full & (~frreq + fwreq) );
 
        //
        // Simulation checks
        //
        // synopsys translate_off
        always @(posedge clk)
          if (full & fwreq)
            $display("Writing while FIFO full\n");
 
        always @(posedge clk)
          if (empty & frreq)
            $display("Reading while FIFO empty\n");
        // synopsys translate_on
endmodule
 

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Subversion Repositories generic_fifos

[/] [generic_fifos/] [trunk/] [rtl/] [verilog/] [generic_fifo_lfsr.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	4	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// generic FIFO, uses LFSRs for read/write pointers ////`
4			`//// ////`
5			`//// Author: Richard Herveille ////`
6			`//// richard@asics.ws ////`
7			`//// www.asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
12			`//// richard@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`//`
36			`// CVS Log`
37			`//`
38			`// $Id: generic_fifo_lfsr.v,v 1.1 2002-10-29 19:45:07 rherveille Exp $`
39			`//`
40			`// $Date: 2002-10-29 19:45:07 $`
41			`// $Revision: 1.1 $`
42			`// $Author: rherveille $`
43			`// $Locker: $`
44			`// $State: Exp $`
45			`//`
46			`// Change History:`
47			`// $Log: not supported by cvs2svn $`
48
49			`include "timescale.v"
50
51			`// set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO`
52			//`define FIFO_RW_CHECK
53
54			`// Long Pseudo Random Generators can generate (N^2 -1) combinations. This means`
55			`// 1 FIFO entry is unavailable. This might be a problem, especially for small`
56			`// FIFOs. Setting FIFO_ALL_ENTRIES creates additional logic that ensures that`
57			`// all FIFO entries are used at the expense of some additional logic.`
58			`define FIFO_ALL_ENTRIES
59
60			`module generic_fifo_lfsr (`
61			`clk,`
62			`nReset,`
63			`rst,`
64			`wreq,`
65			`rreq,`
66			`d,`
67			`q,`
68			`empty,`
69			`full,`
70			`aempty,`
71			`afull`
72			`);`
73
74			`//`
75			`// parameters`
76			`//`
77			`parameter aw = 3; // no.of entries (in bits; 2^7=128 entries)`
78			`parameter dw = 8; // datawidth (in bits)`
79
80			`//`
81			`// inputs & outputs`
82			`//`
83			`input clk; // master clock`
84			`input nReset; // asynchronous active low reset`
85			`input rst; // synchronous active high reset`
86
87			`input wreq; // write request`
88			`input rreq; // read request`
89			`input [dw:1] d; // data-input`
90			`output [dw:1] q; // data-output`
91
92			`output empty; // fifo empty`
93			`output full; // fifo full`
94
95			`output aempty; // fifo asynchronous/almost empty (1 entry left)`
96			`output afull; // fifo asynchronous/almost full (1 entry left)`
97
98			`reg empty, full;`
99
100			`//`
101			`// Module body`
102			`//`
103			`reg [aw:1] rp, wp;`
104			`wire [dw:1] ramq;`
105			`wire fwreq, frreq;`
106
107			`ifdef FIFO_ALL_ENTRIES
108			`function lsb;`
109			`input [aw:1] q;`
110			`case (aw)`
111			`2: lsb = ~q[2];`
112			`3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);`
113			`4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);`
114			`5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);`
115			`6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);`
116			`7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);`
117			`8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);`
118			`9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);`
119			`10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);`
120			`11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);`
121			`12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);`
122			`13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);`
123			`14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);`
124			`15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);`
125			`16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);`
126			`endcase`
127			`endfunction`
128			`else
129			`function lsb;`
130			`input [aw:1] q;`
131			`case (aw)`
132			`2: lsb = ~q[2];`
133			`3: lsb = ~(q[3] ^ q[2]);`
134			`4: lsb = ~(q[4] ^ q[3]);`
135			`5: lsb = ~(q[5] ^ q[3]);`
136			`6: lsb = ~(q[6] ^ q[5]);`
137			`7: lsb = ~(q[7] ^ q[6]);`
138			`8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);`
139			`9: lsb = ~(q[9] ^ q[5]);`
140			`10: lsb = ~(q[10] ^ q[7]);`
141			`11: lsb = ~(q[11] ^ q[9]);`
142			`12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);`
143			`13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);`
144			`14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);`
145			`15: lsb = ~(q[15] ^ q[14]);`
146			`16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);`
147			`endcase`
148			`endfunction`
149			`endif
150
151			`ifdef RW_CHECK
152			`assign fwreq = wreq & ~full;`
153			`assign frreq = rreq & ~empty;`
154			`else
155			`assign fwreq = wreq;`
156			`assign frreq = rreq;`
157			`endif
158
159			`// hookup read-pointer`
160			`always @(posedge clk or negedge nReset)`
161			`if (~nReset) rp <= #1 0;`
162			`else if (rst) rp <= #1 0;`
163			`else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};`
164
165			`// hookup write-pointer`
166			`always @(posedge clk or negedge nReset)`
167			`if (~nReset) wp <= #1 0;`
168			`else if (rst) wp <= #1 0;`
169			`else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};`
170
171			`// hookup RAM-block`
172			`generic_dpram #(aw, dw)`
173			`fiforam (`
174			`// write section`
175			`.wclk(clk),`
176			`.wrst(1'b0),`
177			`.wce(1'b1),`
178			`.we(fwreq),`
179			`.waddr(wp),`
180			`.di(d),`
181
182			`// read section`
183			`.rclk(clk),`
184			`.rrst(1'b0),`
185			`.rce(1'b1),`
186			`.oe(1'b1),`
187			`.raddr(rp),`
188			`.do(q)`
189			`);`
190
191			`// generate full/empty signals`
192			`assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;`
193			`always @(posedge clk or negedge nReset)`
194			`if (~nReset)`
195			`empty <= #1 1'b1;`
196			`else if (rst)`
197			`empty <= #1 1'b1;`
198			`else`
199			`empty <= #1 aempty \| (empty & (~fwreq + frreq));`
200
201			`assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;`
202			`always @(posedge clk or negedge nReset)`
203			`if (~nReset)`
204			`full <= #1 1'b0;`
205			`else if (rst)`
206			`full <= #1 1'b0;`
207			`else`
208			`full <= #1 afull \| ( full & (~frreq + fwreq) );`
209
210			`//`
211			`// Simulation checks`
212			`//`
213			`// synopsys translate_off`
214			`always @(posedge clk)`
215			`if (full & fwreq)`
216			`$display("Writing while FIFO full\n");`
217
218			`always @(posedge clk)`
219			`if (empty & frreq)`
220			`$display("Reading while FIFO empty\n");`
221			`// synopsys translate_on`
222			`endmodule`
223