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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Linear Feedback Shift Register ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//
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// CVS Log
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//
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// $Id: lfsr.v,v 1.1 2002-10-29 19:45:07 rherveille Exp $
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//
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// $Date: 2002-10-29 19:45:07 $
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// $Revision: 1.1 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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`include "timescale.v"
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module lfsr (clk, ena, nReset, rst, q);
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//
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// parameters
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//
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parameter [3:0] TAPS = 8; // number of flip-flops in LFSR
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//
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// inputs & outputs
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//
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input clk; // master clock
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input ena; // clock enable
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input nReset; // asynchronous active low reset
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input rst; // synchronous active high reset
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output [TAPS:1] q; // LFSR output
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reg [TAPS:1] q;
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//
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// Module body
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//
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function lsb;
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input [TAPS-1:0] q;
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case (TAPS)
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2: lsb = ~q[0];
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3: lsb = q[3] ^ q[2];
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4: lsb = q[4] ^ q[3];
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5: lsb = q[5] ^ q[3];
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6: lsb = q[6] ^ q[5];
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7: lsb = q[7] ^ q[6];
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8: lsb = q[8] ^ q[6] ^ q[5] ^ q[4];
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9: lsb = q[9] ^ q[5];
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10: lsb = q[10] ^ q[7];
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11: lsb = q[11] ^ q[9];
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12: lsb = q[12] ^ q[6] ^ q[4] ^ q[1];
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13: lsb = q[13] ^ q[4] ^ q[3] ^ q[1];
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14: lsb = q[14] ^ q[5] ^ q[3] ^ q[1];
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15: lsb = q[15] ^ q[14];
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16: lsb = q[16] ^ q[15] ^ q[13] ^ q[4];
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endcase
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endfunction
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always @(posedge clk or negedge nReset)
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if (~nReset) q <= #1 0;
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else if (rst) q <= #1 0;
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else if (ena) q <= #1 {q[TAPS-1:1], lsb(q)};
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endmodule
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