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[/] [genesys_ddr2/] [trunk/] [bench/] [test_DDR2_wb.v] - Blame information for rev 2

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: UPT
// Engineer: Oana Boncalo & Alexandru Amaricai
// 
// Create Date:    19:05:16 03/22/2013 
// Design Name: 
// Module Name:    test_DDR2_wb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test_DDR2_wb#
  (
   parameter BANK_WIDTH              = 2,
                                       // # of memory bank addr bits.
   parameter CKE_WIDTH               = 1,
                                       // # of memory clock enable outputs.
   parameter CLK_WIDTH               = 2,
                                       // # of clock outputs.
   parameter COL_WIDTH               = 10,
                                       // # of memory column bits.
   parameter CS_NUM                  = 1,
                                       // # of separate memory chip selects.
   parameter CS_WIDTH                = 1,
                                       // # of total memory chip selects.
   parameter CS_BITS                 = 0,
                                       // set to log2(CS_NUM) (rounded up).
   parameter DM_WIDTH                = 8,
                                       // # of data mask bits.
   parameter DQ_WIDTH                = 64,
                                       // # of data width.
   parameter DQ_PER_DQS              = 8,
                                       // # of DQ data bits per strobe.
   parameter DQS_WIDTH               = 8,
                                       // # of DQS strobes.
   parameter DQ_BITS                 = 6,
                                       // set to log2(DQS_WIDTH*DQ_PER_DQS).
   parameter DQS_BITS                = 3,
                                       // set to log2(DQS_WIDTH).
   parameter ODT_WIDTH               = 1,
                                       // # of memory on-die term enables.
   parameter ROW_WIDTH               = 13,
                                       // # of memory row and # of addr bits.
   parameter ADDITIVE_LAT            = 0,
                                       // additive write latency.
   parameter BURST_LEN               = 4,
                                       // burst length (in double words).
   parameter BURST_TYPE              = 0,
                                       // burst type (=0 seq; =1 interleaved).
   parameter CAS_LAT                 = 3,
                                       // CAS latency.
   parameter ECC_ENABLE              = 0,
                                       // enable ECC (=1 enable).
   parameter APPDATA_WIDTH           = 128,
                                       // # of usr read/write data bus bits.
   parameter MULTI_BANK_EN           = 1,
                                       // Keeps multiple banks open. (= 1 enable).
   parameter TWO_T_TIME_EN           = 1,
                                       // 2t timing for unbuffered dimms.
   parameter ODT_TYPE                = 1,
                                       // ODT (=0(none),=1(75),=2(150),=3(50)).
   parameter REDUCE_DRV              = 0,
                                       // reduced strength mem I/O (=1 yes).
   parameter REG_ENABLE              = 0,
                                       // registered addr/ctrl (=1 yes).
   parameter TREFI_NS                = 7800,
                                       // auto refresh interval (ns).
   parameter TRAS                    = 40000,
                                       // active->precharge delay.
   parameter TRCD                    = 15000,
                                       // active->read/write delay.
   parameter TRFC                    = 105000,
                                       // refresh->refresh, refresh->active delay.
   parameter TRP                     = 15000,
                                       // precharge->command delay.
   parameter TRTP                    = 7500,
                                       // read->precharge delay.
   parameter TWR                     = 15000,
                                       // used to determine write->precharge.
   parameter TWTR                    = 7500,
                                       // write->read delay.
   parameter HIGH_PERFORMANCE_MODE   = "TRUE",
                              // # = TRUE, the IODELAY performance mode is set
                              // to high.
                              // # = FALSE, the IODELAY performance mode is set
                              // to low.
   parameter SIM_ONLY                = 0,
                                       // = 1 to skip SDRAM power up delay.
   parameter DEBUG_EN                = 0,
                                       // Enable debug signals/controls.
                                       // When this parameter is changed from 0 to 1,
                                       // make sure to uncomment the coregen commands
                                       // in ise_flow.bat or create_ise.bat files in
                                       // par folder.
   parameter CLK_PERIOD              = 8000,
                                       // Core/Memory clock period (in ps).
   parameter RST_ACT_LOW             = 0
                                       // =1 for active low reset, =0 for active high.
   )
        (
        input sysClk,
        input sysRst,  //Asynchronous PLL reset
        //output outSysClk,
 
        input [7:0] sw,
        output [7:0] leds,
 
        inout  [DQ_WIDTH-1:0]              ddr2_dq,
   output [ROW_WIDTH-1:0]             ddr2_a,
   output [BANK_WIDTH-1:0]            ddr2_ba,
   output                             ddr2_ras_n,
   output                             ddr2_cas_n,
   output                             ddr2_we_n,
   output [CS_WIDTH-1:0]              ddr2_cs_n,
   output [ODT_WIDTH-1:0]             ddr2_odt,
   output [CKE_WIDTH-1:0]             ddr2_cke,
   output [DM_WIDTH-1:0]              ddr2_dm,
        inout  [DQS_WIDTH-1:0]             ddr2_dqs,
   inout  [DQS_WIDTH-1:0]             ddr2_dqs_n,
   output [CLK_WIDTH-1:0]             ddr2_ck,
   output [CLK_WIDTH-1:0]             ddr2_ck_n
    );
        //chipscope ila and icon connecting signals
        wire [35:0] control;
        wire [327:0] data;
        wire [7:0] trig0;
 
        //wishbone signals
         wire                                                           cyc_wb;
         wire                                                                   stb_wb;
         wire   [30:0]                                           address_wb;
         wire   [(APPDATA_WIDTH/8)-1:0]  sel_wb; //write mask     
         wire   [APPDATA_WIDTH-1:0]              wr_data_wb; // write data
         wire                                                                   we_wb;
         wire   [2:0]                                            cti_wb;
         wire   [1:0]                                            bte_wb;
         //to wishbone from memory interface
         wire                                                                   ack_mem, err_mem, rty_mem;
         wire [APPDATA_WIDTH-1:0]                rd_data_wb; // rd data
         wire [3:0]                                                      wb_state;
         wire   [2:0]                                                    state;
         wire [3:0]                                                      state_master;
         wire                                                                   phy_init_done;
         wire                                                           clk0_tb, rst0_tb;
         wire                                                                   sysClk_bufg;
 
 
   DDR2_Mem #
  (
   .BANK_WIDTH (BANK_WIDTH),
                                       // # of memory bank addr bits.
   .CKE_WIDTH  (CKE_WIDTH),
                                       // # of memory clock enable outputs.
   .CLK_WIDTH (CLK_WIDTH),
                                       // # of clock outputs.
   .COL_WIDTH (COL_WIDTH),
                                       // # of memory column bits.
   .CS_NUM (CS_NUM),
                                       // # of separate memory chip selects.
   .CS_WIDTH (CS_WIDTH),
                                       // # of total memory chip selects.
   .CS_BITS (CS_BITS),
                                       // set to log2(CS_NUM) (rounded up).
   .DM_WIDTH (DM_WIDTH),
                                       // # of data mask bits.
   .DQ_WIDTH (DQ_WIDTH),
                                       // # of data width.
   .DQ_PER_DQS (DQ_PER_DQS),
                                       // # of DQ data bits per strobe.
   .DQS_WIDTH (DQS_WIDTH),
                                       // # of DQS strobes.
   .DQ_BITS (DQ_BITS),
                                       // set to log2(DQS_WIDTH*DQ_PER_DQS).
   .DQS_BITS (DQS_BITS),
                                       // set to log2(DQS_WIDTH).
   .ODT_WIDTH (ODT_WIDTH),
                                       // # of memory on-die term enables.
   .ROW_WIDTH (ROW_WIDTH),
                                       // # of memory row and # of addr bits.
   .ADDITIVE_LAT (ADDITIVE_LAT),
                                       // additive write latency.
   .BURST_LEN (BURST_LEN),
                                       // burst length (in double words).
   .BURST_TYPE (BURST_TYPE),
                                       // burst type (=0 seq; =1 interleaved).
   .CAS_LAT (CAS_LAT),
                                       // CAS latency.
   .ECC_ENABLE (ECC_ENABLE),
                                       // enable ECC (=1 enable).
   .APPDATA_WIDTH (APPDATA_WIDTH),
                                       // # of usr read/write data bus bits.
   .MULTI_BANK_EN (MULTI_BANK_EN),
                                       // Keeps multiple banks open. (= 1 enable).
   .TWO_T_TIME_EN  (TWO_T_TIME_EN),
                                       // 2t timing for unbuffered dimms.
   .ODT_TYPE  (ODT_TYPE),
                                       // ODT (=0(none),=1(75),=2(150),=3(50)).
   .REDUCE_DRV (REDUCE_DRV),
                                       // reduced strength mem I/O (=1 yes).
   .REG_ENABLE (REG_ENABLE),
                                       // registered addr/ctrl (=1 yes).
   .TREFI_NS (TREFI_NS),
                                                                                                        // auto refresh interval (ns).
   .TRAS (TRAS),
                                       // active->precharge delay.
   .TRCD (TRCD),
                                       // active->read/write delay.
   .TRFC  (TRFC),
                                       // refresh->refresh, refresh->active delay.
   .TRP (TRP),
                                       // precharge->command delay.
   .TRTP (TRTP),
                                       // read->precharge delay.
   .TWR (TWR),
                                       // used to determine write->precharge.
   .TWTR (TWTR),
                                       // write->read delay.
   .HIGH_PERFORMANCE_MODE  (HIGH_PERFORMANCE_MODE),
                              // # = TRUE, the IODELAY performance mode is set
                              // to high.
                              // # = FALSE, the IODELAY performance mode is set
                              // to low.
   .SIM_ONLY (SIM_ONLY),
                                       // = 1 to skip SDRAM power up delay.
   .DEBUG_EN (DEBUG_EN),
                                       // Enable debug signals/controls.
                                       // When this parameter is changed from 0 to 1,
                                       // make sure to uncomment the coregen commands
                                       // in ise_flow.bat or create_ise.bat files in
                                       // par folder.
   .CLK_PERIOD (CLK_PERIOD),
                                       // Core/Memory clock period (in ps).
   .RST_ACT_LOW (RST_ACT_LOW)
                                       // =1 for active low reset, =0 for active high.
   )
        test_ddr2_mem_wb
        (
        .sysClk (sysClk),
        .sysRst (sysRst),  //Asynchronous PLL reset
        .clk0 (clk0_tb),
        .rst0 (rst0_tb),
 
        .ddr2_dq (ddr2_dq),
   .ddr2_a (ddr2_a),
   .ddr2_ba (ddr2_ba),
   .ddr2_ras_n (ddr2_ras_n),
   .ddr2_cas_n (ddr2_cas_n),
   .ddr2_we_n (ddr2_we_n),
   .ddr2_cs_n (ddr2_cs_n),
   .ddr2_odt (ddr2_odt),
   .ddr2_cke (ddr2_cke),
   .ddr2_dm (ddr2_dm),
        .ddr2_dqs (ddr2_dqs),
   .ddr2_dqs_n (ddr2_dqs_n),
   .ddr2_ck (ddr2_ck),
   .ddr2_ck_n (ddr2_ck_n),
        //wishbone if signals
         .cyc_wb (cyc_wb),
         .stb_wb (stb_wb),
         .address_wb (address_wb),
         .sel_wb (sel_wb), //write mask  
         .wr_data_wb (wr_data_wb), // write data
         .we_wb (we_wb),
         .cti_wb (cti_wb),
         .bte_wb (bte_wb),
         //to wishbone from memory interface
         .ack_mem (ack_mem),
         .err_mem (err_mem),
         .rty_mem (rty_mem),
         .rd_data_wb (rd_data_wb), // rd data
         .wb_state (wb_state),
         .state (state),
         .phy_init_done_o (phy_init_done)
    );
 
        //only for test purposes
        wishbone_master_mock #(
    .APPDATA_WIDTH (APPDATA_WIDTH)  )
         master_test_wb
        (
    .clk (clk0_tb),
         .rst (rst0_tb),
 
         .cyc_wb (cyc_wb),
         .stb_wb (stb_wb),
         .address_wb (address_wb),
         .sel_wb (sel_wb), //write mask  
         .wr_data_wb (wr_data_wb), // write data
         .we_wb (we_wb),
         .cti_wb (cti_wb),
         .bte_wb (bte_wb),
         //to wishbone from memory interface
         .ack_mem (ack_mem),
         .err_mem (err_mem),
         .rty_mem (rty_mem),
         .rd_data_mem (rd_data_wb),
         .state (state_master)
         );
 
 
endmodule

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Subversion Repositories genesys_ddr2

[/] [genesys_ddr2/] [trunk/] [bench/] [test_DDR2_wb.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	oana.bonca	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company: UPT`
4			`// Engineer: Oana Boncalo & Alexandru Amaricai`
5			`//`
6			`// Create Date: 19:05:16 03/22/2013`
7			`// Design Name:`
8			`// Module Name: test_DDR2_wb`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module test_DDR2_wb#`
22			`(`
23			`parameter BANK_WIDTH = 2,`
24			`// # of memory bank addr bits.`
25			`parameter CKE_WIDTH = 1,`
26			`// # of memory clock enable outputs.`
27			`parameter CLK_WIDTH = 2,`
28			`// # of clock outputs.`
29			`parameter COL_WIDTH = 10,`
30			`// # of memory column bits.`
31			`parameter CS_NUM = 1,`
32			`// # of separate memory chip selects.`
33			`parameter CS_WIDTH = 1,`
34			`// # of total memory chip selects.`
35			`parameter CS_BITS = 0,`
36			`// set to log2(CS_NUM) (rounded up).`
37			`parameter DM_WIDTH = 8,`
38			`// # of data mask bits.`
39			`parameter DQ_WIDTH = 64,`
40			`// # of data width.`
41			`parameter DQ_PER_DQS = 8,`
42			`// # of DQ data bits per strobe.`
43			`parameter DQS_WIDTH = 8,`
44			`// # of DQS strobes.`
45			`parameter DQ_BITS = 6,`
46			`// set to log2(DQS_WIDTH*DQ_PER_DQS).`
47			`parameter DQS_BITS = 3,`
48			`// set to log2(DQS_WIDTH).`
49			`parameter ODT_WIDTH = 1,`
50			`// # of memory on-die term enables.`
51			`parameter ROW_WIDTH = 13,`
52			`// # of memory row and # of addr bits.`
53			`parameter ADDITIVE_LAT = 0,`
54			`// additive write latency.`
55			`parameter BURST_LEN = 4,`
56			`// burst length (in double words).`
57			`parameter BURST_TYPE = 0,`
58			`// burst type (=0 seq; =1 interleaved).`
59			`parameter CAS_LAT = 3,`
60			`// CAS latency.`
61			`parameter ECC_ENABLE = 0,`
62			`// enable ECC (=1 enable).`
63			`parameter APPDATA_WIDTH = 128,`
64			`// # of usr read/write data bus bits.`
65			`parameter MULTI_BANK_EN = 1,`
66			`// Keeps multiple banks open. (= 1 enable).`
67			`parameter TWO_T_TIME_EN = 1,`
68			`// 2t timing for unbuffered dimms.`
69			`parameter ODT_TYPE = 1,`
70			`// ODT (=0(none),=1(75),=2(150),=3(50)).`
71			`parameter REDUCE_DRV = 0,`
72			`// reduced strength mem I/O (=1 yes).`
73			`parameter REG_ENABLE = 0,`
74			`// registered addr/ctrl (=1 yes).`
75			`parameter TREFI_NS = 7800,`
76			`// auto refresh interval (ns).`
77			`parameter TRAS = 40000,`
78			`// active->precharge delay.`
79			`parameter TRCD = 15000,`
80			`// active->read/write delay.`
81			`parameter TRFC = 105000,`
82			`// refresh->refresh, refresh->active delay.`
83			`parameter TRP = 15000,`
84			`// precharge->command delay.`
85			`parameter TRTP = 7500,`
86			`// read->precharge delay.`
87			`parameter TWR = 15000,`
88			`// used to determine write->precharge.`
89			`parameter TWTR = 7500,`
90			`// write->read delay.`
91			`parameter HIGH_PERFORMANCE_MODE = "TRUE",`
92			`// # = TRUE, the IODELAY performance mode is set`
93			`// to high.`
94			`// # = FALSE, the IODELAY performance mode is set`
95			`// to low.`
96			`parameter SIM_ONLY = 0,`
97			`// = 1 to skip SDRAM power up delay.`
98			`parameter DEBUG_EN = 0,`
99			`// Enable debug signals/controls.`
100			`// When this parameter is changed from 0 to 1,`
101			`// make sure to uncomment the coregen commands`
102			`// in ise_flow.bat or create_ise.bat files in`
103			`// par folder.`
104			`parameter CLK_PERIOD = 8000,`
105			`// Core/Memory clock period (in ps).`
106			`parameter RST_ACT_LOW = 0`
107			`// =1 for active low reset, =0 for active high.`
108			`)`
109			`(`
110			`input sysClk,`
111			`input sysRst, //Asynchronous PLL reset`
112			`//output outSysClk,`
113
114			`input [7:0] sw,`
115			`output [7:0] leds,`
116
117			`inout [DQ_WIDTH-1:0] ddr2_dq,`
118			`output [ROW_WIDTH-1:0] ddr2_a,`
119			`output [BANK_WIDTH-1:0] ddr2_ba,`
120			`output ddr2_ras_n,`
121			`output ddr2_cas_n,`
122			`output ddr2_we_n,`
123			`output [CS_WIDTH-1:0] ddr2_cs_n,`
124			`output [ODT_WIDTH-1:0] ddr2_odt,`
125			`output [CKE_WIDTH-1:0] ddr2_cke,`
126			`output [DM_WIDTH-1:0] ddr2_dm,`
127			`inout [DQS_WIDTH-1:0] ddr2_dqs,`
128			`inout [DQS_WIDTH-1:0] ddr2_dqs_n,`
129			`output [CLK_WIDTH-1:0] ddr2_ck,`
130			`output [CLK_WIDTH-1:0] ddr2_ck_n`
131			`);`
132			`//chipscope ila and icon connecting signals`
133			`wire [35:0] control;`
134			`wire [327:0] data;`
135			`wire [7:0] trig0;`
136
137			`//wishbone signals`
138			`wire cyc_wb;`
139			`wire stb_wb;`
140			`wire [30:0] address_wb;`
141			`wire [(APPDATA_WIDTH/8)-1:0] sel_wb; //write mask`
142			`wire [APPDATA_WIDTH-1:0] wr_data_wb; // write data`
143			`wire we_wb;`
144			`wire [2:0] cti_wb;`
145			`wire [1:0] bte_wb;`
146			`//to wishbone from memory interface`
147			`wire ack_mem, err_mem, rty_mem;`
148			`wire [APPDATA_WIDTH-1:0] rd_data_wb; // rd data`
149			`wire [3:0] wb_state;`
150			`wire [2:0] state;`
151			`wire [3:0] state_master;`
152			`wire phy_init_done;`
153			`wire clk0_tb, rst0_tb;`
154			`wire sysClk_bufg;`
155
156
157			`DDR2_Mem #`
158			`(`
159			`.BANK_WIDTH (BANK_WIDTH),`
160			`// # of memory bank addr bits.`
161			`.CKE_WIDTH (CKE_WIDTH),`
162			`// # of memory clock enable outputs.`
163			`.CLK_WIDTH (CLK_WIDTH),`
164			`// # of clock outputs.`
165			`.COL_WIDTH (COL_WIDTH),`
166			`// # of memory column bits.`
167			`.CS_NUM (CS_NUM),`
168			`// # of separate memory chip selects.`
169			`.CS_WIDTH (CS_WIDTH),`
170			`// # of total memory chip selects.`
171			`.CS_BITS (CS_BITS),`
172			`// set to log2(CS_NUM) (rounded up).`
173			`.DM_WIDTH (DM_WIDTH),`
174			`// # of data mask bits.`
175			`.DQ_WIDTH (DQ_WIDTH),`
176			`// # of data width.`
177			`.DQ_PER_DQS (DQ_PER_DQS),`
178			`// # of DQ data bits per strobe.`
179			`.DQS_WIDTH (DQS_WIDTH),`
180			`// # of DQS strobes.`
181			`.DQ_BITS (DQ_BITS),`
182			`// set to log2(DQS_WIDTH*DQ_PER_DQS).`
183			`.DQS_BITS (DQS_BITS),`
184			`// set to log2(DQS_WIDTH).`
185			`.ODT_WIDTH (ODT_WIDTH),`
186			`// # of memory on-die term enables.`
187			`.ROW_WIDTH (ROW_WIDTH),`
188			`// # of memory row and # of addr bits.`
189			`.ADDITIVE_LAT (ADDITIVE_LAT),`
190			`// additive write latency.`
191			`.BURST_LEN (BURST_LEN),`
192			`// burst length (in double words).`
193			`.BURST_TYPE (BURST_TYPE),`
194			`// burst type (=0 seq; =1 interleaved).`
195			`.CAS_LAT (CAS_LAT),`
196			`// CAS latency.`
197			`.ECC_ENABLE (ECC_ENABLE),`
198			`// enable ECC (=1 enable).`
199			`.APPDATA_WIDTH (APPDATA_WIDTH),`
200			`// # of usr read/write data bus bits.`
201			`.MULTI_BANK_EN (MULTI_BANK_EN),`
202			`// Keeps multiple banks open. (= 1 enable).`
203			`.TWO_T_TIME_EN (TWO_T_TIME_EN),`
204			`// 2t timing for unbuffered dimms.`
205			`.ODT_TYPE (ODT_TYPE),`
206			`// ODT (=0(none),=1(75),=2(150),=3(50)).`
207			`.REDUCE_DRV (REDUCE_DRV),`
208			`// reduced strength mem I/O (=1 yes).`
209			`.REG_ENABLE (REG_ENABLE),`
210			`// registered addr/ctrl (=1 yes).`
211			`.TREFI_NS (TREFI_NS),`
212			`// auto refresh interval (ns).`
213			`.TRAS (TRAS),`
214			`// active->precharge delay.`
215			`.TRCD (TRCD),`
216			`// active->read/write delay.`
217			`.TRFC (TRFC),`
218			`// refresh->refresh, refresh->active delay.`
219			`.TRP (TRP),`
220			`// precharge->command delay.`
221			`.TRTP (TRTP),`
222			`// read->precharge delay.`
223			`.TWR (TWR),`
224			`// used to determine write->precharge.`
225			`.TWTR (TWTR),`
226			`// write->read delay.`
227			`.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),`
228			`// # = TRUE, the IODELAY performance mode is set`
229			`// to high.`
230			`// # = FALSE, the IODELAY performance mode is set`
231			`// to low.`
232			`.SIM_ONLY (SIM_ONLY),`
233			`// = 1 to skip SDRAM power up delay.`
234			`.DEBUG_EN (DEBUG_EN),`
235			`// Enable debug signals/controls.`
236			`// When this parameter is changed from 0 to 1,`
237			`// make sure to uncomment the coregen commands`
238			`// in ise_flow.bat or create_ise.bat files in`
239			`// par folder.`
240			`.CLK_PERIOD (CLK_PERIOD),`
241			`// Core/Memory clock period (in ps).`
242			`.RST_ACT_LOW (RST_ACT_LOW)`
243			`// =1 for active low reset, =0 for active high.`
244			`)`
245			`test_ddr2_mem_wb`
246			`(`
247			`.sysClk (sysClk),`
248			`.sysRst (sysRst), //Asynchronous PLL reset`
249			`.clk0 (clk0_tb),`
250			`.rst0 (rst0_tb),`
251
252			`.ddr2_dq (ddr2_dq),`
253			`.ddr2_a (ddr2_a),`
254			`.ddr2_ba (ddr2_ba),`
255			`.ddr2_ras_n (ddr2_ras_n),`
256			`.ddr2_cas_n (ddr2_cas_n),`
257			`.ddr2_we_n (ddr2_we_n),`
258			`.ddr2_cs_n (ddr2_cs_n),`
259			`.ddr2_odt (ddr2_odt),`
260			`.ddr2_cke (ddr2_cke),`
261			`.ddr2_dm (ddr2_dm),`
262			`.ddr2_dqs (ddr2_dqs),`
263			`.ddr2_dqs_n (ddr2_dqs_n),`
264			`.ddr2_ck (ddr2_ck),`
265			`.ddr2_ck_n (ddr2_ck_n),`
266			`//wishbone if signals`
267			`.cyc_wb (cyc_wb),`
268			`.stb_wb (stb_wb),`
269			`.address_wb (address_wb),`
270			`.sel_wb (sel_wb), //write mask`
271			`.wr_data_wb (wr_data_wb), // write data`
272			`.we_wb (we_wb),`
273			`.cti_wb (cti_wb),`
274			`.bte_wb (bte_wb),`
275			`//to wishbone from memory interface`
276			`.ack_mem (ack_mem),`
277			`.err_mem (err_mem),`
278			`.rty_mem (rty_mem),`
279			`.rd_data_wb (rd_data_wb), // rd data`
280			`.wb_state (wb_state),`
281			`.state (state),`
282			`.phy_init_done_o (phy_init_done)`
283			`);`
284
285			`//only for test purposes`
286			`wishbone_master_mock #(`
287			`.APPDATA_WIDTH (APPDATA_WIDTH) )`
288			`master_test_wb`
289			`(`
290			`.clk (clk0_tb),`
291			`.rst (rst0_tb),`
292
293			`.cyc_wb (cyc_wb),`
294			`.stb_wb (stb_wb),`
295			`.address_wb (address_wb),`
296			`.sel_wb (sel_wb), //write mask`
297			`.wr_data_wb (wr_data_wb), // write data`
298			`.we_wb (we_wb),`
299			`.cti_wb (cti_wb),`
300			`.bte_wb (bte_wb),`
301			`//to wishbone from memory interface`
302			`.ack_mem (ack_mem),`
303			`.err_mem (err_mem),`
304			`.rty_mem (rty_mem),`
305			`.rd_data_mem (rd_data_wb),`
306			`.state (state_master)`
307			`);`
308
309
310			`endmodule`