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[/] [genesys_ddr2/] [trunk/] [bench/] [wishbone_mock.v] - Blame information for rev 2

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1 2 oana.bonca 
`timescale 1ns / 1ps
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module wishbone_master_mock #(
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    parameter APPDATA_WIDTH           = 128  )
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        (
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    input clk, rst,
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         output         reg                                                                     cyc_wb,
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         output reg                                                             stb_wb,
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         output reg [30:0]                                                       address_wb,
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         output reg [(APPDATA_WIDTH/8)-1:0]      sel_wb, //write mask
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         output reg [APPDATA_WIDTH-1:0]             wr_data_wb, // write data
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         output reg                                                             we_wb,
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         output         reg [2:0]                                                        cti_wb,
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         output  reg [1:0]                                                       bte_wb,
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         //to wishbone from memory interface
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         input                                                                          ack_mem, err_mem, rty_mem,
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         input  [APPDATA_WIDTH-1:0]                      rd_data_mem,
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         output [3:0]                                                            state
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         );
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    localparam WB_IDLE  = 4'b0000;
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    localparam WR_CYC0  = 4'b0001;
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    localparam WR_CYCI  = 4'b0010;
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    localparam RD_REQ           = 4'b0011;
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    localparam RD_WAIT_RSP= 4'b0100;
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    localparam RD_RSP0          = 4'b0101;
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    localparam RD_RSP1          = 4'b0110;
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    localparam WR_CYCI_1                = 4'b0111;
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    localparam STALL1           = 4'b1000;
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         localparam STALL2              = 4'b1001;
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    reg [3:0] st_reg, st_nxt;
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         reg [1:0] cnt_reg, cnt_nxt;
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         reg [7:0] adr_cnt_reg, adr_cnt_nxt;
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         reg [4:0] op_cnt_reg, op_cnt_nxt;
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    //reg [1:0] cnt_reg, cnt_nxt;
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    //reg [APPDATA_WIDTH-1:0]           wr_data_reg, wr_data_nxt;
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    //reg [(APPDATA_WIDTH/8)-1:0]        wr_mask_reg, wr_mask_nxt;
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  assign state = st_reg;
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  always
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                @(posedge clk, posedge rst)
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         begin
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                if(rst)
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                        begin
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                                //wr_data_reg <= 0;
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              st_reg <= 0; //st_reg;
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                        cnt_reg <= 0;
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                        adr_cnt_reg <= 0;
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                        op_cnt_reg <= 0;
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                        end
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                else
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                        begin
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                                //wr_data_reg <= wr_data_nxt;
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              st_reg <= st_nxt;
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                        cnt_reg <= cnt_nxt;
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                        adr_cnt_reg <= adr_cnt_nxt;
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                        op_cnt_reg <= op_cnt_nxt;
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                        end
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         end
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  //***************************************************************************
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  // State Machine for mimicking responses from memory to mem_wb_if for wb bus
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  //***************************************************************************
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  always @*
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  begin
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        //for memory WR operations
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        //wr_data_nxt = wr_data_reg;
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        st_nxt = st_reg;
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        sel_wb = 0;
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        cyc_wb = 1'b0;
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        stb_wb = 1'b0;
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        we_wb = 1'bx;
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        wr_data_wb = 0;
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        cnt_nxt = cnt_reg;
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        cti_wb = 3'b010;
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        bte_wb = 2'b00;
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        adr_cnt_nxt = adr_cnt_reg;
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        op_cnt_nxt = op_cnt_reg;
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        address_wb [30] = 1;
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        case (st_reg)
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                WB_IDLE:
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                        begin
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                                  //start with WR command
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                                        st_nxt = WR_CYC0;
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                                        cyc_wb = 1'b0;
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                                        stb_wb = 1'b0;
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                                        we_wb = 1'b0;
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                                        address_wb = 8'h00;
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                                        cti_wb = 3'b111;
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                                        adr_cnt_nxt = 0;
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                                        //adr_cnt_nxt = adr_cnt_reg + 32;
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                                        wr_data_wb = 128'hBABEBABEBABEBABEBABEBABEBABEBABE;
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                                        sel_wb = 16'hFFFFFFFF;
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                        end
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                WR_CYC0:
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                                begin
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                                  cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        we_wb = 1'b1;
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                                        sel_wb = 16'hFFFFFFFF;
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                                   wr_data_wb = 128'hBABEBABEBABEBABEBABEBABEBABEBABE;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        st_nxt = WR_CYCI;
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                                end
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                WR_CYCI:
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                                begin
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                                  cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        we_wb = 1'b1;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        sel_wb = 16'hFFFFFFFF;
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                                        //wait for ack
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                                        if (ack_mem)
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                                        begin
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                                           st_nxt = WR_CYCI_1;
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                                                //wr_data_wb = 128'hADADADADADADADADADADADADADADADAD;
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                                                wr_data_wb = 128'hBABEBABEBABEBABEBABEBABEBABEBABE;
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                                        end
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                                        else
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                                        begin
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                                          st_nxt = WR_CYCI;
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                                          wr_data_wb = 128'hBABEBABEBABEBABEBABEBABEBABEBABE;
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                                        end
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                                end
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                WR_CYCI_1:
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                     begin
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                                        cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        we_wb  = 1'b1;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        we_wb = 1'b1;
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                                        wr_data_wb = 128'hADADADADADADADADADADADADADADADAD;
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                                        sel_wb = 16'hFFFFFFFF;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        //wait for ack
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                                        if (!ack_mem)
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                                        begin
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                                           st_nxt = WR_CYCI_1;
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                                        end
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                                        else
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                                        begin
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                                          st_nxt = 8;
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                                          cyc_wb = 1'b1;
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                                          stb_wb = 1'b1;
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                                          we_wb  = 1'b1;
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                                          cti_wb = 3'b010;
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                                          op_cnt_nxt = 0;
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                                        end
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                                end
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                8:
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                    begin
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                      if (op_cnt_reg == 0)
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                                begin
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                                        st_nxt = RD_REQ;
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                                        op_cnt_nxt = 0;
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                                        adr_cnt_nxt = 0;
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                                        //adr_cnt_nxt[30] = 1;
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                                end
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                                else
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                                begin
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                                        st_nxt = 8;
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                                        op_cnt_nxt = op_cnt_reg + 1;
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                                        //adr_cnt_nxt = adr_cnt_reg + 32;
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                                end
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                      cyc_wb = 1'b0;
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                                stb_wb = 1'b0;
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                                we_wb  = 1'b0;
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                                cti_wb = 3'b111;
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                    end
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                RD_REQ:
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                                begin
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                                        cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        we_wb  = 1'b0;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        st_nxt = RD_WAIT_RSP;
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                                end
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                RD_WAIT_RSP:
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                                begin
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                                  cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        we_wb  = 1'b0;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        cnt_nxt = 2;
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                                        if (err_mem)
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                                                st_nxt = WB_IDLE;
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                                        else
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                                        begin
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                                                if (ack_mem)
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                                                        st_nxt = RD_RSP0;
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                                                else
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                                                  st_nxt = RD_WAIT_RSP;
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                                        end
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                                end
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                RD_RSP0:
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                                begin
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                                  cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        we_wb  = 1'b0;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        cnt_nxt = cnt_reg -1;
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                                        if (ack_mem && (cnt_reg != 0))
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                                         begin
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                                           st_nxt = RD_RSP1;
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                                           //$display ("RD response available from mem ... \n");
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                                         end
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                                        else
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                                          st_nxt = RD_RSP0;
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                                end
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                 RD_RSP1:
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                                begin
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                                        cyc_wb = 1'b1;
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                                        stb_wb = 1'b1;
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                                        we_wb  = 1'b0;
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                                        address_wb = adr_cnt_reg;
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                                        address_wb [30] = 1;
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                                        cti_wb = 3'b010;
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                                        bte_wb = 2'b00;
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                                        //$display ("Data bus word: %h \n", rd_data_mem);
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                                        cnt_nxt = cnt_reg - 1;
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                                        if (ack_mem && (cnt_reg != 0))
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                                          st_nxt = RD_RSP1;
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                                         else
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                                         begin
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                                           //latch data
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                                                st_nxt = 9;
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                                                cyc_wb = 1'b0;
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                                                stb_wb = 1'b0;
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                                                we_wb  = 1'b0;
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                                                cti_wb = 3'b010;
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                                           //$display ("Data bus word 2: %h", rd_data_mem);
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                                         end
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                                end
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                        10:
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                                begin
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                                        st_nxt = 9;
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                                        op_cnt_nxt = 0;
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                                        cyc_wb = 1'b0;
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                                        stb_wb = 1'b0;
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                                        we_wb = 1'b0;
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                                        //adr_cnt_nxt = adr_cnt_reg + 16;
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                                        cti_wb = 3'b111;
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                                end
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                        9:
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                    begin
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                      if (op_cnt_reg == 0)
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                                begin
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                                        st_nxt = WB_IDLE;//RD_REQ;
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                                        op_cnt_nxt = 0;
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                                        adr_cnt_nxt = 0;
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                                        //adr_cnt_nxt[30] = 1;
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                                end
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                                else
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                                begin
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                                        st_nxt = 9;
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                                        op_cnt_nxt = op_cnt_reg + 1;
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                                        //adr_cnt_nxt = adr_cnt_reg + 32;
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                                end
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                      cyc_wb = 1'b0;
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                                stb_wb = 1'b0;
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                                we_wb  = 1'b0;
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                                cti_wb = 3'b111;
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                    end
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                endcase
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  end
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endmodule

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