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[/] [genesys_ddr2/] [trunk/] [rtl/] [DDR2_Mem.v] - Blame information for rev 2

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: UPT
// Engineer: Oana Boncalo & Alexandru Amaricai
// 
// Create Date:    17:25:32 11/26/2012 
// Design Name: 
// Module Name:    DDR2_Mem 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DDR2_Mem #
  (
   parameter BANK_WIDTH              = 2,
                                       // # of memory bank addr bits.
   parameter CKE_WIDTH               = 1,
                                       // # of memory clock enable outputs.
   parameter CLK_WIDTH               = 2,
                                       // # of clock outputs.
   parameter COL_WIDTH               = 10,
                                       // # of memory column bits.
   parameter CS_NUM                  = 1,
                                       // # of separate memory chip selects.
   parameter CS_WIDTH                = 1,
                                       // # of total memory chip selects.
   parameter CS_BITS                 = 0,
                                       // set to log2(CS_NUM) (rounded up).
   parameter DM_WIDTH                = 8,
                                       // # of data mask bits.
   parameter DQ_WIDTH                = 64,
                                       // # of data width.
   parameter DQ_PER_DQS              = 8,
                                       // # of DQ data bits per strobe.
   parameter DQS_WIDTH               = 8,
                                       // # of DQS strobes.
   parameter DQ_BITS                 = 6,
                                       // set to log2(DQS_WIDTH*DQ_PER_DQS).
   parameter DQS_BITS                = 3,
                                       // set to log2(DQS_WIDTH).
   parameter ODT_WIDTH               = 1,
                                       // # of memory on-die term enables.
   parameter ROW_WIDTH               = 13,
                                       // # of memory row and # of addr bits.
   parameter ADDITIVE_LAT            = 0,
                                       // additive write latency.
   parameter BURST_LEN               = 4,
                                       // burst length (in double words).
   parameter BURST_TYPE              = 0,
                                       // burst type (=0 seq; =1 interleaved).
   parameter CAS_LAT                 = 3,
                                       // CAS latency.
   parameter ECC_ENABLE              = 0,
                                       // enable ECC (=1 enable).
   parameter APPDATA_WIDTH           = 128,
                                       // # of usr read/write data bus bits.
   parameter MULTI_BANK_EN           = 1,
                                       // Keeps multiple banks open. (= 1 enable).
   parameter TWO_T_TIME_EN           = 1,
                                       // 2t timing for unbuffered dimms.
   parameter ODT_TYPE                = 1,
                                       // ODT (=0(none),=1(75),=2(150),=3(50)).
   parameter REDUCE_DRV              = 0,
                                       // reduced strength mem I/O (=1 yes).
   parameter REG_ENABLE              = 0,
                                       // registered addr/ctrl (=1 yes).
   parameter TREFI_NS                = 7800,
                                       // auto refresh interval (ns).
   parameter TRAS                    = 40000,
                                       // active->precharge delay.
   parameter TRCD                    = 15000,
                                       // active->read/write delay.
   parameter TRFC                    = 105000,
                                       // refresh->refresh, refresh->active delay.
   parameter TRP                     = 15000,
                                       // precharge->command delay.
   parameter TRTP                    = 7500,
                                       // read->precharge delay.
   parameter TWR                     = 15000,
                                       // used to determine write->precharge.
   parameter TWTR                    = 7500,
                                       // write->read delay.
   parameter HIGH_PERFORMANCE_MODE   = "TRUE",
                              // # = TRUE, the IODELAY performance mode is set
                              // to high.
                              // # = FALSE, the IODELAY performance mode is set
                              // to low.
   parameter SIM_ONLY                = 0,
                                       // = 1 to skip SDRAM power up delay.
   parameter DEBUG_EN                = 0,
                                       // Enable debug signals/controls.
                                       // When this parameter is changed from 0 to 1,
                                       // make sure to uncomment the coregen commands
                                       // in ise_flow.bat or create_ise.bat files in
                                       // par folder.
   parameter CLK_PERIOD              = 8000,
                                       // Core/Memory clock period (in ps).
   parameter RST_ACT_LOW             = 0
                                       // =1 for active low reset, =0 for active high.
   )
        (
        input sysRst,  //Asynchronous reset
        input sysClk,
        output clk0,
        output rst0,
        output clkTFT10,
        output clkTFT10_180,
 
 
        input [7:0] sw,
        output [7:0] leds,
 
        inout  [DQ_WIDTH-1:0]              ddr2_dq,
   output [ROW_WIDTH-1:0]             ddr2_a,
   output [BANK_WIDTH-1:0]            ddr2_ba,
   output                             ddr2_ras_n,
   output                             ddr2_cas_n,
   output                             ddr2_we_n,
   output [CS_WIDTH-1:0]              ddr2_cs_n,
   output [ODT_WIDTH-1:0]             ddr2_odt,
   output [CKE_WIDTH-1:0]             ddr2_cke,
   output [DM_WIDTH-1:0]              ddr2_dm,
        inout  [DQS_WIDTH-1:0]             ddr2_dqs,
   inout  [DQS_WIDTH-1:0]             ddr2_dqs_n,
   output [CLK_WIDTH-1:0]             ddr2_ck,
   output [CLK_WIDTH-1:0]             ddr2_ck_n,
//rd/wr command signals from bus
//address, data & data mask from bus if
//wishbone if signals
         input                                                                  cyc_wb,
         input                                                                  stb_wb,
         input  [30:0]                                           address_wb,
         input  [(APPDATA_WIDTH/8)-1:0]  sel_wb, //write mask     
         input  [APPDATA_WIDTH-1:0]              wr_data_wb, // write data
         input                                                                  we_wb,
         input  [2:0]                                                    cti_wb,
         input   [1:0]                                                   bte_wb,
         //to wishbone from memory interface
         output                                                                 ack_mem, err_mem, rty_mem,
         output [APPDATA_WIDTH-1:0]              rd_data_wb, // rd data
         output [3:0]                                               wb_state,
         output reg [2:0]                                                state,
         output phy_init_done_o
 
    );
 
        localparam IDLE  = 3'b000;
        localparam WR_OP_D0 = 3'b001;
        localparam WR_OP_D1 = 3'b010;
        localparam RD_OP  = 3'b011;
        localparam WAIT_RD_RSP  = 3'b100;
        localparam WAIT_END_OF_RD_RSP  = 3'b101;
        localparam RD_COUNTER_TIMEOUT  = 3'b110;
 
        localparam WR_IDLE_FIRST_DATA = 2'b00;
        localparam WR_SECOND_DATA     = 2'b01;
        localparam WR_THIRD_DATA      = 2'b10;
        localparam WR_FOURTH_DATA     = 2'b11;
 
 
        wire clk0_125;
        wire clk0Phase90;
        wire clk0Div2;
        wire outSysClk1;
        wire outSysClk2;
        wire clk200;
        wire locked;
 
        //reset logic signal
        wire async_rst;
        wire pll_rst;
 
        wire [30:0] address;
        wire [2:0]       cmd;
        wire    af_we;
        wire    wd_we;
        wire [127:0]     wr_data;
        wire [16:0]              wr_mask;
        wire [127:0]     rd_data;
        wire    rd_valid;
        wire    wd_fifo_full;
        wire    a_fifo_full;
        wire    phy_init_done;
        wire clk_tb;
        wire rts_tb;
        wire  rd_cmd;
        wire  wr_cmd;
        wire end_op;
        wire [30:0] bus_if_addr;
        reg  [30:0] test_addr_cnt;
 
        //data for write
        wire [(APPDATA_WIDTH/8)-1:0]         wr_mask_data;
        wire [(APPDATA_WIDTH/16)-1:0]        wr_mask_data_fall;
        wire [(APPDATA_WIDTH/16)-1:0]        wr_mask_data_rise;
        reg [1:0]                            wr_state;
        reg [(APPDATA_WIDTH/2)-1:0]          wr_data_fall
                                       /* synthesis syn_maxfan = 2 */;
        reg [(APPDATA_WIDTH/2)-1:0]          wr_data_rise
                                        /* synthesis syn_maxfan = 2 */;
        //data for write
        wire  [APPDATA_WIDTH-1:0]         bus_if_wr_data;
        wire  [(APPDATA_WIDTH/8)-1:0]     bus_if_wr_mask_data;
        //data from memory if to request the second 128 bit data word
        wire                                                                             req_wd;
        wire                                                                             idelay_ctrl_rdy;
 
        //rd/wr command signals from bus
        //address, data & data mask from bus if
        wire  [30:0]                                                      wb_bus_if_addr;
        wire  [APPDATA_WIDTH-1:0]         bus_if_wr_data0, bus_if_wr_data1;
        wire  [(APPDATA_WIDTH/8)-1:0]     bus_if_wr_mask_data0, bus_if_wr_mask_data1;
        wire                                                                        mem_rd_cmd;
        wire                                                                             mem_wr_cmd;
        wire [APPDATA_WIDTH-1:0]          bus_if_rd_data;
        reg   [4:0]                                                               counter;
        wire                                                                             rd_failed;
 
        assign phy_init_done_o = phy_init_done;
 
//global reset logic 
debounceRst global_rst_logic(
    .clk (sysClk),
    .noisyRst (sysRst),
         .PLLLocked (locked),
    .cleanPLLRst (pll_rst),
         .cleanAsyncRst (async_rst)
    );
 
 
 
clkGenPLL clkGen(
        .sysClk (sysClk),
        .sysRst (pll_rst),  //Asynchronous PLL reset
        .clk0_125 (clk0_125), //125 Mhz
        .clk0Phase90 (clk0Phase90), //125 MHz clk200 with 90 degree phase
        .clk0Div2 (clk0Div2), //62.5 MHz
        .clk200 (clk200),   //200 MHz clk
        .clkTFT10 (clkTFT10),
        .clkTFT10_180(clkTFT10_180),
        .locked (locked)
    );
        BUFG u_bufg_clk0
    (
     .O (clk0_bufg),
     .I (clk0_125)
     );
 
  BUFG u_bufg_clk90
    (
     .O (clk90_bufg),
     .I (clk0Phase90)
     );
 
  BUFG u_bufg_clk200
    (
     .O (clk200_bufg),
     .I (clk200)
     );
 
   BUFG u_bufg_clkdiv0
    (
     .O (clkdiv0_bufg),
     .I (clk0Div2)
     );
 
 MEMCtrl #
  (
   .BANK_WIDTH (BANK_WIDTH),
                                       // # of memory bank addr bits.
   .CKE_WIDTH (CKE_WIDTH),
                                       // # of memory clock enable outputs.
   .CLK_WIDTH (CLK_WIDTH),
                                       // # of clock outputs.
   .COL_WIDTH (COL_WIDTH),
                                       // # of memory column bits.
   .CS_NUM (CS_NUM),
                                       // # of separate memory chip selects.
   .CS_WIDTH (CS_WIDTH),
                                       // # of total memory chip selects.
   .CS_BITS (CS_BITS),
                                       // set to log2(CS_NUM) (rounded up).
   .DM_WIDTH (DM_WIDTH),
                                       // # of data mask bits.
   .DQ_WIDTH (DQ_WIDTH),
                                       // # of data width.
   .DQ_PER_DQS (DQ_PER_DQS),
                                       // # of DQ data bits per strobe.
   .DQS_WIDTH  (DQS_WIDTH),
                                       // # of DQS strobes.
   .DQ_BITS (DQ_BITS),
                                       // set to log2(DQS_WIDTH*DQ_PER_DQS).
   .DQS_BITS (DQS_BITS),
                                       // set to log2(DQS_WIDTH).
   .ODT_WIDTH (ODT_WIDTH),
                                       // # of memory on-die term enables.
   .ROW_WIDTH (ROW_WIDTH),
                                       // # of memory row and # of addr bits.
   .ADDITIVE_LAT(ADDITIVE_LAT),
                                       // additive write latency.
   .BURST_LEN (BURST_LEN),
                                       // burst length (in double words).
   .BURST_TYPE(BURST_TYPE),
                                       // burst type (=0 seq; =1 interleaved).
   .CAS_LAT (CAS_LAT),
                                       // CAS latency.
   .ECC_ENABLE (ECC_ENABLE),
                                       // enable ECC (=1 enable).
   .APPDATA_WIDTH (APPDATA_WIDTH),
                                       // # of usr read/write data bus bits.
   .MULTI_BANK_EN (MULTI_BANK_EN),
                                       // Keeps multiple banks open. (= 1 enable).
   .TWO_T_TIME_EN (TWO_T_TIME_EN),
                                       // 2t timing for unbuffered dimms.
   .ODT_TYPE (ODT_TYPE),
                                       // ODT (=0(none),=1(75),=2(150),=3(50)).
   .REDUCE_DRV (REDUCE_DRV),
                                       // reduced strength mem I/O (=1 yes).
   .REG_ENABLE (REDUCE_DRV),
                                       // registered addr/ctrl (=1 yes).
   .TREFI_NS (TREFI_NS),
                                       // auto refresh interval (ns).
   .TRAS (TRAS),
                                       // active->precharge delay.
   .TRCD (TRCD),
                                       // active->read/write delay.
   .TRFC (TRFC),
                                       // refresh->refresh, refresh->active delay.
   .TRP (TRP),
                                       // precharge->command delay.
   .TRTP (TRTP),
                                       // read->precharge delay.
   .TWR (TWR),
                                       // used to determine write->precharge.
   .TWTR (TWTR),
                                       // write->read delay.
   .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
                              // # = TRUE, the IODELAY performance mode is set
                              // to high.
                              // # = FALSE, the IODELAY performance mode is set
                              // to low.
   .SIM_ONLY (SIM_ONLY),
                                       // = 1 to skip SDRAM power up delay.
   .DEBUG_EN (DEBUG_EN),
                                       // Enable debug signals/controls.
                                       // When this parameter is changed from 0 to 1,
                                       // make sure to uncomment the coregen commands
                                       // in ise_flow.bat or create_ise.bat files in
                                       // par folder.
   .CLK_PERIOD (CLK_PERIOD),
                                       // Core/Memory clock period (in ps).
   .RST_ACT_LOW (RST_ACT_LOW)
                                       // =1 for active low reset, =0 for active high.
   )
        mig_if
  (
   .ddr2_dq (ddr2_dq),
   .ddr2_a (ddr2_a),
   .ddr2_ba (ddr2_ba),
   .ddr2_ras_n (ddr2_ras_n),
   .ddr2_cas_n (ddr2_cas_n),
   .ddr2_we_n (ddr2_we_n),
   .ddr2_cs_n (ddr2_cs_n),
   .ddr2_odt (ddr2_odt),
   .ddr2_cke (ddr2_cke),
   .ddr2_dm (ddr2_dm),
        .ddr2_dqs (ddr2_dqs),
   .ddr2_dqs_n (ddr2_dqs_n),
   .ddr2_ck (ddr2_ck),
   .ddr2_ck_n (ddr2_ck_n),
 
        //pll & reset
 
        .sys_rst_n (async_rst), //debounced asynchronous reset signal
   .phy_init_done (phy_init_done),
   .locked (locked),
   .rst0_tb (rst0_tb),
   .clk0 (clk0_bufg),
   .clk0_tb (clk0_tb),
   .clk90 (clk90_bufg),
   .clkdiv0 (clkdiv0_bufg),
   .clk200 (clk200_bufg),
 
        //testbench
   .app_wdf_afull (wd_fifo_full),
   .app_af_afull (a_fifo_full),
   .rd_data_valid (rd_valid),
   .app_wdf_wren (wd_we),
   .app_af_wren (af_we),
   .app_af_addr (address),
   .app_af_cmd (cmd),
   .rd_data_fifo_out (rd_data),
   .app_wdf_data (wr_data),
   .app_wdf_mask_data (wr_mask)
   );
 
        assign clk0 = clk0_tb;
        assign rst0 = rst0_tb;
//wishbone bus interface
DDR2_mem_wb_if #
  (
   .APPDATA_WIDTH (128)     // # of usr read/write data bus bits.                                 
        )
        test_ddr2_wb_if
        (
         .clk (clk0_tb),
         .rst (rst0_tb),
         //wishbone if signals
         .cyc_wb (cyc_wb),
         .stb_wb (stb_wb),
         .address_wb (address_wb),
         .sel_wb (sel_wb), //write mask  
         .wr_data_wb (wr_data_wb), // write data
         .we_wb (we_wb),
         .cti_wb (cti_wb),
         .bte_wb (bte_wb),
         //to wishbone from memory interface
         .ack_mem (ack_mem),
         .err_mem (err_mem),
         .rty_mem (rty_mem),
         .rd_data_wb (rd_data_wb), // rd data
 
         //signals to/from memory user interface
         .bus_if_addr (wb_bus_if_addr),
         .bus_if_wr_data0 (bus_if_wr_data0),
         .bus_if_wr_data1 (bus_if_wr_data1),
         .bus_if_wr_mask_data0 (bus_if_wr_mask_data0),
         .bus_if_wr_mask_data1 (bus_if_wr_mask_data1),
         .mem_rd_cmd (mem_rd_cmd),
         .mem_wr_cmd (mem_wr_cmd),
         .rd_valid (rd_valid),
         .end_op (end_op),
         .bus_if_rd_data (bus_if_rd_data),
         .app_wdf_afull (wd_fifo_afull),
    .app_af_afull (a_fifo_afull),
         .phy_init_done (phy_init_done),
         .rd_failed (rd_failed),
         .wb_state (wb_state)
    );
 
// synthesizable test bench provided for wotb designs
  ddr2_user_if_top #
     (
      .BANK_WIDTH        (BANK_WIDTH),
      .COL_WIDTH         (COL_WIDTH),
      .DM_WIDTH          (DM_WIDTH),
      .DQ_WIDTH          (DQ_WIDTH),
      .ROW_WIDTH         (ROW_WIDTH),
      .ECC_ENABLE        (ECC_ENABLE),
      .APPDATA_WIDTH     (APPDATA_WIDTH),
      .BURST_LEN         (BURST_LEN)
      )
   u_user_if_top
     (
      .clk0              (clk0_tb),
      .rst0              (rst0_tb),
      .app_af_afull      (a_fifo_full),
      .app_wdf_afull     (wd_fifo_full),
      .rd_data_valid     (rd_valid),
      .rd_data_fifo_out  (rd_data),
      .phy_init_done     (phy_init_done),
                .rd_cmd                          (rd_cmd),
                .wr_cmd                          (wr_cmd),
                .bus_if_addr       (bus_if_addr),
                .end_op                          (end_op),
                .req_wd            (req_wd),
                .bus_if_wr_mask_data(bus_if_wr_mask_data),
                .bus_if_wr_data    (bus_if_wr_data),
      .app_af_wren       (af_we),
      .app_af_cmd        (cmd),
      .app_af_addr       (address),
      .app_wdf_wren      (wd_we),
      .app_wdf_data      (wr_data),
      .app_wdf_mask_data (wr_mask),
      .error             (error),
      .error_cmp         (error_cmp)
      );
 
 
        assign rd_failed = (state == RD_COUNTER_TIMEOUT)? 1'b1: 1'b0;
 
        always @(posedge clk0_tb)
        begin
                if (rst0_tb)
                        begin
                                state <= 0;
                        end
                else
                        begin
                                case (state)
                                        IDLE:
                                                begin
                                                        //check if memory if is available for commands
                                                        //i.e. initialization done & ready for WR
                                                        if (mem_wr_cmd)
                                                                state <= WR_OP_D0;
                                                        else if (mem_rd_cmd)
                                                                state <= RD_OP;
                                                end
                                        RD_OP:
                                                begin
                                                        if (end_op)
                                                                state <= WAIT_RD_RSP;
                                                        else
                                                                state <= RD_OP;
                                                end
                                        WAIT_RD_RSP:
                                                begin
                                                        if (rd_valid)
                                                                state <= WAIT_END_OF_RD_RSP;
                                                        else if (counter == 0)
                                                                state <= RD_COUNTER_TIMEOUT;
                                                end
                                         WAIT_END_OF_RD_RSP:
                                                        if (!rd_valid)
                                                                state <= IDLE;
                                                        else
                                                                state <= WAIT_END_OF_RD_RSP;
                                         WR_OP_D0:
                                                begin
                                                        //signal for first data word latch and data byte en and address 
                                                        //generate bus ack/request for second data
                                                        if (req_wd) //this is wd_fifo_we
                                                                state <= WR_OP_D1;
                                                        else
                                                                state <= WR_OP_D0;
                                                end
                                         WR_OP_D1:
                                                begin
                                                        //signal for second data word latch and then wait for 
                                                        //end of operation
                                                        if (end_op)
                                                                state <= RD_OP;
                                                        else
                                                                state <= WR_OP_D1;
                                                end
                                        RD_COUNTER_TIMEOUT:
                                                begin
                                                        state <= IDLE;
                                                end
                                endcase
                        end
        end
        assign bus_if_rd_data = rd_data;
 
        //latch address from wishbone if
        always @(posedge clk0_tb)
        begin
                if (rst0_tb)
                        test_addr_cnt <= 0;
                else
                        if (wr_cmd)
                                test_addr_cnt <= wb_bus_if_addr;
        end
        assign bus_if_addr = test_addr_cnt;
 
        //timeout counter fro RD
        always @(posedge clk0_tb)
        begin
                if (rst0_tb)
                        counter <= 0;
                else
                        if (state == RD_OP)
                                counter <= 24;
                        else if (state == WAIT_RD_RSP)
                                counter <= counter -  1'b1;
        end
 
  //generate data for write
  //***************************************************************************
  // DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE
  //***************************************************************************
 
  assign bus_if_wr_data      = {wr_data_fall, wr_data_rise};
  assign bus_if_wr_mask_data = {wr_mask_data_fall, wr_mask_data_rise};
 
  //*****************************************************************
  // For now, don't vary data masks
  //*****************************************************************
 
  assign wr_mask_data_rise = {(APPDATA_WIDTH/8){1'b0}};
  assign wr_mask_data_fall = {(APPDATA_WIDTH/8){1'b0}};
 
  //*****************************************************************
  // Write data logic
  //*****************************************************************
 
  // write data generation
  //synthesis attribute max_fanout of wr_data_fall is 2
  //synthesis attribute max_fanout of wr_data_rise is 2
  always @(posedge clk0_tb) begin
    if (rst0_tb) begin
      wr_state <= WR_IDLE_FIRST_DATA;
    end else begin
      case (wr_state)
        WR_IDLE_FIRST_DATA:
          if (req_wd) begin
            wr_state <= WR_SECOND_DATA;
          end
        WR_SECOND_DATA:
            if (end_op) //begin
                                        wr_state <= WR_IDLE_FIRST_DATA;
      endcase
    end
  end
 
  //get data from memory if
         always @(*)
         begin
                wr_data_rise = {(APPDATA_WIDTH/2){1'bx}};
                wr_data_fall = {(APPDATA_WIDTH/2){1'bx}};
                case (wr_state)
                  WR_IDLE_FIRST_DATA:
                         begin
                                wr_data_rise = bus_if_wr_data0[(APPDATA_WIDTH/2)-1:0];
                                wr_data_fall = bus_if_wr_data0[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];
                         end
                  WR_SECOND_DATA:
                         begin
                                wr_data_rise = bus_if_wr_data1[(APPDATA_WIDTH/2)-1:0];
                                wr_data_fall = bus_if_wr_data1[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];
                         end
                endcase
         end
 
        assign wr_cmd = ((state == WR_OP_D0) && !end_op)? 1'b1:1'b0;
        assign rd_cmd = ((state == RD_OP) && !end_op)? 1'b1:1'b0;
 
 
endmodule

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[/] [genesys_ddr2/] [trunk/] [rtl/] [DDR2_Mem.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	oana.bonca	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company: UPT`
4			`// Engineer: Oana Boncalo & Alexandru Amaricai`
5			`//`
6			`// Create Date: 17:25:32 11/26/2012`
7			`// Design Name:`
8			`// Module Name: DDR2_Mem`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module DDR2_Mem #`
22			`(`
23			`parameter BANK_WIDTH = 2,`
24			`// # of memory bank addr bits.`
25			`parameter CKE_WIDTH = 1,`
26			`// # of memory clock enable outputs.`
27			`parameter CLK_WIDTH = 2,`
28			`// # of clock outputs.`
29			`parameter COL_WIDTH = 10,`
30			`// # of memory column bits.`
31			`parameter CS_NUM = 1,`
32			`// # of separate memory chip selects.`
33			`parameter CS_WIDTH = 1,`
34			`// # of total memory chip selects.`
35			`parameter CS_BITS = 0,`
36			`// set to log2(CS_NUM) (rounded up).`
37			`parameter DM_WIDTH = 8,`
38			`// # of data mask bits.`
39			`parameter DQ_WIDTH = 64,`
40			`// # of data width.`
41			`parameter DQ_PER_DQS = 8,`
42			`// # of DQ data bits per strobe.`
43			`parameter DQS_WIDTH = 8,`
44			`// # of DQS strobes.`
45			`parameter DQ_BITS = 6,`
46			`// set to log2(DQS_WIDTH*DQ_PER_DQS).`
47			`parameter DQS_BITS = 3,`
48			`// set to log2(DQS_WIDTH).`
49			`parameter ODT_WIDTH = 1,`
50			`// # of memory on-die term enables.`
51			`parameter ROW_WIDTH = 13,`
52			`// # of memory row and # of addr bits.`
53			`parameter ADDITIVE_LAT = 0,`
54			`// additive write latency.`
55			`parameter BURST_LEN = 4,`
56			`// burst length (in double words).`
57			`parameter BURST_TYPE = 0,`
58			`// burst type (=0 seq; =1 interleaved).`
59			`parameter CAS_LAT = 3,`
60			`// CAS latency.`
61			`parameter ECC_ENABLE = 0,`
62			`// enable ECC (=1 enable).`
63			`parameter APPDATA_WIDTH = 128,`
64			`// # of usr read/write data bus bits.`
65			`parameter MULTI_BANK_EN = 1,`
66			`// Keeps multiple banks open. (= 1 enable).`
67			`parameter TWO_T_TIME_EN = 1,`
68			`// 2t timing for unbuffered dimms.`
69			`parameter ODT_TYPE = 1,`
70			`// ODT (=0(none),=1(75),=2(150),=3(50)).`
71			`parameter REDUCE_DRV = 0,`
72			`// reduced strength mem I/O (=1 yes).`
73			`parameter REG_ENABLE = 0,`
74			`// registered addr/ctrl (=1 yes).`
75			`parameter TREFI_NS = 7800,`
76			`// auto refresh interval (ns).`
77			`parameter TRAS = 40000,`
78			`// active->precharge delay.`
79			`parameter TRCD = 15000,`
80			`// active->read/write delay.`
81			`parameter TRFC = 105000,`
82			`// refresh->refresh, refresh->active delay.`
83			`parameter TRP = 15000,`
84			`// precharge->command delay.`
85			`parameter TRTP = 7500,`
86			`// read->precharge delay.`
87			`parameter TWR = 15000,`
88			`// used to determine write->precharge.`
89			`parameter TWTR = 7500,`
90			`// write->read delay.`
91			`parameter HIGH_PERFORMANCE_MODE = "TRUE",`
92			`// # = TRUE, the IODELAY performance mode is set`
93			`// to high.`
94			`// # = FALSE, the IODELAY performance mode is set`
95			`// to low.`
96			`parameter SIM_ONLY = 0,`
97			`// = 1 to skip SDRAM power up delay.`
98			`parameter DEBUG_EN = 0,`
99			`// Enable debug signals/controls.`
100			`// When this parameter is changed from 0 to 1,`
101			`// make sure to uncomment the coregen commands`
102			`// in ise_flow.bat or create_ise.bat files in`
103			`// par folder.`
104			`parameter CLK_PERIOD = 8000,`
105			`// Core/Memory clock period (in ps).`
106			`parameter RST_ACT_LOW = 0`
107			`// =1 for active low reset, =0 for active high.`
108			`)`
109			`(`
110			`input sysRst, //Asynchronous reset`
111			`input sysClk,`
112			`output clk0,`
113			`output rst0,`
114			`output clkTFT10,`
115			`output clkTFT10_180,`
116
117
118			`input [7:0] sw,`
119			`output [7:0] leds,`
120
121			`inout [DQ_WIDTH-1:0] ddr2_dq,`
122			`output [ROW_WIDTH-1:0] ddr2_a,`
123			`output [BANK_WIDTH-1:0] ddr2_ba,`
124			`output ddr2_ras_n,`
125			`output ddr2_cas_n,`
126			`output ddr2_we_n,`
127			`output [CS_WIDTH-1:0] ddr2_cs_n,`
128			`output [ODT_WIDTH-1:0] ddr2_odt,`
129			`output [CKE_WIDTH-1:0] ddr2_cke,`
130			`output [DM_WIDTH-1:0] ddr2_dm,`
131			`inout [DQS_WIDTH-1:0] ddr2_dqs,`
132			`inout [DQS_WIDTH-1:0] ddr2_dqs_n,`
133			`output [CLK_WIDTH-1:0] ddr2_ck,`
134			`output [CLK_WIDTH-1:0] ddr2_ck_n,`
135			`//rd/wr command signals from bus`
136			`//address, data & data mask from bus if`
137			`//wishbone if signals`
138			`input cyc_wb,`
139			`input stb_wb,`
140			`input [30:0] address_wb,`
141			`input [(APPDATA_WIDTH/8)-1:0] sel_wb, //write mask`
142			`input [APPDATA_WIDTH-1:0] wr_data_wb, // write data`
143			`input we_wb,`
144			`input [2:0] cti_wb,`
145			`input [1:0] bte_wb,`
146			`//to wishbone from memory interface`
147			`output ack_mem, err_mem, rty_mem,`
148			`output [APPDATA_WIDTH-1:0] rd_data_wb, // rd data`
149			`output [3:0] wb_state,`
150			`output reg [2:0] state,`
151			`output phy_init_done_o`
152
153			`);`
154
155			`localparam IDLE = 3'b000;`
156			`localparam WR_OP_D0 = 3'b001;`
157			`localparam WR_OP_D1 = 3'b010;`
158			`localparam RD_OP = 3'b011;`
159			`localparam WAIT_RD_RSP = 3'b100;`
160			`localparam WAIT_END_OF_RD_RSP = 3'b101;`
161			`localparam RD_COUNTER_TIMEOUT = 3'b110;`
162
163			`localparam WR_IDLE_FIRST_DATA = 2'b00;`
164			`localparam WR_SECOND_DATA = 2'b01;`
165			`localparam WR_THIRD_DATA = 2'b10;`
166			`localparam WR_FOURTH_DATA = 2'b11;`
167
168
169			`wire clk0_125;`
170			`wire clk0Phase90;`
171			`wire clk0Div2;`
172			`wire outSysClk1;`
173			`wire outSysClk2;`
174			`wire clk200;`
175			`wire locked;`
176
177			`//reset logic signal`
178			`wire async_rst;`
179			`wire pll_rst;`
180
181			`wire [30:0] address;`
182			`wire [2:0] cmd;`
183			`wire af_we;`
184			`wire wd_we;`
185			`wire [127:0] wr_data;`
186			`wire [16:0] wr_mask;`
187			`wire [127:0] rd_data;`
188			`wire rd_valid;`
189			`wire wd_fifo_full;`
190			`wire a_fifo_full;`
191			`wire phy_init_done;`
192			`wire clk_tb;`
193			`wire rts_tb;`
194			`wire rd_cmd;`
195			`wire wr_cmd;`
196			`wire end_op;`
197			`wire [30:0] bus_if_addr;`
198			`reg [30:0] test_addr_cnt;`
199
200			`//data for write`
201			`wire [(APPDATA_WIDTH/8)-1:0] wr_mask_data;`
202			`wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_fall;`
203			`wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_rise;`
204			`reg [1:0] wr_state;`
205			`reg [(APPDATA_WIDTH/2)-1:0] wr_data_fall`
206			`/* synthesis syn_maxfan = 2 */;`
207			`reg [(APPDATA_WIDTH/2)-1:0] wr_data_rise`
208			`/* synthesis syn_maxfan = 2 */;`
209			`//data for write`
210			`wire [APPDATA_WIDTH-1:0] bus_if_wr_data;`
211			`wire [(APPDATA_WIDTH/8)-1:0] bus_if_wr_mask_data;`
212			`//data from memory if to request the second 128 bit data word`
213			`wire req_wd;`
214			`wire idelay_ctrl_rdy;`
215
216			`//rd/wr command signals from bus`
217			`//address, data & data mask from bus if`
218			`wire [30:0] wb_bus_if_addr;`
219			`wire [APPDATA_WIDTH-1:0] bus_if_wr_data0, bus_if_wr_data1;`
220			`wire [(APPDATA_WIDTH/8)-1:0] bus_if_wr_mask_data0, bus_if_wr_mask_data1;`
221			`wire mem_rd_cmd;`
222			`wire mem_wr_cmd;`
223			`wire [APPDATA_WIDTH-1:0] bus_if_rd_data;`
224			`reg [4:0] counter;`
225			`wire rd_failed;`
226
227			`assign phy_init_done_o = phy_init_done;`
228
229			`//global reset logic`
230			`debounceRst global_rst_logic(`
231			`.clk (sysClk),`
232			`.noisyRst (sysRst),`
233			`.PLLLocked (locked),`
234			`.cleanPLLRst (pll_rst),`
235			`.cleanAsyncRst (async_rst)`
236			`);`
237
238
239
240			`clkGenPLL clkGen(`
241			`.sysClk (sysClk),`
242			`.sysRst (pll_rst), //Asynchronous PLL reset`
243			`.clk0_125 (clk0_125), //125 Mhz`
244			`.clk0Phase90 (clk0Phase90), //125 MHz clk200 with 90 degree phase`
245			`.clk0Div2 (clk0Div2), //62.5 MHz`
246			`.clk200 (clk200), //200 MHz clk`
247			`.clkTFT10 (clkTFT10),`
248			`.clkTFT10_180(clkTFT10_180),`
249			`.locked (locked)`
250			`);`
251			`BUFG u_bufg_clk0`
252			`(`
253			`.O (clk0_bufg),`
254			`.I (clk0_125)`
255			`);`
256
257			`BUFG u_bufg_clk90`
258			`(`
259			`.O (clk90_bufg),`
260			`.I (clk0Phase90)`
261			`);`
262
263			`BUFG u_bufg_clk200`
264			`(`
265			`.O (clk200_bufg),`
266			`.I (clk200)`
267			`);`
268
269			`BUFG u_bufg_clkdiv0`
270			`(`
271			`.O (clkdiv0_bufg),`
272			`.I (clk0Div2)`
273			`);`
274
275			`MEMCtrl #`
276			`(`
277			`.BANK_WIDTH (BANK_WIDTH),`
278			`// # of memory bank addr bits.`
279			`.CKE_WIDTH (CKE_WIDTH),`
280			`// # of memory clock enable outputs.`
281			`.CLK_WIDTH (CLK_WIDTH),`
282			`// # of clock outputs.`
283			`.COL_WIDTH (COL_WIDTH),`
284			`// # of memory column bits.`
285			`.CS_NUM (CS_NUM),`
286			`// # of separate memory chip selects.`
287			`.CS_WIDTH (CS_WIDTH),`
288			`// # of total memory chip selects.`
289			`.CS_BITS (CS_BITS),`
290			`// set to log2(CS_NUM) (rounded up).`
291			`.DM_WIDTH (DM_WIDTH),`
292			`// # of data mask bits.`
293			`.DQ_WIDTH (DQ_WIDTH),`
294			`// # of data width.`
295			`.DQ_PER_DQS (DQ_PER_DQS),`
296			`// # of DQ data bits per strobe.`
297			`.DQS_WIDTH (DQS_WIDTH),`
298			`// # of DQS strobes.`
299			`.DQ_BITS (DQ_BITS),`
300			`// set to log2(DQS_WIDTH*DQ_PER_DQS).`
301			`.DQS_BITS (DQS_BITS),`
302			`// set to log2(DQS_WIDTH).`
303			`.ODT_WIDTH (ODT_WIDTH),`
304			`// # of memory on-die term enables.`
305			`.ROW_WIDTH (ROW_WIDTH),`
306			`// # of memory row and # of addr bits.`
307			`.ADDITIVE_LAT(ADDITIVE_LAT),`
308			`// additive write latency.`
309			`.BURST_LEN (BURST_LEN),`
310			`// burst length (in double words).`
311			`.BURST_TYPE(BURST_TYPE),`
312			`// burst type (=0 seq; =1 interleaved).`
313			`.CAS_LAT (CAS_LAT),`
314			`// CAS latency.`
315			`.ECC_ENABLE (ECC_ENABLE),`
316			`// enable ECC (=1 enable).`
317			`.APPDATA_WIDTH (APPDATA_WIDTH),`
318			`// # of usr read/write data bus bits.`
319			`.MULTI_BANK_EN (MULTI_BANK_EN),`
320			`// Keeps multiple banks open. (= 1 enable).`
321			`.TWO_T_TIME_EN (TWO_T_TIME_EN),`
322			`// 2t timing for unbuffered dimms.`
323			`.ODT_TYPE (ODT_TYPE),`
324			`// ODT (=0(none),=1(75),=2(150),=3(50)).`
325			`.REDUCE_DRV (REDUCE_DRV),`
326			`// reduced strength mem I/O (=1 yes).`
327			`.REG_ENABLE (REDUCE_DRV),`
328			`// registered addr/ctrl (=1 yes).`
329			`.TREFI_NS (TREFI_NS),`
330			`// auto refresh interval (ns).`
331			`.TRAS (TRAS),`
332			`// active->precharge delay.`
333			`.TRCD (TRCD),`
334			`// active->read/write delay.`
335			`.TRFC (TRFC),`
336			`// refresh->refresh, refresh->active delay.`
337			`.TRP (TRP),`
338			`// precharge->command delay.`
339			`.TRTP (TRTP),`
340			`// read->precharge delay.`
341			`.TWR (TWR),`
342			`// used to determine write->precharge.`
343			`.TWTR (TWTR),`
344			`// write->read delay.`
345			`.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),`
346			`// # = TRUE, the IODELAY performance mode is set`
347			`// to high.`
348			`// # = FALSE, the IODELAY performance mode is set`
349			`// to low.`
350			`.SIM_ONLY (SIM_ONLY),`
351			`// = 1 to skip SDRAM power up delay.`
352			`.DEBUG_EN (DEBUG_EN),`
353			`// Enable debug signals/controls.`
354			`// When this parameter is changed from 0 to 1,`
355			`// make sure to uncomment the coregen commands`
356			`// in ise_flow.bat or create_ise.bat files in`
357			`// par folder.`
358			`.CLK_PERIOD (CLK_PERIOD),`
359			`// Core/Memory clock period (in ps).`
360			`.RST_ACT_LOW (RST_ACT_LOW)`
361			`// =1 for active low reset, =0 for active high.`
362			`)`
363			`mig_if`
364			`(`
365			`.ddr2_dq (ddr2_dq),`
366			`.ddr2_a (ddr2_a),`
367			`.ddr2_ba (ddr2_ba),`
368			`.ddr2_ras_n (ddr2_ras_n),`
369			`.ddr2_cas_n (ddr2_cas_n),`
370			`.ddr2_we_n (ddr2_we_n),`
371			`.ddr2_cs_n (ddr2_cs_n),`
372			`.ddr2_odt (ddr2_odt),`
373			`.ddr2_cke (ddr2_cke),`
374			`.ddr2_dm (ddr2_dm),`
375			`.ddr2_dqs (ddr2_dqs),`
376			`.ddr2_dqs_n (ddr2_dqs_n),`
377			`.ddr2_ck (ddr2_ck),`
378			`.ddr2_ck_n (ddr2_ck_n),`
379
380			`//pll & reset`
381
382			`.sys_rst_n (async_rst), //debounced asynchronous reset signal`
383			`.phy_init_done (phy_init_done),`
384			`.locked (locked),`
385			`.rst0_tb (rst0_tb),`
386			`.clk0 (clk0_bufg),`
387			`.clk0_tb (clk0_tb),`
388			`.clk90 (clk90_bufg),`
389			`.clkdiv0 (clkdiv0_bufg),`
390			`.clk200 (clk200_bufg),`
391
392			`//testbench`
393			`.app_wdf_afull (wd_fifo_full),`
394			`.app_af_afull (a_fifo_full),`
395			`.rd_data_valid (rd_valid),`
396			`.app_wdf_wren (wd_we),`
397			`.app_af_wren (af_we),`
398			`.app_af_addr (address),`
399			`.app_af_cmd (cmd),`
400			`.rd_data_fifo_out (rd_data),`
401			`.app_wdf_data (wr_data),`
402			`.app_wdf_mask_data (wr_mask)`
403			`);`
404
405			`assign clk0 = clk0_tb;`
406			`assign rst0 = rst0_tb;`
407			`//wishbone bus interface`
408			`DDR2_mem_wb_if #`
409			`(`
410			`.APPDATA_WIDTH (128) // # of usr read/write data bus bits.`
411			`)`
412			`test_ddr2_wb_if`
413			`(`
414			`.clk (clk0_tb),`
415			`.rst (rst0_tb),`
416			`//wishbone if signals`
417			`.cyc_wb (cyc_wb),`
418			`.stb_wb (stb_wb),`
419			`.address_wb (address_wb),`
420			`.sel_wb (sel_wb), //write mask`
421			`.wr_data_wb (wr_data_wb), // write data`
422			`.we_wb (we_wb),`
423			`.cti_wb (cti_wb),`
424			`.bte_wb (bte_wb),`
425			`//to wishbone from memory interface`
426			`.ack_mem (ack_mem),`
427			`.err_mem (err_mem),`
428			`.rty_mem (rty_mem),`
429			`.rd_data_wb (rd_data_wb), // rd data`
430
431			`//signals to/from memory user interface`
432			`.bus_if_addr (wb_bus_if_addr),`
433			`.bus_if_wr_data0 (bus_if_wr_data0),`
434			`.bus_if_wr_data1 (bus_if_wr_data1),`
435			`.bus_if_wr_mask_data0 (bus_if_wr_mask_data0),`
436			`.bus_if_wr_mask_data1 (bus_if_wr_mask_data1),`
437			`.mem_rd_cmd (mem_rd_cmd),`
438			`.mem_wr_cmd (mem_wr_cmd),`
439			`.rd_valid (rd_valid),`
440			`.end_op (end_op),`
441			`.bus_if_rd_data (bus_if_rd_data),`
442			`.app_wdf_afull (wd_fifo_afull),`
443			`.app_af_afull (a_fifo_afull),`
444			`.phy_init_done (phy_init_done),`
445			`.rd_failed (rd_failed),`
446			`.wb_state (wb_state)`
447			`);`
448
449			`// synthesizable test bench provided for wotb designs`
450			`ddr2_user_if_top #`
451			`(`
452			`.BANK_WIDTH (BANK_WIDTH),`
453			`.COL_WIDTH (COL_WIDTH),`
454			`.DM_WIDTH (DM_WIDTH),`
455			`.DQ_WIDTH (DQ_WIDTH),`
456			`.ROW_WIDTH (ROW_WIDTH),`
457			`.ECC_ENABLE (ECC_ENABLE),`
458			`.APPDATA_WIDTH (APPDATA_WIDTH),`
459			`.BURST_LEN (BURST_LEN)`
460			`)`
461			`u_user_if_top`
462			`(`
463			`.clk0 (clk0_tb),`
464			`.rst0 (rst0_tb),`
465			`.app_af_afull (a_fifo_full),`
466			`.app_wdf_afull (wd_fifo_full),`
467			`.rd_data_valid (rd_valid),`
468			`.rd_data_fifo_out (rd_data),`
469			`.phy_init_done (phy_init_done),`
470			`.rd_cmd (rd_cmd),`
471			`.wr_cmd (wr_cmd),`
472			`.bus_if_addr (bus_if_addr),`
473			`.end_op (end_op),`
474			`.req_wd (req_wd),`
475			`.bus_if_wr_mask_data(bus_if_wr_mask_data),`
476			`.bus_if_wr_data (bus_if_wr_data),`
477			`.app_af_wren (af_we),`
478			`.app_af_cmd (cmd),`
479			`.app_af_addr (address),`
480			`.app_wdf_wren (wd_we),`
481			`.app_wdf_data (wr_data),`
482			`.app_wdf_mask_data (wr_mask),`
483			`.error (error),`
484			`.error_cmp (error_cmp)`
485			`);`
486
487
488			`assign rd_failed = (state == RD_COUNTER_TIMEOUT)? 1'b1: 1'b0;`
489
490			`always @(posedge clk0_tb)`
491			`begin`
492			`if (rst0_tb)`
493			`begin`
494			`state <= 0;`
495			`end`
496			`else`
497			`begin`
498			`case (state)`
499			`IDLE:`
500			`begin`
501			`//check if memory if is available for commands`
502			`//i.e. initialization done & ready for WR`
503			`if (mem_wr_cmd)`
504			`state <= WR_OP_D0;`
505			`else if (mem_rd_cmd)`
506			`state <= RD_OP;`
507			`end`
508			`RD_OP:`
509			`begin`
510			`if (end_op)`
511			`state <= WAIT_RD_RSP;`
512			`else`
513			`state <= RD_OP;`
514			`end`
515			`WAIT_RD_RSP:`
516			`begin`
517			`if (rd_valid)`
518			`state <= WAIT_END_OF_RD_RSP;`
519			`else if (counter == 0)`
520			`state <= RD_COUNTER_TIMEOUT;`
521			`end`
522			`WAIT_END_OF_RD_RSP:`
523			`if (!rd_valid)`
524			`state <= IDLE;`
525			`else`
526			`state <= WAIT_END_OF_RD_RSP;`
527			`WR_OP_D0:`
528			`begin`
529			`//signal for first data word latch and data byte en and address`
530			`//generate bus ack/request for second data`
531			`if (req_wd) //this is wd_fifo_we`
532			`state <= WR_OP_D1;`
533			`else`
534			`state <= WR_OP_D0;`
535			`end`
536			`WR_OP_D1:`
537			`begin`
538			`//signal for second data word latch and then wait for`
539			`//end of operation`
540			`if (end_op)`
541			`state <= RD_OP;`
542			`else`
543			`state <= WR_OP_D1;`
544			`end`
545			`RD_COUNTER_TIMEOUT:`
546			`begin`
547			`state <= IDLE;`
548			`end`
549			`endcase`
550			`end`
551			`end`
552			`assign bus_if_rd_data = rd_data;`
553
554			`//latch address from wishbone if`
555			`always @(posedge clk0_tb)`
556			`begin`
557			`if (rst0_tb)`
558			`test_addr_cnt <= 0;`
559			`else`
560			`if (wr_cmd)`
561			`test_addr_cnt <= wb_bus_if_addr;`
562			`end`
563			`assign bus_if_addr = test_addr_cnt;`
564
565			`//timeout counter fro RD`
566			`always @(posedge clk0_tb)`
567			`begin`
568			`if (rst0_tb)`
569			`counter <= 0;`
570			`else`
571			`if (state == RD_OP)`
572			`counter <= 24;`
573			`else if (state == WAIT_RD_RSP)`
574			`counter <= counter - 1'b1;`
575			`end`
576
577			`//generate data for write`
578			`//***************************************************************************`
579			`// DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE`
580			`//***************************************************************************`
581
582			`assign bus_if_wr_data = {wr_data_fall, wr_data_rise};`
583			`assign bus_if_wr_mask_data = {wr_mask_data_fall, wr_mask_data_rise};`
584
585			`//*****************************************************************`
586			`// For now, don't vary data masks`
587			`//*****************************************************************`
588
589			`assign wr_mask_data_rise = {(APPDATA_WIDTH/8){1'b0}};`
590			`assign wr_mask_data_fall = {(APPDATA_WIDTH/8){1'b0}};`
591
592			`//*****************************************************************`
593			`// Write data logic`
594			`//*****************************************************************`
595
596			`// write data generation`
597			`//synthesis attribute max_fanout of wr_data_fall is 2`
598			`//synthesis attribute max_fanout of wr_data_rise is 2`
599			`always @(posedge clk0_tb) begin`
600			`if (rst0_tb) begin`
601			`wr_state <= WR_IDLE_FIRST_DATA;`
602			`end else begin`
603			`case (wr_state)`
604			`WR_IDLE_FIRST_DATA:`
605			`if (req_wd) begin`
606			`wr_state <= WR_SECOND_DATA;`
607			`end`
608			`WR_SECOND_DATA:`
609			`if (end_op) //begin`
610			`wr_state <= WR_IDLE_FIRST_DATA;`
611			`endcase`
612			`end`
613			`end`
614
615			`//get data from memory if`
616			`always @(*)`
617			`begin`
618			`wr_data_rise = {(APPDATA_WIDTH/2){1'bx}};`
619			`wr_data_fall = {(APPDATA_WIDTH/2){1'bx}};`
620			`case (wr_state)`
621			`WR_IDLE_FIRST_DATA:`
622			`begin`
623			`wr_data_rise = bus_if_wr_data0[(APPDATA_WIDTH/2)-1:0];`
624			`wr_data_fall = bus_if_wr_data0[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];`
625			`end`
626			`WR_SECOND_DATA:`
627			`begin`
628			`wr_data_rise = bus_if_wr_data1[(APPDATA_WIDTH/2)-1:0];`
629			`wr_data_fall = bus_if_wr_data1[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];`
630			`end`
631			`endcase`
632			`end`
633
634			`assign wr_cmd = ((state == WR_OP_D0) && !end_op)? 1'b1:1'b0;`
635			`assign rd_cmd = ((state == RD_OP) && !end_op)? 1'b1:1'b0;`
636
637
638			`endmodule`