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oana.bonca |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: UPT
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// Engineer: Oana Boncalo & Alexandru Amaricai
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//
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// Create Date: 09:51:04 03/18/2013
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// Design Name:
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// Module Name: DDR2_mem_wb_if
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module DDR2_mem_wb_if #
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(
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parameter APPDATA_WIDTH = 128 // # of usr read/write data bus bits.
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)
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(
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input clk,
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input rst,
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//wishbone if signals
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input cyc_wb,
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input stb_wb,
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input [30:0] address_wb,
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input [(APPDATA_WIDTH/8)-1:0] sel_wb, //write mask
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input [APPDATA_WIDTH-1:0] wr_data_wb, // write data
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input we_wb,
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input [2:0] cti_wb,
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input [1:0] bte_wb,
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//to wishbone from memory interface
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output reg ack_mem,
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output err_mem, rty_mem,
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output [APPDATA_WIDTH-1:0] rd_data_wb, // rd data
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//signals to/from memory user interface
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output reg[30:0] bus_if_addr,
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output reg [APPDATA_WIDTH-1:0] bus_if_wr_data0, bus_if_wr_data1,
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output reg [(APPDATA_WIDTH/8)-1:0] bus_if_wr_mask_data0, bus_if_wr_mask_data1,
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output reg mem_rd_cmd,
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output reg mem_wr_cmd,
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input rd_valid,
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input end_op,
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input [APPDATA_WIDTH-1:0] bus_if_rd_data,
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input app_wdf_afull,
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input app_af_afull,
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input phy_init_done,
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input rd_failed, //signals the abnormal termination of a RD op
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output [3:0] wb_state,
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output is_burst_flag_o
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);
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//for wishbone if state machine
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localparam WB_IDLE = 4'b0000;
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localparam WR_LATCH_D0 = 4'b0001;
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localparam WR_WAIT_D1 = 4'b0010;
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localparam WR_LATCH_D1 = 4'b0011;
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localparam WR_WAIT_END_OP = 4'b0100;
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localparam RD_REQ = 4'b0101;
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localparam RD_WAIT_RSP= 4'b0110;
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localparam RD_RSP = 4'b0111;
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localparam RD_WR_ERROR = 4'b1000;
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localparam WB_END_BURST = 4'b1001;
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reg [3:0] wb_state_reg;
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reg is_burst_flag;
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//rd/wr commands to memory
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wire rd_cmd;
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wire wr_cmd;
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wire [APPDATA_WIDTH-1:0] rd_data_to_latch;
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reg [APPDATA_WIDTH-1:0] rd_data_wb_reg;
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reg is_burst;
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reg [3:0] counter;
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//reg err_flag;
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assign rd_cmd = cyc_wb & stb_wb & (!we_wb);
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assign wr_cmd = cyc_wb & stb_wb & we_wb;
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assign rty_mem = (!phy_init_done) && ((wr_cmd && (app_af_afull || app_wdf_afull)) || (rd_cmd && app_af_afull))? 1'b1: 1'b0;
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assign wb_state = wb_state_reg;
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always @(posedge clk)
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begin
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if (rst)
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begin
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wb_state_reg <= WB_IDLE;
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mem_wr_cmd <= 1'b0;
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mem_rd_cmd <= 1'b0;
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//counter <= 0;
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end
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else
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case (wb_state_reg)
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WB_IDLE:
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begin
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mem_wr_cmd <= 1'b0;
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mem_rd_cmd <= 1'b0;
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if (wr_cmd && !rty_mem)
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wb_state_reg <= WR_LATCH_D0;
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if (rd_cmd && !rty_mem)
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wb_state_reg <= RD_REQ;
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end
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WR_LATCH_D0:
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begin
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//latch data0 & mask, address
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//generate ack
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wb_state_reg <= WR_WAIT_D1;
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//counter <= 15;
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end
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WR_WAIT_D1:
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begin
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if (cti_wb == 3'b000) //single write
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begin
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//no need for second data proceed with WR
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mem_wr_cmd <= 1'b1;
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wb_state_reg <= WR_WAIT_END_OP;
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end
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else
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begin
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if (wr_cmd)
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wb_state_reg <= WR_LATCH_D1;
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else if (counter == 0)
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wb_state_reg <= RD_WR_ERROR;
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end
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end
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WR_LATCH_D1:
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begin
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//latch data1 & mask and generate ack
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mem_wr_cmd <= 1'b1; // start write to mem
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wb_state_reg <= WR_WAIT_END_OP;
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end
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WR_WAIT_END_OP:
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begin
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//wait for memory to signal end of wr to fifos
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mem_wr_cmd <= 1'b0;
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if (end_op)
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wb_state_reg <= WB_IDLE;
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end
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RD_REQ:
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begin
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//latch address from mem
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mem_rd_cmd <= 1'b1;
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wb_state_reg <= RD_WAIT_RSP;
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end
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RD_WAIT_RSP:
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begin
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//check if rsp. available
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mem_rd_cmd <= 1'b0;
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if (rd_failed)
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begin
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wb_state_reg <= RD_WR_ERROR; //todo: revise if WB_IDLE is not more suitable
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end
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else
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begin
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if (rd_valid)
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wb_state_reg <= RD_RSP;
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end
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end
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RD_RSP:
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begin
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//based on (cti_wb == 3'b000) value - single read
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//deactivate ack /latch second data word for bus transfer
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wb_state_reg <= WB_IDLE;
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end
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RD_WR_ERROR:
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begin
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wb_state_reg <= WB_IDLE;
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end
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endcase
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end
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//latch address
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always @(posedge clk, posedge rst)
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begin
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if (rst == 1'b1)
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bus_if_addr <= 0;
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else
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if ((wb_state_reg == WR_LATCH_D0) || (wb_state_reg == RD_REQ))
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bus_if_addr <= address_wb;
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end
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//latch data0
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always @(posedge clk, posedge rst)
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begin
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if (rst == 1'b1)
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begin
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bus_if_wr_data0 <= 0;
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bus_if_wr_mask_data0 <= 0;
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end
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else
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if (wb_state_reg == WR_LATCH_D0)
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begin
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bus_if_wr_data0 <= wr_data_wb;
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bus_if_wr_mask_data0 <= sel_wb;
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end
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end
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//latch data1
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always @(posedge clk, posedge rst)
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begin
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if (rst == 1'b1)
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begin
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bus_if_wr_data1 <= 0;
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bus_if_wr_mask_data1 <= 0;
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end
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else
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case (wb_state_reg)
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WR_LATCH_D0:
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begin
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bus_if_wr_data1 <= 0;
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bus_if_wr_mask_data1 <= 0;
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end
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WR_LATCH_D1:
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begin
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bus_if_wr_data1 <= wr_data_wb;
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bus_if_wr_mask_data1 <= sel_wb;
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end
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endcase
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end
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//generate ack for write & rd
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//assign ack_mem = ((wb_state_reg == WR_WAIT_D1 && wr_cmd) || ((wb_state_reg == WR_WAIT_END_OP && wr_cmd) && (end_op == 1'b1)) || ((wb_state_reg == RD_WAIT_RSP) && rd_valid) || ((wb_state_reg == RD_RSP) && is_burst) )? 1'b1: 1'b0;
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//latch rd data
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always @(posedge clk, posedge rst)
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begin
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if (rst == 1'b1)
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begin
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rd_data_wb_reg <= 0;
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end
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else
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rd_data_wb_reg <= rd_data_to_latch;
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end
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//assign rd_data_to_latch = rd_valid && ((wb_state_reg == RD_WAIT_RSP) || ((wb_state_reg == RD_RSP) && is_burst_flag))? bus_if_rd_data: rd_data_wb_reg;
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assign rd_data_to_latch = (rd_valid && ack_mem)? bus_if_rd_data: rd_data_wb_reg;
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assign rd_data_wb = rd_data_to_latch;
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//assign rd_data_to_latch = rd_valid? bus_if_rd_data: rd_data_wb_reg;
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//single/burst op signaling
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assign is_burst_flag_o = is_burst_flag;
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always @(posedge clk, posedge rst)
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begin
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if (rst == 1'b1)
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begin
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is_burst_flag <= 0;
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end
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else
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is_burst_flag <= is_burst;
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end
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always @*
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begin
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is_burst = is_burst_flag;
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if ((wb_state_reg == WR_LATCH_D0) || (wb_state_reg == RD_REQ))
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if (cti_wb != 3'b000)
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is_burst = 1'b1;
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else
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is_burst = 1'b0;
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if (wb_state_reg == WB_IDLE)
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is_burst = 1'b0;
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end
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always @*
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begin
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ack_mem = 1'b0;
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if ((cyc_wb && stb_wb) &&((wb_state_reg == WR_WAIT_D1 && wr_cmd) || ((wb_state_reg == WR_WAIT_END_OP && wr_cmd)&& (end_op == 1'b1))))
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ack_mem = 1'b1;
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if ((cyc_wb && stb_wb) &&( ((wb_state_reg == RD_WAIT_RSP) && rd_valid) || ((wb_state_reg == RD_RSP) && is_burst) ))
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ack_mem = 1'b1;
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end
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//wishbone error signaling
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assign err_mem = (wb_state_reg == RD_WR_ERROR)? 1'b1: 1'b0;
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//assign is_burst = (cti_wb == 3'b010);
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//timeout counter for WR
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always @(posedge clk, posedge rst)
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begin
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if (rst == 1'b1)
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begin
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counter <= 0;
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end
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else
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if ((wb_state_reg == WR_LATCH_D0))
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counter <= 15;
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else
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if (wb_state_reg == WR_WAIT_D1)
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counter <= counter - 1'b1;
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end
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endmodule
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