1 |
2 |
oana.bonca |
`timescale 1ns / 1ps
|
2 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
3 |
|
|
// Company: UPT
|
4 |
|
|
// Engineer: Oana Boncalo & Alexandru Amaricai
|
5 |
|
|
//
|
6 |
|
|
// Create Date: 15:37:02 04/10/2013
|
7 |
|
|
// Design Name:
|
8 |
|
|
// Module Name: debounceRst
|
9 |
|
|
// Project Name:
|
10 |
|
|
// Target Devices:
|
11 |
|
|
// Tool versions:
|
12 |
|
|
// Description:
|
13 |
|
|
//
|
14 |
|
|
// Dependencies:
|
15 |
|
|
//
|
16 |
|
|
// Revision:
|
17 |
|
|
// Revision 0.01 - File Created
|
18 |
|
|
// Additional Comments:
|
19 |
|
|
//
|
20 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
21 |
|
|
module debounceRst(
|
22 |
|
|
input clk,
|
23 |
|
|
input noisyRst,
|
24 |
|
|
input PLLLocked,
|
25 |
|
|
output cleanPLLRst,
|
26 |
|
|
output cleanAsyncRst
|
27 |
|
|
);
|
28 |
|
|
|
29 |
|
|
localparam NR_SAMPLES = 10;
|
30 |
|
|
localparam DELAY_CC = 100;
|
31 |
|
|
localparam BITS_DELAY_CC = 8;// 8 = ceil(log2(DELAY_CC));
|
32 |
|
|
|
33 |
|
|
reg [NR_SAMPLES-1: 0] rst_samples;
|
34 |
|
|
wire rst_samples_and_N, rst_samples_and_N_1;
|
35 |
|
|
reg [DELAY_CC-1: 0] rst_debounce_delay_loop = {1'b0, {(DELAY_CC-1){1'b1}}};
|
36 |
|
|
reg [BITS_DELAY_CC-1: 0] rst_cnt_delay = 100 + 128;//100 + {1'b1, {(BITS_DELAY_CC-2){1'b0}}}; //keep reset active for DELAY_CC time
|
37 |
|
|
wire async_rst, PLLRst, rst_edge, start_up_rst;
|
38 |
|
|
|
39 |
|
|
|
40 |
3 |
oana.bonca |
// --4-bit Shift Register For resetting the PLL
|
41 |
2 |
oana.bonca |
//--Asserts Start_Up_Rst for 4 clock periods
|
42 |
|
|
|
43 |
|
|
SRL16E #(
|
44 |
|
|
.INIT(16'h000F) // Initial Value of Shift Register
|
45 |
|
|
) SRL16E_inst (
|
46 |
|
|
.Q(start_up_rst), // SRL data output
|
47 |
|
|
.A0 (1'b1), //-- Select[0] input
|
48 |
|
|
.A1 (1'b1), //-- Select[1] input
|
49 |
|
|
.A2 (1'b0), //-- Select[2] input
|
50 |
|
|
.A3 (1'b0), //-- Select[3] input
|
51 |
|
|
.CE (1'b1), // Clock enable input
|
52 |
|
|
.CLK(clk), // Clock input
|
53 |
|
|
.D(1'b0) // SRL data input
|
54 |
|
|
);
|
55 |
|
|
//debounce logic
|
56 |
|
|
always @(posedge clk)
|
57 |
|
|
begin
|
58 |
|
|
rst_samples <= {rst_samples [NR_SAMPLES-2: 0],noisyRst};
|
59 |
|
|
end
|
60 |
|
|
|
61 |
|
|
assign rst_samples_and_N = & rst_samples;
|
62 |
|
|
assign rst_samples_and_N_1 = & rst_samples[NR_SAMPLES-2:0];
|
63 |
|
|
//detect edge
|
64 |
|
|
assign rst_edge = (rst_samples_and_N_1 && (! rst_samples_and_N))? 1'b1: 1'b0;
|
65 |
|
|
|
66 |
|
|
//----------------------------------------------------------------------------------
|
67 |
|
|
//-- Reset with take-off and landing
|
68 |
3 |
oana.bonca |
//-- delay 95 cc = DELAY_CC - 4 reset
|
69 |
|
|
//-- then keep it active for 3 cc (as long as one of rst_debounce_delay_loop[DELAY_CC-2], rst_debounce_delay_loop[DELAY_CC-3] or rst_debounce_delay_loop[DELAY_CC-4] is 0)
|
70 |
2 |
oana.bonca |
//----------------------------------------------------------------------------------
|
71 |
|
|
always @(posedge clk)
|
72 |
|
|
begin
|
73 |
|
|
if (rst_edge || rst_debounce_delay_loop[DELAY_CC-1])
|
74 |
|
|
rst_debounce_delay_loop <= {rst_debounce_delay_loop[DELAY_CC-2:0],rst_debounce_delay_loop[DELAY_CC-1]};
|
75 |
|
|
end
|
76 |
|
|
|
77 |
|
|
assign PLLRst = ((~rst_debounce_delay_loop[DELAY_CC-2]) || (~rst_debounce_delay_loop[DELAY_CC-3]) ||
|
78 |
|
|
(~rst_debounce_delay_loop[DELAY_CC-4]) || start_up_rst)? 1'b1: 1'b0;
|
79 |
|
|
|
80 |
|
|
assign int_rst = ~PLLLocked;
|
81 |
|
|
|
82 |
3 |
oana.bonca |
//decrement counter for 100 cc then rst_cnt_delay[BITS_DELAY_CC-1] becomes 0
|
83 |
2 |
oana.bonca |
always @(posedge clk)
|
84 |
|
|
begin
|
85 |
|
|
if (int_rst)
|
86 |
3 |
oana.bonca |
rst_cnt_delay <= 228;//DELAY_CC + {1'b1, {(BITS_DELAY_CC-2){1'b0}}};
|
87 |
2 |
oana.bonca |
else
|
88 |
|
|
if (rst_cnt_delay[BITS_DELAY_CC-1])
|
89 |
|
|
rst_cnt_delay <= rst_cnt_delay - 1;
|
90 |
|
|
end
|
91 |
|
|
|
92 |
|
|
assign async_rst = rst_cnt_delay[BITS_DELAY_CC-1] | rst_debounce_delay_loop[DELAY_CC -1]; //--100 cc have passed since reset signal has been generated
|
93 |
|
|
|
94 |
|
|
assign cleanAsyncRst = async_rst;
|
95 |
|
|
assign cleanPLLRst = PLLRst;
|
96 |
|
|
|
97 |
|
|
|
98 |
|
|
endmodule
|