1 |
5 |
ahmed.shah |
############
|
2 |
|
|
# Overview #
|
3 |
|
|
############
|
4 |
|
|
This is an elementary generic structural VHDL code for FIR digital filters in transposed-form and direct-form implementations.
|
5 |
|
|
This project covers a wide spectrum of design aspects, in particular design and both functional and formal verification.
|
6 |
|
|
The project is developed in VHDL and modeled in SystemC. The SystemC model is used for functional and formal verification.
|
7 |
|
|
TCL scripts for GHDL and SystemC is included within the project files.
|
8 |
|
|
This code could be considered for VHDL classes or DSP classes for amateurs or beginners.
|
9 |
|
|
The developed code was synthesized for FPGA and ASIC (0.13um CMOS) using:
|
10 |
|
|
Xilinx ISE
|
11 |
|
|
Synopsys Design Compiler
|
12 |
|
|
Cadende RTL Encounter
|
13 |
|
|
|
14 |
|
|
Further, it was implemented using Xilinx Spartan-3E FPGA utilizing the Spartan-3E Starter Kit. It was tested using Xilinx ChipScope and a complete lab setup, as well. The filter output was converted to analog output using the on-board DAC to trace it on a Spectrum analyzer.
|
15 |
|
|
|
16 |
|
|
It should be noted that, the developed filters does not employ filter symmetry. However, the recent synthesizers consider symmetry automatically.
|
17 |
|
|
|
18 |
|
|
I should acknowledge Alan Fitch and Patrick Grogan for their constructive involvement in the SystemC model.
|
19 |
|
|
|
20 |
|
|
Enjoy!
|
21 |
|
|
Ahmed Shahein
|
22 |
|
|
ahmed.shahein@ieee.org
|
23 |
|
|
##############
|
24 |
|
|
# How to start? #
|
25 |
|
|
##############
|
26 |
|
|
after unzipping the zipped file you should have two main sub-directories, vhdl and sc. The VHDL codes are located at the vhdl sub-directory and the SystemC model is located in the sc sub-directory.
|
27 |
|
|
Execute the TCL script within each folder to see the output. There is a case study for transposed-form (TF) FIR filter with 18 tap and quantization bit-width of 12-bit. The filter is stimulated by a an impulse, therefore, the output is the filter response for a impulse input. I would recommend to change the format of the output signal (fir_out) to signed decimal then to analog-step, in order to have a more representative illustration for the output.
|
28 |
|
|
In order to build or generate your specific filter, the user has to modify the fir_pkg.vhd file only. The user has to change three constant parameters, coeff, quantization, and width_out. That's it and That's all. Further, you can change the stimulus file in the test-bench file (fir_filter_stage_tb.vhd) through modifying/replacing the data.txt file.
|
29 |
|
|
Regarding the SystemC model, the model initially illustrate a transposed-form FIR filter response for the same filter used in the VHDL implementation. The user has to modify 2 parameters within the firTF.h file, which are:
|
30 |
|
|
#define order 18 → integer represents the filter length (number of taps)
|
31 |
|
|
static const sc_int<12> fir_coeff[order] = {-51,25,128,77,-203,-372,70,1122,2047,2047,1122,70,-372,-203,77,128,25,-51}; → to the new filter coefficient set
|
32 |
|
|
Both VHDL implementation and SystemC model exports the final output into a text file. Which can be loaded to a signal processing software (Matlab or Octave) to plot the time and frequency domain analysis.
|
33 |
|
|
####################
|
34 |
|
|
# Folder Structure #
|
35 |
|
|
####################
|
36 |
|
|
./src/
|
37 |
|
|
adder_gen.vhd
|
38 |
|
|
Entity and architecture for adder element
|
39 |
|
|
delay_gen.vhd
|
40 |
|
|
Entity and architecture for delay element
|
41 |
|
|
multiplier_gen.vhd
|
42 |
|
|
Entity and architecture for multiplier element
|
43 |
|
|
fir_filter_stage.vhd
|
44 |
|
|
Design top-level
|
45 |
|
|
fir_pkg.vhd
|
46 |
|
|
Package for setting the filter coefficeints and quantization bit-width
|
47 |
|
|
THIS IS THE ONLY FILE THAT THE USER NEED TO CHANGE IT
|
48 |
|
|
tb_pack.vhd
|
49 |
|
|
Package for testbench
|
50 |
|
|
|
51 |
|
|
./testbench/
|
52 |
|
|
fir_filter_stage_tb.vhd
|
53 |
|
|
Testbench
|
54 |
|
|
data.txt
|
55 |
|
|
Stimuli bit-stream for filter input
|
56 |
|
|
|
57 |
|
|
./
|
58 |
|
|
ghdl.tcl
|
59 |
|
|
TCL script for GHDL
|
60 |
|
|
|
61 |
|
|
./simu/
|
62 |
|
|
Temporary folder used by GHDL
|
63 |
|
|
DON'T DELETE IT or RENAME IT
|
64 |
|
|
|
65 |
|
|
./help/
|
66 |
|
|
./html/
|
67 |
|
|
This folder contains a complete help for the VHDL codes.
|
68 |
|
|
The help could be run using the following command:
|
69 |
|
|
firefox help/html/index.html
|
70 |
|
|
./doc/
|
71 |
|
|
firTF.jpg
|
72 |
|
|
This is an analytical analysis for a transposed-form FIR with 3 taps
|
73 |
|
|
|
74 |
|
|
|
75 |
|
|
|