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1 4 ahmed.shah 
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<title>FIR Digital Filter: adder_gen Entity  Reference</title>
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<h1>adder_gen Entity Reference</h1>  </div>
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Inheritance diagram for adder_gen:</div>
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<p><a href="classadder__gen-members.html">List of all members.</a></p>
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<tr><td colspan="2"><h2><a name="nested-classes"></a>
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Architectures</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classadder__gen_1_1behave.html">behave</a>&#160;</td><td class="memItemRight" valign="bottom"><b>Architecture </b></td></tr>
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<br/>
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<br/>
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Libraries</h2></td></tr>
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<a class="el" href="classadder__gen.html#acbe0bfecfa56fa4103ea80a491bfdbc8">ieee</a>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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Packages</h2></td></tr>
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<a class="el" href="classadder__gen.html#a75f07bd8bde6f849270ce9de65573a4f">std_logic_1164</a>&#160;</td><td class="memItemRight" valign="bottom">  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88344fc897bb0e5e04f4c42e34595c87"></a><!-- doxytag: member="adder_gen::std_logic_signed" ref="a88344fc897bb0e5e04f4c42e34595c87" args="" -->
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<a class="el" href="classadder__gen.html#a88344fc897bb0e5e04f4c42e34595c87">std_logic_signed</a>&#160;</td><td class="memItemRight" valign="bottom">  </td></tr>
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<tr><td colspan="2"><h2><a name="pub-attribs"></a>
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Generics</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeeb50b5f733b5842672fbdd5b808e8d5"></a><!-- doxytag: member="adder_gen::add_width" ref="aeeb50b5f733b5842672fbdd5b808e8d5" args="" -->
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<a class="el" href="classadder__gen.html#aeeb50b5f733b5842672fbdd5b808e8d5">add_width</a>&#160;</td><td class="memItemRight" valign="bottom"><b> <b><span class="vhdlkeyword">natural</span><span class="vhdlchar"> </span></b></b></td></tr>
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<tr><td colspan="2"><h2><a name="pub-attribs"></a>
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Ports</h2></td></tr>
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<a class="el" href="classadder__gen.html#ac8dd8d308e841a9c0b3610064e1c2c63">add_a_in</a>&#160;</td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">add_width</span><span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Two input adder element first input port with variable input bit-width. <br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae06f8ada5cc8c9043c161103f152bac5"></a><!-- doxytag: member="adder_gen::add_b_in" ref="ae06f8ada5cc8c9043c161103f152bac5" args="std_logic_vector(add_width&#45;1 downto 0);" -->
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<a class="el" href="classadder__gen.html#ae06f8ada5cc8c9043c161103f152bac5">add_b_in</a>&#160;</td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">add_width</span><span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Two input adder element second input port with variable input bit-width. <br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a592d89406ba1ecefcf4800a2cc356915"></a><!-- doxytag: member="adder_gen::add_out" ref="a592d89406ba1ecefcf4800a2cc356915" args="std_logic_vector(add_width&#45;1 downto 0);" -->
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<a class="el" href="classadder__gen.html#a592d89406ba1ecefcf4800a2cc356915">add_out</a>&#160;</td><td class="memItemRight" valign="bottom"> <b>out</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">add_width</span><span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Two input adder element output port with variable input bit-width. <br/></td></tr>
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</table>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li>src/<a class="el" href="adder__gen_8vhd.html">adder_gen.vhd</a></li>
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