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1 4 ahmed.shah 
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<title>FIR Digital Filter: fir_filter_stage Entity  Reference</title>
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<h1>fir_filter_stage Entity Reference</h1><!-- doxytag: class="fir_filter_stage" --><!-- doxytag: inherits="fir_filter_stage::struct" --><div class="dynheader">
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Inheritance diagram for fir_filter_stage:</div>
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 <div class="center">
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  <img src="classfir__filter__stage.png" usemap="#fir_filter_stage_map" alt=""/>
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<area href="classfir__filter__stage_1_1struct.html" alt="struct" shape="rect" coords="103,112,196,136"/>
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<area href="classmultiplier__gen.html" alt="multiplier_gen" shape="rect" coords="0,56,93,80"/>
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<area href="classdelay__gen.html" alt="delay_gen" shape="rect" coords="103,56,196,80"/>
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<p><a href="classfir__filter__stage-members.html">List of all members.</a></p>
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<table border="0" cellpadding="0" cellspacing="0">
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<tr><td colspan="2"><h2>Architectures</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classfir__filter__stage_1_1struct.html">struct</a>&nbsp;</td><td class="memItemRight" valign="bottom"><b>Architecture </b></td></tr>
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<br/>
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<br/>
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<tr><td colspan="2"><h2>Libraries</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classfir__filter__stage.html#acbe0bfecfa56fa4103ea80a491bfdbc8">ieee</a>&nbsp;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2>Packages</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a75f07bd8bde6f849270ce9de65573a4f"></a><!-- doxytag: member="fir_filter_stage::std_logic_1164" ref="a75f07bd8bde6f849270ce9de65573a4f" args="" -->
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<a class="el" href="classfir__filter__stage.html#a75f07bd8bde6f849270ce9de65573a4f">std_logic_1164</a>&nbsp;</td><td class="memItemRight" valign="bottom">  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afa3f6e309d54fde7de3148deddb32c77"></a><!-- doxytag: member="fir_filter_stage::std_logic_arith" ref="afa3f6e309d54fde7de3148deddb32c77" args="" -->
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<a class="el" href="classfir__filter__stage.html#afa3f6e309d54fde7de3148deddb32c77">std_logic_arith</a>&nbsp;</td><td class="memItemRight" valign="bottom">  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5cb95d6cc481013a3f10b88926230077"></a><!-- doxytag: member="fir_filter_stage::std_logic_unsigned" ref="a5cb95d6cc481013a3f10b88926230077" args="" -->
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<a class="el" href="classfir__filter__stage.html#a5cb95d6cc481013a3f10b88926230077">std_logic_unsigned</a>&nbsp;</td><td class="memItemRight" valign="bottom">  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8fcee58e05e809c9790c3821c9735d3c"></a><!-- doxytag: member="fir_filter_stage::fir_pkg" ref="a8fcee58e05e809c9790c3821c9735d3c" args="" -->
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<a class="el" href="classfir__filter__stage.html#a8fcee58e05e809c9790c3821c9735d3c">fir_pkg</a>&nbsp;</td><td class="memItemRight" valign="bottom">   <b>Package</b><em><a class="el" href="classfir__pkg.html"> &lt;fir_pkg&gt;</a></td></tr>
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<tr><td colspan="2"><h2>Ports</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a89651e2933897b977b23c53fec93c9e0"></a><!-- doxytag: member="fir_filter_stage::fir_clk" ref="a89651e2933897b977b23c53fec93c9e0" args="std_logic;" -->
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<a class="el" href="classfir__filter__stage.html#a89651e2933897b977b23c53fec93c9e0">fir_clk</a>&nbsp;</td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Rising edge clock. <br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab88437b89f2e0b1588b987872e23698f"></a><!-- doxytag: member="fir_filter_stage::fir_clr" ref="ab88437b89f2e0b1588b987872e23698f" args="std_logic;" -->
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<a class="el" href="classfir__filter__stage.html#ab88437b89f2e0b1588b987872e23698f">fir_clr</a>&nbsp;</td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Active high asynchronous reset. <br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab508794e1ce35c2946d28703f4ebca9f"></a><!-- doxytag: member="fir_filter_stage::fir_in" ref="ab508794e1ce35c2946d28703f4ebca9f" args="std_logic_vector(0 downto 0);" -->
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<a class="el" href="classfir__filter__stage.html#ab508794e1ce35c2946d28703f4ebca9f">fir_in</a>&nbsp;</td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Unsigned single/multi-bit input. <br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae7fe87ee8521c3fce91172c78537df25"></a><!-- doxytag: member="fir_filter_stage::fir_out" ref="ae7fe87ee8521c3fce91172c78537df25" args="std_logic_vector(14 downto 0);" -->
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<a class="el" href="classfir__filter__stage.html#ae7fe87ee8521c3fce91172c78537df25">fir_out</a>&nbsp;</td><td class="memItemRight" valign="bottom"> <b>out</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdldigit">14</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Signed multi-bit output. <br/></td></tr>
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</table>
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<hr/><h2>Member Data Documentation</h2>
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<a class="anchor" id="acbe0bfecfa56fa4103ea80a491bfdbc8"></a><!-- doxytag: member="fir_filter_stage::ieee" ref="acbe0bfecfa56fa4103ea80a491bfdbc8" args="" -->
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<div class="memitem">
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<div class="memproto">
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      <table class="memname">
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        <tr>
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          <td class="memname"><a class="el" href="classfir__filter__stage.html#acbe0bfecfa56fa4103ea80a491bfdbc8">ieee</a> <b><span class="vhdlkeyword">library</span><span class="vhdlchar"> </span></b> <code> [Library]</code></td>
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        </tr>
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</div>
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<div class="memdoc">
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<div align="center">
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<img src="firTF.png" alt="firTF.png"/>
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<p><strong>Transposed-form FIR Filter Structure</strong></p></div>
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 <dl class="author"><dt><b>Author:</b></dt><dd>Ahmed Shahein  <a href="mailto:ahmed.shahein@ieee.org">ahmed.shahein@ieee.org</a> </dd></dl>
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<dl class="date"><dt><b>Date:</b></dt><dd>04.2012 </dd></dl>
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<p>Reimplemented from <a class="el" href="classadder__gen.html">adder_gen</a>.</p>
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</div>
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</div>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li>src/<a class="el" href="fir__filter__stage_8vhd.html">fir_filter_stage.vhd</a></li>
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</ul>
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<hr class="footer"/><address style="text-align: right;"><small>Generated on Mon Apr 9 16:26:40 2012 for FIR Digital Filter by&nbsp;
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