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[/] [gfir/] [trunk/] [vhdl/] [src/] [adder_gen.vhd] - Blame information for rev 4
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ahmed.shah |
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--! @file
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--! @brief This is a two input signed adder.
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---------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_signed.all;
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ENTITY adder_gen IS
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generic (add_width : natural);
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port (add_a_in : in std_logic_vector(add_width-1 downto 0); --! Two input adder element first input port with variable input bit-width
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add_b_in : in std_logic_vector(add_width-1 downto 0); --! Two input adder element second input port with variable input bit-width
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add_out : out std_logic_vector(add_width-1 downto 0));--! Two input adder element output port with variable input bit-width
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END ENTITY adder_gen;
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ARCHITECTURE behave OF adder_gen IS
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BEGIN
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add_out <= add_a_in + add_b_in;
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END ARCHITECTURE behave;
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