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ahmed.shah |
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--! @file
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--! @brief This is the top-level design for a transposed-form FIR digital filter. \n
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--! @details It instantiate the three major components for constructing a digital filter such as;\n
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--! adder (adder_gen), multiplier (multiplier_gen), and delay (delay_gen). \n
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--! The top-level is a structural description in a generic/scalable form. \n
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--! The filter coefficients and the quantization bit width should be edited/pasted \n
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--! into the fir_pkg.vhd. The filter coefficients should be given in integer format. \n
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--! Design specs: \n
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--! Unsigned single/multi-bit input (fir_in) \n
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--! Signed multi-bit output (fir_out) \n
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--! Active high asynchronous reset (fir_clr) \n
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--! Rising edge clock (fir_clk) \n
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--
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--! @image html firTF.png "Transposed-form FIR Filter Structure"
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--
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--! @author Ahmed Shahein
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--! @email ahmed.shahein@ieee.org
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--! @date 04.2012
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---------------------------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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USE work.fir_pkg.all;
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ENTITY fir_filter_stage_TF IS
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port (fir_clk : in std_logic; --! Rising edge clock
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fir_clr : in std_logic; --! Active high asynchronous reset
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fir_in : in std_logic_vector(0 downto 0); --! Unsigned single/multi-bit input
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fir_out : out std_logic_vector(14 downto 0)); --! Signed multi-bit output
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END ENTITY fir_filter_stage_TF;
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--
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ARCHITECTURE struct OF fir_filter_stage_TF IS
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-- COMPONENT DECLARATION
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component multiplier_gen
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generic (multi_width_const : natural;
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multi_width_in : natural);
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port (multiplier_const : in std_logic_vector(multi_width_const-1 downto 0);
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multiplier_in : in std_logic_vector(multi_width_in-1 downto 0);
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multiplier_out : out std_logic_vector((multi_width_const+multi_width_in)+1 downto 0));
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end component;
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component adder_gen
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generic (add_width : natural);
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port (add_a_in : in std_logic_vector(add_width-1 downto 0);
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add_b_in : in std_logic_vector(add_width-1 downto 0);
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add_out : out std_logic_vector(add_width-1 downto 0));
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end component;
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component delay_gen
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generic (delay_width : natural);
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port (clk, clr : in std_logic;
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delay_in : in std_logic_vector(delay_width-1 downto 0);
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delay_out : out std_logic_vector(delay_width-1 downto 0));
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end component;
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-- CONSTANT DECLARATION
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--constant coeff : int_vector := fir_coeff_thirdstage; --! Filter coefficients defined in the fir_pkg.vhd
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constant width_in : natural := fir_in'length; --! Input bit-width
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--constant width_out : natural := fir_out'length; --! Output bit-width
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constant width_const : positive := quantization; --! Quantization bit-width defined in the fir_pkg.vhd
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--constant order : natural := coeff'length; --! Filter length
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-- SIGNAL DECLARATION
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signal multi_add : std_logic_vector((order-1)*width_out-1 downto 0); --! Internal signal holding multiplier's outputs and adder's inputs
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signal add_delay : std_logic_vector((order-2)*width_out-1 downto 0); --! Internal signal holding adder's outputs and delay's inputs
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signal delay_add : std_logic_vector((order-1)*width_out-1 downto 0); --! Internal signal holding delay's output and adder's inputs
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signal multi_delay : std_logic_vector(width_out-1 downto 0); --! internal signal for the left most multiplier since it is connected directly to delay
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BEGIN
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COEFFMULTIs: for i in 0 to order-1 generate --! Generate the filter multipliers set
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LastMULT: if i = order-1 generate
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MULTI: multiplier_gen
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generic map(multi_width_const => width_const,
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multi_width_in => width_in)
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port map(multiplier_const => conv_std_logic_vector(coeff(i), width_const),
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multiplier_in => fir_in,
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multiplier_out => multi_delay);
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end generate;
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InterMULTs: if i < order-1 generate
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MULTIs: multiplier_gen
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generic map(multi_width_const => width_const,
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multi_width_in => width_in)
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port map(multiplier_const => conv_std_logic_vector(coeff(i), width_const),
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multiplier_in => fir_in,
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multiplier_out => multi_add((i+1)*width_out-1 downto i*width_out));
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end generate;
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end generate;
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COEFFDELAY: for i in 0 to order-2 generate --! Generate the filter delays set
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DELAY: if i = order-2 generate
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LastDELAY: delay_gen
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generic map(delay_width => width_out)
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port map(clk => fir_clk,
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clr => fir_clr,
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delay_in => multi_delay,
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delay_out => delay_add((i+1)*width_out-1 downto i*width_out));
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end generate;
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InterDElAYs: if i < order-2 generate
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DELAYs: delay_gen
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generic map(delay_width => width_out)
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port map(clk => fir_clk,
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clr => fir_clr,
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delay_in => add_delay((i+1)*width_out-1 downto i*width_out),
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delay_out => delay_add((i+1)*width_out-1 downto i*width_out));
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end generate;
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end generate;
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COEFFADD: for i in 0 to order-2 generate --! Generate the filter adders set
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FirstADDER: if i = 0 generate
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ADDER0: adder_gen
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generic map(add_width => width_out)
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port map(
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add_a_in => multi_add((i+1)*width_out-1 downto i*width_out),
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add_b_in => delay_add((i+1)*width_out-1 downto i*width_out),
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add_out => fir_out);
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end generate;
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InterADDER: if i > 0 generate
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ADDERs: adder_gen
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generic map(add_width => width_out)
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port map(
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add_a_in => multi_add((i+1)*width_out-1 downto i*width_out),
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add_b_in => delay_add((i+1)*width_out-1 downto i*width_out),
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add_out => add_delay(i*width_out-1 downto (i-1)*width_out));
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end generate;
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end generate;
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-- Internal debugging signals
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g_multi_add <= multi_add;
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g_add_delay <= add_delay;
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g_delay_add <= delay_add;
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g_multi_delay <= multi_delay;
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END ARCHITECTURE struct;
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