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boa_a_m |
--****************************************************************************************
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-- Company:
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-- Engineer: Mehran.HekmatPanah
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-- Create Date: 1393/01/18
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-- Module Name: Ethernet_1G
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-- Project Name: Ethernet_1G
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-- Version: v0.0
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-- Difference with Old Version:
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-- Target Devices: XC6VLX240t-1FF1156
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-- Code Status: Final
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-- Operation Clock: Input:125MHz,Output:125MHz
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-- In/Out Rate: 1Gbps/1Gbps
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-- Block RAM Usage:
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-- Slice Usage:
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-- Block Technical Info:
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-- Additional Comments:
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--****************************************************************************************
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity Ethernet_1g is
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generic (
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LAN_Lable : string:="LAN_0";
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IDELAY_GRP_Str : string:="Grp_KED";
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IDELAY_GRP_Str_s : string:="<Grp_KED_tx>";
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g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900"; --20S
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g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0):= x"07735940"; --1S
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g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0):= x"A"; --10
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g_GENERATE_PING_MODULE : boolean := true;
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g_GENERATE_ARP_MODULE : boolean := true;
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g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF"
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);
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port
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(
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i_clk_125 : in STD_LOGIC ;
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rx_mac_aclk : out STD_LOGIC ;
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gmii_rx_clk : in STD_LOGIC ;
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gmii_tx_clk : out STD_LOGIC ;
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i_global_reset : in STD_LOGIC ;
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i_vector_reset : in STD_LOGIC ;
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refclk : in std_logic;
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i_Reset_tx : in STD_LOGIC ;
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i_Reset_rx : in STD_LOGIC ;
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o_tx_clk_out : out STD_LOGIC ;
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o_rx_clk_out : out STD_LOGIC ;
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------------------------- UDP ----------------------------
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-- UDP & IP Tx header construction
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i_udp_tx_src_ip : in std_logic_vector (31 downto 0);
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i_udp_tx_dst_ip : in std_logic_vector (31 downto 0);
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i_udp_tx_data_len : in std_logic_vector (15 downto 0);
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i_udp_tx_protocol : in std_logic_vector (7 downto 0);
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i_udp_tx_src_mac : in std_logic_vector (47 downto 0);
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i_udp_tx_checksum : in std_logic_vector (15 downto 0);
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i_udp_tx_src_port : in std_logic_vector (15 downto 0);
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i_udp_tx_dst_port : in std_logic_vector (15 downto 0);
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i_ip_tx_fragmantation : in std_logic_vector(15 downto 0):=x"4000";
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i_fragment_len : in std_logic_vector(16 - 1 downto 0):=x"4000";
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-- UDP TX Inpus
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i_udp_tx_start : in std_logic;
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o_udp_tx_ready : out std_logic;
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o_mac_tx_tready : out std_logic;
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i_udp_tx_din : in std_logic_vector (7 downto 0);
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-- UDP RX Outputs
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o_udp_rx_dout : buffer std_logic_vector(7 downto 0);
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o_udp_rx_dout_rdy : buffer std_logic;
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o_udp_rx_dout_last : buffer std_logic;
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-- UDP RX Status Outputs
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o_udp_rx_src_ip : out std_logic_vector(31 downto 0);
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o_udp_rx_src_port : out std_logic_vector(15 downto 0);
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o_udp_rx_dst_port : out std_logic_vector(15 downto 0);
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o_udp_rx_data_len : out std_logic_vector(15 downto 0);
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o_udp_rx_err_out : out std_logic_vector(3 downto 0);
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o_udp_tx_err_out : out std_logic_vector(3 downto 0);
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o_arp_rx_err_out : out std_logic_vector(3 downto 0);
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o_ip_rx_fragmantation : out std_logic_vector(15 downto 0);
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o_arp_addr_valid : out std_logic;
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-- IP Status
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o_ip_rx_dst_ip : out std_logic_vector(31 downto 0);
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o_ip_rx_err_out : out std_logic_vector (3 downto 0);
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o_ip_tx_err_out : out std_logic_vector (3 downto 0);
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--------------------- PHY --------------------------------
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-- o_Rgmii_txc : out std_logic;
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-- o_Rgmii_tx_ctrl : out std_logic;
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-- o_Rgmii_txd : out std_logic_vector(4 downto 0);
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-- i_Rgmii_rxc : in std_logic;
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-- i_Rgmii_rx_ctrl : in std_logic;
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-- i_Rgmii_rxd : in std_logic_vector(4 downto 0);
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o_gmii_tx_en : out std_logic;
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o_gmii_tx_er : out std_logic;
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o_gmii_txd : out std_logic_vector(7 downto 0);
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i_gmii_rx_dv : in std_logic;
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i_gmii_rx_er : in std_logic;
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i_gmii_rxd : in std_logic_vector(7 downto 0);
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i_gmii_crs : in std_logic;
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i_gmii_col : in std_logic
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);
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end Ethernet_1g;
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architecture Behavioral of Ethernet_1g is
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COMPONENT tri_mode_ethernet_mac_0
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PORT (
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gtx_clk : IN STD_LOGIC;
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glbl_rstn : IN STD_LOGIC;
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rx_axi_rstn : IN STD_LOGIC;
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tx_axi_rstn : IN STD_LOGIC;
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rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
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rx_statistics_valid : OUT STD_LOGIC;
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rx_mac_aclk : OUT STD_LOGIC;
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rx_reset : OUT STD_LOGIC;
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rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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rx_axis_mac_tvalid : OUT STD_LOGIC;
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rx_axis_mac_tlast : OUT STD_LOGIC;
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rx_axis_mac_tuser : OUT STD_LOGIC;
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tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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tx_statistics_valid : OUT STD_LOGIC;
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tx_mac_aclk : OUT STD_LOGIC;
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tx_reset : OUT STD_LOGIC;
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tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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tx_axis_mac_tvalid : IN STD_LOGIC;
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tx_axis_mac_tlast : IN STD_LOGIC;
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tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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tx_axis_mac_tready : OUT STD_LOGIC;
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pause_req : IN STD_LOGIC;
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pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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speedis100 : OUT STD_LOGIC;
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speedis10100 : OUT STD_LOGIC;
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gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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gmii_tx_en : OUT STD_LOGIC;
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gmii_tx_er : OUT STD_LOGIC;
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gmii_tx_clk : OUT STD_LOGIC;
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gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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gmii_rx_dv : IN STD_LOGIC;
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gmii_rx_er : IN STD_LOGIC;
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gmii_rx_clk : IN STD_LOGIC;
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rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
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tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
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);
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END COMPONENT;
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--=========================================================================================
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signal s_reset_txn : std_logic;
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signal s_reset_rxn : std_logic;
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--================================ Ethernet 1g Signals =================================================
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signal s_tx_clk : std_logic;
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signal s_rx_clk : std_logic;
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signal s_rstn : std_logic;
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signal s_vecrstn : std_logic;
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--mac to gmii_if signals
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signal s_mac_gmii_rxd : std_logic_vector(7 downto 0);
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signal s_mac_gmii_rx_dv : std_logic;
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signal s_mac_gmii_rx_er : std_logic;
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0);
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signal s_mac_gmii_tx_en : std_logic;
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signal s_mac_gmii_tx_er : std_logic;
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--ip to mac signals
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signal s_mac_tx_tready : std_logic;
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signal s_mac_tx_tdata : std_logic_vector(7 downto 0);
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signal s_mac_tx_tvalid : std_logic;
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signal s_mac_tx_tlast : std_logic;
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0);
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signal s_mac_rx_tvalid : std_logic;
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signal s_mac_rx_tlast : std_logic;
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signal s_mac_gtx_clkout : std_logic;
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signal s_Rx_vector : std_logic_vector(80-1 downto 0);
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signal s_Tx_vector : std_logic_vector(80-1 downto 0);
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signal i_global_reset_r : std_logic;
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signal s_udp_rx_err_out : std_logic_vector (3 downto 0);
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signal s_udp_tx_err_out : std_logic_vector (3 downto 0);
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signal s_arp_rx_err_out : std_logic_vector (3 downto 0);
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--======================================================================================================
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constant tx_ifg_delay : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00";
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signal tx_reset : STD_LOGIC:='0';
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signal rx_reset : STD_LOGIC:='0';
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signal Reset_txn : STD_LOGIC:='0';
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signal rx_configuration_vector : std_logic_vector(79 downto 0):=(others => '0');
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signal tx_configuration_vector : std_logic_vector(79 downto 0):=(others => '0');
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signal pause_req : std_logic;
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signal pause_val : std_logic_vector(15 downto 0);
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begin
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o_mac_tx_tready <= s_mac_tx_tready;
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o_udp_rx_err_out <= s_udp_rx_err_out;
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o_udp_tx_err_out <= s_udp_tx_err_out;
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o_arp_rx_err_out <= s_arp_rx_err_out;
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--========================= Clk & Reset ===================================================
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s_rstn <= not(i_global_reset);
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s_reset_txn <= not(i_reset_tx);
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s_reset_rxn <= not(i_reset_rx);
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o_tx_clk_out <= s_tx_clk;
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o_rx_clk_out <= s_rx_clk;
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--=========================================================================================
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process(i_clk_125)
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begin
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if(rising_edge(i_clk_125)) then
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i_global_reset_r <= i_global_reset;
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pause_req <= '0';
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pause_val <= (others => '0');
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end if;
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end process;
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--=============================== UDP ====================================================
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--inst_UDP:UDP_NGC
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inst_UDP:entity work.UDP_KED
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generic map(
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g_TIME_OUT_LOOKUP_TABLE_ARP => g_TIME_OUT_LOOKUP_TABLE_ARP,
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g_TIME_OUT_WAIT_FOR_ARP_REPLY => g_TIME_OUT_WAIT_FOR_ARP_REPLY,
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g_RE_SEND_ARP_REQUEST => g_RE_SEND_ARP_REQUEST,
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g_GENERATE_PING_MODULE => g_GENERATE_PING_MODULE,
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g_GENERATE_ARP_MODULE => g_GENERATE_ARP_MODULE,
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g_DEFAULT_DST_MAC_ADDR => g_DEFAULT_DST_MAC_ADDR
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)
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port map
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(
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i_ip_tx_fragmantation => i_ip_tx_fragmantation,
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i_fragment_len => i_fragment_len,
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o_ip_rx_fragmantation => o_ip_rx_fragmantation,
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i_rx_clk => s_rx_clk,
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i_tx_clk => i_clk_125, --125MHz
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i_reset_tx => tx_reset,-- i_Reset_tx,--
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i_reset_rx => rx_reset,-- i_Reset_rx,--
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--******************************* IP ***************************************
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-- IP to MAC TX Outputs
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i_mac_tx_tready => s_mac_tx_tready,
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o_mac_tx_tdata => s_mac_tx_tdata,
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o_mac_tx_tvalid => s_mac_tx_tvalid,
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o_mac_tx_tlast => s_mac_tx_tlast,
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-- MAC to IP RX Inputs
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i_mac_rx_tdata => s_mac_rx_tdata,
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i_mac_rx_tvalid => s_mac_rx_tvalid,
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i_mac_rx_tlast => s_mac_rx_tlast,
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--IP Status
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o_ip_rx_dst_ip => o_ip_rx_dst_ip,
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o_ip_rx_err_out => o_ip_rx_err_out,
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o_ip_tx_err_out => o_ip_tx_err_out,
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o_arp_rx_err_out => s_arp_rx_err_out,
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--************************** UDP*********************************************
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-- UDP & IP Tx header construction
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i_udp_tx_src_ip => i_udp_tx_src_ip,
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i_udp_tx_dst_ip => i_udp_tx_dst_ip,
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i_udp_tx_data_len => i_udp_tx_data_len,
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i_udp_tx_protocol => i_udp_tx_protocol ,
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i_udp_tx_src_mac => i_udp_tx_src_mac,
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i_udp_tx_checksum => i_udp_tx_checksum,
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i_udp_tx_src_port => i_udp_tx_src_port,
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i_udp_tx_dst_port => i_udp_tx_dst_port,
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-- UDP TX Inpus
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i_udp_tx_start => i_udp_tx_start,
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o_udp_tx_ready => o_udp_tx_ready,
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311 |
|
|
i_udp_tx_din => i_udp_tx_din,
|
312 |
|
|
|
313 |
|
|
-- UDP RX Outputs
|
314 |
|
|
o_udp_rx_dout => o_udp_rx_dout,
|
315 |
|
|
o_udp_rx_dout_rdy => o_udp_rx_dout_rdy,
|
316 |
|
|
o_udp_rx_dout_last => o_udp_rx_dout_last,
|
317 |
|
|
|
318 |
|
|
-- UDP RX Status Outputs
|
319 |
|
|
o_udp_rx_src_ip => o_udp_rx_src_ip,
|
320 |
|
|
o_udp_rx_src_port => o_udp_rx_src_port,
|
321 |
|
|
o_udp_rx_dst_port => o_udp_rx_dst_port,
|
322 |
|
|
o_udp_rx_data_len => o_udp_rx_data_len ,
|
323 |
|
|
|
324 |
|
|
o_arp_addr_valid => o_arp_addr_valid,
|
325 |
|
|
|
326 |
|
|
o_udp_rx_err_out => s_udp_rx_err_out,
|
327 |
|
|
o_udp_tx_err_out => s_udp_tx_err_out
|
328 |
|
|
|
329 |
|
|
);
|
330 |
|
|
--=========================================================================================
|
331 |
|
|
|
332 |
|
|
--LAN0_MAC: Entity Work.MAC_Controller
|
333 |
|
|
--GENERIC MAP(
|
334 |
|
|
-- PHY_ADDR => "00100", -- PHY_AD0/1 pulled-down by 1KOhm, PHY_AD2 pulled-up in .ucf file.
|
335 |
|
|
-- CLK_FREQUENCY => 125
|
336 |
|
|
--)
|
337 |
|
|
--PORT MAP(
|
338 |
|
|
-- CLK => i_clk_125,
|
339 |
|
|
-- IDELAYREFCLK200MHZ => refclk,
|
340 |
|
|
-- ASYNC_RESET => i_Reset_tx,
|
341 |
|
|
-- MAC_ADDR => x"0123456789ab",
|
342 |
|
|
-- MAC_TX_CONFIG => X"0003", -- MAC must must provide pad + crc32
|
343 |
|
|
-- MAC_RX_CONFIG => x"000F", -- promiscuous mode, strip crc32, accept broadcast/multicast
|
344 |
|
|
-- PHY_CONFIG_CHANGE => '1',--CONFIG_CHANGE_PULSE,
|
345 |
|
|
-- PHY_RESET => '0',
|
346 |
|
|
-- SPEED => "10", -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
|
347 |
|
|
-- DUPLEX => '1', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
|
348 |
|
|
-- TEST_MODE => "00", -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
|
349 |
|
|
-- POWER_DOWN => '0', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
|
350 |
|
|
-- MAC_TX_DATA => s_mac_tx_tdata,
|
351 |
|
|
-- MAC_TX_DATA_VALID => s_mac_tx_tvalid,
|
352 |
|
|
-- MAC_TX_EOF => s_mac_tx_tlast,
|
353 |
|
|
-- MAC_TX_CTS => s_mac_tx_tready,
|
354 |
|
|
-- MAC_RX_DATA => s_mac_rx_tdata,
|
355 |
|
|
-- MAC_RX_DATA_VALID => s_mac_rx_tvalid,
|
356 |
|
|
-- MAC_RX_SOF => open,--s_mac_rx_SOF,
|
357 |
|
|
-- MAC_RX_EOF => s_mac_rx_tlast,
|
358 |
|
|
-- MAC_RX_CTS => '1', -- follow-on processing is expected to always accept data even at max speed.
|
359 |
|
|
-- RESET_N => OPEN,--o_LAN1G_RESETn1,
|
360 |
|
|
-- GMII_MII_TXD => o_gmii_txd,
|
361 |
|
|
-- GMII_MII_TX_EN => o_gmii_tx_en,
|
362 |
|
|
-- GMII_MII_TX_ER => o_gmii_tx_er,
|
363 |
|
|
-- GMII_MII_RX_CLK => i_clk_125,
|
364 |
|
|
-- GMII_MII_RXD => i_gmii_rxd,
|
365 |
|
|
-- GMII_MII_RX_DV => i_gmii_rx_dv,
|
366 |
|
|
-- GMII_MII_RX_ER => i_gmii_rx_er, -- end of MII interface ------
|
367 |
|
|
|
368 |
|
|
-- PHY_ID => open
|
369 |
|
|
--);
|
370 |
|
|
Reset_txn <= not i_Reset_tx;
|
371 |
|
|
|
372 |
|
|
LAN0_MAC : tri_mode_ethernet_mac_0
|
373 |
|
|
PORT MAP (
|
374 |
|
|
gtx_clk => i_clk_125,
|
375 |
|
|
glbl_rstn => Reset_txn,
|
376 |
|
|
rx_axi_rstn => '1',
|
377 |
|
|
tx_axi_rstn => '1',
|
378 |
|
|
rx_statistics_vector => open,
|
379 |
|
|
rx_statistics_valid => open,
|
380 |
|
|
rx_mac_aclk => rx_mac_aclk,--??
|
381 |
|
|
rx_reset => rx_reset,
|
382 |
|
|
rx_axis_mac_tdata => s_mac_rx_tdata,
|
383 |
|
|
rx_axis_mac_tvalid => s_mac_rx_tvalid,
|
384 |
|
|
rx_axis_mac_tlast => s_mac_rx_tlast,
|
385 |
|
|
rx_axis_mac_tuser => open,
|
386 |
|
|
tx_ifg_delay => tx_ifg_delay,
|
387 |
|
|
tx_statistics_vector => open,
|
388 |
|
|
tx_statistics_valid => open,
|
389 |
|
|
tx_mac_aclk => open,--??
|
390 |
|
|
tx_reset => tx_reset,
|
391 |
|
|
tx_axis_mac_tdata => s_mac_tx_tdata,
|
392 |
|
|
tx_axis_mac_tvalid => s_mac_tx_tvalid,
|
393 |
|
|
tx_axis_mac_tlast => s_mac_tx_tlast,
|
394 |
|
|
tx_axis_mac_tuser => "0",
|
395 |
|
|
tx_axis_mac_tready => s_mac_tx_tready,
|
396 |
|
|
pause_req => pause_req,
|
397 |
|
|
pause_val => pause_val,
|
398 |
|
|
speedis100 => open,
|
399 |
|
|
speedis10100 => open,
|
400 |
|
|
gmii_txd => o_gmii_txd,
|
401 |
|
|
gmii_tx_en => o_gmii_tx_en,
|
402 |
|
|
gmii_tx_er => o_gmii_tx_er,
|
403 |
|
|
gmii_tx_clk => gmii_tx_clk,--??
|
404 |
|
|
gmii_rxd => i_gmii_rxd,
|
405 |
|
|
gmii_rx_dv => i_gmii_rx_dv,
|
406 |
|
|
gmii_rx_er => i_gmii_rx_er,
|
407 |
|
|
gmii_rx_clk => gmii_rx_clk,
|
408 |
|
|
rx_configuration_vector => rx_configuration_vector,
|
409 |
|
|
tx_configuration_vector => tx_configuration_vector
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
rx_configuration_vector(13 downto 12) <= "10";--1G
|
414 |
|
|
rx_configuration_vector(1) <= '1';--Enable
|
415 |
|
|
|
416 |
|
|
tx_configuration_vector(13 downto 12) <= "10";--1G
|
417 |
|
|
tx_configuration_vector(1) <= '1';--Enable
|
418 |
|
|
-- -- ////////////////////////////
|
419 |
|
|
|
420 |
|
|
-- inst_MAC_RGMII: entity work.tri_mode_ethernet_mac_1_example_design
|
421 |
|
|
-- generic map( IDELAY_GRP_Str => IDELAY_GRP_Str )
|
422 |
|
|
-- port map (
|
423 |
|
|
-- -- asynchronous reset
|
424 |
|
|
-- ----------------------------
|
425 |
|
|
-- glbl_rst => '0',--i_global_reset_r,
|
426 |
|
|
|
427 |
|
|
-- -- 200MHz clock input from board
|
428 |
|
|
-- refclk_bufg => refclk,
|
429 |
|
|
-- -- 125 MHz clock
|
430 |
|
|
-- gtx_clk_bufg => i_clk_125,
|
431 |
|
|
|
432 |
|
|
-- phy_resetn => open,
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
-- -- RGMII Interface
|
436 |
|
|
-- ----------------------------
|
437 |
|
|
-- rgmii_txd => o_Rgmii_txd,
|
438 |
|
|
-- rgmii_tx_ctl => o_Rgmii_tx_ctrl,
|
439 |
|
|
-- rgmii_txc => o_Rgmii_txc,
|
440 |
|
|
-- rgmii_rxd => i_Rgmii_rxd,
|
441 |
|
|
-- rgmii_rx_ctl => i_Rgmii_rx_ctrl,
|
442 |
|
|
-- rgmii_rxc => i_Rgmii_rxc,
|
443 |
|
|
|
444 |
|
|
|
445 |
|
|
-- --------------------------------------
|
446 |
|
|
-- rx_axis_tdata => s_mac_rx_tdata ,
|
447 |
|
|
-- rx_axis_tvalid => s_mac_rx_tvalid ,
|
448 |
|
|
-- rx_axis_tlast => s_mac_rx_tlast ,
|
449 |
|
|
-- rx_axis_tready => '1',--s_mac_rx_tready ,
|
450 |
|
|
|
451 |
|
|
-- tx_axis_tdata => s_mac_tx_tdata ,
|
452 |
|
|
-- tx_axis_tvalid => s_mac_tx_tvalid ,
|
453 |
|
|
-- tx_axis_tlast => s_mac_tx_tlast ,
|
454 |
|
|
-- tx_axis_tready => s_mac_tx_tready ,
|
455 |
|
|
-- --------------------------------------
|
456 |
|
|
|
457 |
|
|
-- -- Serialised statistics vectors
|
458 |
|
|
-- ----------------------------
|
459 |
|
|
-- tx_statistics_s => open,
|
460 |
|
|
-- rx_statistics_s => open,
|
461 |
|
|
|
462 |
|
|
-- -- Serialised Pause interface controls
|
463 |
|
|
-- ----------------------------------
|
464 |
|
|
-- pause_req_s => '0',
|
465 |
|
|
|
466 |
|
|
-- -- Main example design controls
|
467 |
|
|
-- ---------------------------
|
468 |
|
|
-- mac_speed => "10",
|
469 |
|
|
-- update_speed => '0',
|
470 |
|
|
-- config_board => '0',
|
471 |
|
|
-- serial_response => open,
|
472 |
|
|
-- gen_tx_data => '0',
|
473 |
|
|
-- chk_tx_data => '0',
|
474 |
|
|
-- reset_error => '0',
|
475 |
|
|
-- frame_error => open,
|
476 |
|
|
-- frame_errorn => open,
|
477 |
|
|
-- activity_flash => open,
|
478 |
|
|
-- activity_flashn => open
|
479 |
|
|
-- );
|
480 |
|
|
-- -- ////////////////////////////
|
481 |
|
|
|
482 |
|
|
|
483 |
|
|
s_tx_clk <= i_clk_125;
|
484 |
|
|
s_rx_clk <= i_clk_125;
|
485 |
|
|
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
-- my_ila_Phy : entity work.ila_0
|
489 |
|
|
-- PORT MAP (
|
490 |
|
|
-- clk => i_clk_125,
|
491 |
|
|
|
492 |
|
|
-- probe0(3 downto 0) => "0000",--i_gmii_rxd,
|
493 |
|
|
-- probe0(4) => i_gmii_rx_dv,--i_gmii_rx_ctrl,
|
494 |
|
|
-- probe0(5) => i_gmii_rx_er,--i_gmii_rxc,
|
495 |
|
|
-- probe0(13 downto 6) => s_mac_rx_tdata ,
|
496 |
|
|
-- probe0(14) => s_mac_rx_tvalid ,
|
497 |
|
|
-- probe0(15) => s_mac_rx_tlast ,
|
498 |
|
|
-- probe0(23 downto 16) => s_mac_tx_tdata ,
|
499 |
|
|
-- probe0(24) => s_mac_tx_tvalid ,
|
500 |
|
|
-- probe0(25) => s_mac_tx_tlast ,
|
501 |
|
|
-- probe0(26) => s_mac_tx_tready ,
|
502 |
|
|
-- probe0(30 downto 27) => s_udp_rx_err_out ,
|
503 |
|
|
-- probe0(34 downto 31) => s_udp_tx_err_out ,
|
504 |
|
|
-- probe0(38 downto 35) => s_arp_rx_err_out ,
|
505 |
|
|
-- probe0(39) => i_global_reset ,
|
506 |
|
|
-- probe0(40) => tx_reset ,
|
507 |
|
|
-- probe0(41) => rx_reset ,
|
508 |
|
|
|
509 |
|
|
-- probe0(49 downto 42) => i_gmii_rxd,
|
510 |
|
|
-- probe0(57 downto 50) => o_udp_rx_dout,
|
511 |
|
|
-- probe0(58) => o_udp_rx_dout_rdy,
|
512 |
|
|
-- probe0(59) => o_udp_rx_dout_last,
|
513 |
|
|
|
514 |
|
|
-- probe0(255 downto 60) => (others => '0')
|
515 |
|
|
-- );
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
|
519 |
|
|
----////////////////////////
|
520 |
|
|
|
521 |
|
|
|
522 |
|
|
|
523 |
|
|
end Behavioral;
|
524 |
|
|
|