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boa_a_m |
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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entity ping_pong_fifo2_KED is
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generic (
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g_PACKET_LENGTH : std_logic_vector(15 downto 0):= x"05c0"; --1472(maximum UDP Packet Length)
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g_use_fragment : boolean:= false
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);
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port
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(
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i_clk : in std_logic; --Tx_Clk (125MHz)
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i_rst : in std_logic;
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i_din : in std_logic_vector(8-1 downto 0);
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i_din_valid : in std_logic:='0';
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i_din_last : in std_logic:='0';
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--Read Clock
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o_dout_len : out std_logic_vector(15 downto 0):=(others=>'0');
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o_start_out : out std_logic:='0'; --Start Pulse for Ethernet 1g Block
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i_rd_en : in std_logic;
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o_dout : out std_logic_vector(8-1 downto 0):=(others=>'0');
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o_fragment : out std_logic_vector(16-1 downto 0):=x"4000";
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fifo_ready : out std_logic;
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full : out std_logic;
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o_wr_cnta : out std_logic_vector(15 downto 0):=(others=>'0');
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o_wr_cntb : out std_logic_vector(15 downto 0):=(others=>'0')
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);
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end ping_pong_fifo2_KED;
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architecture Behavioral of ping_pong_fifo2_KED is
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--==============================================================================================
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COMPONENT data_fifo_KED
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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valid : OUT STD_LOGIC;
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data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
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prog_full : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT Arr_fifo_KED
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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valid : OUT STD_LOGIC
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);
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END COMPONENT;
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--========================== Signals ===========================================================
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--Data fifo Signals
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signal s_dina :std_logic_vector(8-1 downto 0):=(others=>'0');
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signal s_dinb :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal s_douta :std_logic_vector(8-1 downto 0);
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signal s_doutb :std_logic_vector(16-1 downto 0);
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signal s_wr_en_a :std_logic:='0';
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signal s_wr_en_b :std_logic:='0';
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signal s_rd_ena :std_logic:='0';
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signal s_rd_enb :std_logic:='0';
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signal s_rst_a :std_logic:='1';
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signal s_rst_b :std_logic:='1';
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signal s_empty_a :std_logic;
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signal s_empty_b :std_logic;
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--Control Signals
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signal s_line_busy_for_a :std_logic:='1';
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signal s_line_busy_for_b :std_logic:='1';
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signal s_wr_cnta :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal s_wr_cnta_r1 :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal s_wr_cnta_r2 :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal s_wr_cnta_r3 :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal s_wr_cntb :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal s_wd_cnt :std_logic_vector(16-1 downto 0):=(others=>'0'); --Watch Dog Timer
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signal s_req_cnt :std_logic_vector(5-1 downto 0):=(others=>'0'); --Watch Dog Timer
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signal s_start_out :std_logic:='0';
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signal delay_cnt :std_logic_vector(8-1 downto 0):=(others=>'0');
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signal s_prog_full_a :std_logic;
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signal s_prog_full_b :std_logic;
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signal s_full_a :std_logic;
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signal s_full_b :std_logic;
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--type t_state is (reset , idle , wr_in_a_rd_of_b , wait_4_free_line_from_b , wr_in_b_rd_of_a , wait_4_free_line_from_a);
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--signal st_state : t_state:=reset;
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signal reset : std_logic:='1';
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signal idle : std_logic:='0';
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signal wr_in_a_rd_of_b : std_logic:='0';
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signal wait_4_free_line_from_b : std_logic:='0';
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signal wr_in_b_rd_of_a : std_logic:='0';
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signal wait_4_free_line_from_a : std_logic:='0';
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signal s_dout_len : std_logic_vector(15 downto 0):=(others=>'0');
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signal LED_state : std_logic_vector(7 downto 0):=(others=>'1');
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signal s_fifo_valida : std_logic:='0';
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signal s_fifo_validb : std_logic:='0';
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signal prog_full1 : std_logic:='0';
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signal prog_full2 : std_logic:='0';
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signal s_mac_ready : std_logic:='0';
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type General_State is (St_init,St_idle,St_0,St_1,St_1_2,St_2,St_3,St_4,St_5,St_6,St_7);
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signal St_ctrl: General_State:=St_idle;
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constant FrRSVD : std_logic:='0';
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signal dntFragSet : std_logic:='0';
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signal MoreFrag: std_logic:='0';
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signal s_wd_cnt_rst: std_logic:='0';
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signal offset_fragment : std_logic_vector(12 downto 0):=(others=>'0');
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signal s_udp_header_len : std_logic_vector(3 downto 0):=x"1";
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signal s_fragment : std_logic_vector(16-1 downto 0):=x"4000";
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signal rdySetLast : std_logic:='0';
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signal s_wr_en_b_r0 : std_logic:='0';
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signal s_wr_en_b_r1 : std_logic:='0';
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signal s_dinb_r0 :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal remain_len :std_logic_vector(16-1 downto 0):=(others=>'0');
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signal data_fifo_cnt :std_logic_vector(10 downto 0):=(others=>'0');
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signal LastPacket : std_logic:='0';
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signal cntr_frag :std_logic_vector(7 downto 0):=(others=>'0');
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signal Num_frag :std_logic_vector(7 downto 0):=(others=>'0');
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signal Num_frag_rst : std_logic:='0';
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signal remainPacket : std_logic:='0';
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signal readyFornext : std_logic:='1';
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signal cntr_wait :std_logic_vector(7 downto 0):=(others=>'0');
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begin
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o_dout_len <= s_dout_len;
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o_start_out <= s_start_out;
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o_fragment <= s_fragment When g_use_fragment else x"4000";
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s_mac_ready <= i_rd_en;
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s_rd_ena <= s_mac_ready;
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o_dout <= s_douta;
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--================= Process for Continues Writing and Discontinues Reading Data =================
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process(i_clk)
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begin
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if rising_edge(i_clk) then
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s_rst_a <= i_rst;
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fifo_ready <= not(prog_full1);-- and readyFornext;
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s_dina <= i_din;
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s_wr_en_a <= i_din_valid;
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-- s_wr_cnta_r1 <= s_wr_cnta;
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-- s_wr_cnta_r2 <= s_wr_cnta_r1;
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-- s_wr_en_b_r0 <= i_din_last;
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-- s_wr_en_b_r1 <= s_wr_en_b_r0;
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---- s_wr_cnta_r3 <= s_wr_cnta_r2;
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---- if (s_wr_cnta>=g_PACKET_LENGTH-1) then
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---- s_dinb <= s_wr_cntb - g_PACKET_LENGTH + 1;
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---- else
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-- s_dinb <= s_wr_cntb + 1;
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---- end if;
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s_dinb <= s_wr_cntb + 1;
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s_wr_en_b <= i_din_last;
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-- s_dinb <= "00000" & data_fifo_cnt;
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-- s_wr_en_b <= s_wr_en_b_r1;
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-- if (s_wr_cnta < (g_PACKET_LENGTH & '0' )-1 and rdySetLast = '1') then
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-- s_dinb <= s_dinb_r0;
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-- s_wr_en_b <= s_wr_en_b_r0;
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-- s_wr_en_b_r0 <= '0';
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-- rdySetLast <= '0';
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-- else
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-- s_wr_en_b <= '0';
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-- end if;
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-- if (i_din_last = '1') then
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-- s_dinb_r0 <= s_wr_cntb + 1;
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-- s_wr_en_b_r0 <= '1';
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-- rdySetLast <= '1';
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-- end if;
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if (s_rst_a = '1') then
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s_wr_cnta <= (others => '0');
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s_wr_cntb <= (others => '0');
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s_wd_cnt <= (others => '0');
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Num_frag <= (others => '0');
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Cntr_frag <= (others => '0');
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remainPacket<= '0';
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readyFornext<= '1';
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dntFragSet <= '1';
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MoreFrag <= '0';
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offset_fragment <= (others => '0');
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s_fragment <= x"4000";
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s_udp_header_len <= x"1";
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St_ctrl <= st_idle;
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-- elsif (i_din_valid = '1') then
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-- if (s_wd_cnt_rst = '1') then
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-- s_wr_cnta <= s_wr_cnta - s_dout_len +1;
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-- else
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-- s_wr_cnta <= s_wr_cnta + 1;
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-- end if;
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-- elsif (s_wd_cnt_rst = '1') then
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-- s_wr_cnta <= s_wr_cnta - s_dout_len;
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end if;
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if (i_din_last = '1') then
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s_wr_cntb <= (others => '0');
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readyFornext<= '0';
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-- if (data_fifo_cnt >= g_PACKET_LENGTH-1 ) then
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-- remainPacket <= '1';
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-- end if;
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else
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if (i_din_valid = '1') then
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if (s_wr_cntb >= g_PACKET_LENGTH-1) then
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s_wr_cntb <= s_wr_cntb - g_PACKET_LENGTH + 1;
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-- Num_frag <= Num_frag+ 1;
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else
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s_wr_cntb <= s_wr_cntb + 1;
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end if;
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end if;
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end if;
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if (s_wd_cnt_rst = '1') then
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s_wd_cnt <= (others => '0');
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elsif (s_mac_ready = '1') then
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s_wd_cnt <= s_wd_cnt + 1;
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end if;
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-- if (Num_frag_rst = '1') then
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-- Num_frag <= (others => '0');
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-- end if;
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-- if (readyFornext = '0') then
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-- cntr_wait <= cntr_wait + 1;
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-- else
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-- cntr_wait <= (others => '0');
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-- end if;
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-- if (cntr_wait = 100) then
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-- readyFornext<= '1';
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-- end if;
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if (s_wd_cnt = s_dout_len -1) then
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s_wd_cnt_rst <= '1';
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end if;
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-- Num_frag_rst <= '0';
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case St_ctrl is
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When st_idle =>
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LED_state <= x"FF";
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s_start_out <= '0';
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s_wd_cnt_rst <= '0';
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-- if (remainPacket = '1') then
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-- St_ctrl <= st_0;
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-- remainPacket<= '0';
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-- els
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if (s_empty_b = '0') then
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s_rd_enb <= '1';
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St_ctrl <= st_1;
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-- elsif (Cntr_frag < Num_frag) then
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-- elsif (s_wr_cnta_r2 >= g_PACKET_LENGTH-1) then
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elsif (data_fifo_cnt >= g_PACKET_LENGTH-1) then
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St_ctrl <= st_0;
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end if;
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When st_0 => -- Befor LastPack
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LED_state <= x"00";
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s_start_out <= '1';
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s_udp_header_len<= x"0";
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s_fragment <= "001" & offset_fragment;--FrRSVD & dntFragSet & MoreFrag & offset_fragment
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offset_fragment <= offset_fragment + g_PACKET_LENGTH(15 downto 3)+s_udp_header_len;
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s_dout_len <= g_PACKET_LENGTH;
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Cntr_frag <= Cntr_frag + 1;
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St_ctrl <= st_2;
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When st_1 =>
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LED_state <= x"01";
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s_rd_enb <= '0';
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Cntr_frag <= (others => '0');
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-- Num_frag_rst <= '1';
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if (s_fifo_validb = '1') then
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|
|
-- if (s_doutb >= g_PACKET_LENGTH-1 ) then
|
322 |
|
|
-- remain_len <= s_doutb - g_PACKET_LENGTH;
|
323 |
|
|
-- LastPacket <= '1';
|
324 |
|
|
-- St_ctrl <= st_0;
|
325 |
|
|
-- else
|
326 |
|
|
-- St_ctrl <= st_1_2;
|
327 |
|
|
-- s_dout_len <= s_doutb;
|
328 |
|
|
-- end if;
|
329 |
|
|
St_ctrl <= st_1_2;
|
330 |
|
|
s_dout_len <= s_doutb;
|
331 |
|
|
end if;
|
332 |
|
|
|
333 |
|
|
When st_1_2 => --LastPack
|
334 |
|
|
LED_state <= x"12";
|
335 |
|
|
s_start_out <= '1';
|
336 |
|
|
s_udp_header_len <= x"1";
|
337 |
|
|
s_fragment <= "000" & offset_fragment;--FrRSVD & dntFragSet & MoreFrag & offset_fragment
|
338 |
|
|
offset_fragment <= (others => '0');
|
339 |
|
|
-- s_dout_len <= s_doutb;
|
340 |
|
|
St_ctrl <= st_2;
|
341 |
|
|
|
342 |
|
|
When st_2 =>
|
343 |
|
|
LED_state <= x"02";
|
344 |
|
|
if (s_mac_ready = '1') then
|
345 |
|
|
St_ctrl <= st_3;
|
346 |
|
|
if (s_wd_cnt = s_dout_len -1) then
|
347 |
|
|
s_wd_cnt_rst <= '1';
|
348 |
|
|
s_start_out <= '0';
|
349 |
|
|
St_ctrl <= st_4;
|
350 |
|
|
-- if (i_din_valid = '1') then
|
351 |
|
|
-- s_wr_cnta <= s_wr_cnta - s_dout_len +1;
|
352 |
|
|
-- else
|
353 |
|
|
-- s_wr_cnta <= s_wr_cnta - s_dout_len;
|
354 |
|
|
-- end if;
|
355 |
|
|
end if;
|
356 |
|
|
end if;
|
357 |
|
|
|
358 |
|
|
When st_3 =>
|
359 |
|
|
LED_state <= x"03";
|
360 |
|
|
s_start_out <= '0';
|
361 |
|
|
-- if (s_mac_ready = '0') then
|
362 |
|
|
if (s_wd_cnt = s_dout_len -1) then
|
363 |
|
|
s_wd_cnt_rst <= '1';
|
364 |
|
|
St_ctrl <= st_idle;--st_4;
|
365 |
|
|
-- if (i_din_valid = '1') then
|
366 |
|
|
-- s_wr_cnta <= s_wr_cnta - s_dout_len +1;
|
367 |
|
|
-- else
|
368 |
|
|
-- s_wr_cnta <= s_wr_cnta - s_dout_len;
|
369 |
|
|
-- end if;
|
370 |
|
|
end if;
|
371 |
|
|
|
372 |
|
|
When st_4 =>
|
373 |
|
|
LED_state <= x"04";
|
374 |
|
|
s_wd_cnt_rst <= '0';
|
375 |
|
|
St_ctrl <= st_5;
|
376 |
|
|
|
377 |
|
|
When st_5 =>
|
378 |
|
|
LED_state <= x"05";
|
379 |
|
|
St_ctrl <= st_6;
|
380 |
|
|
|
381 |
|
|
When st_6 =>
|
382 |
|
|
LED_state <= x"06";
|
383 |
|
|
St_ctrl <= st_7;
|
384 |
|
|
|
385 |
|
|
When st_7 =>
|
386 |
|
|
LED_state <= x"07";
|
387 |
|
|
St_ctrl <= st_idle;
|
388 |
|
|
|
389 |
|
|
When others =>
|
390 |
|
|
end case;
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
end if;
|
394 |
|
|
end process;
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
--========================Fifo for Ping_Pong Writing and Reading Data =============================
|
399 |
|
|
inst_data_fifo:data_fifo_KED
|
400 |
|
|
port map
|
401 |
|
|
(
|
402 |
|
|
clk => i_clk,
|
403 |
|
|
srst => s_rst_a,
|
404 |
|
|
wr_en => s_wr_en_a,
|
405 |
|
|
din => s_dina,
|
406 |
|
|
rd_en => s_rd_ena,
|
407 |
|
|
dout => s_douta,
|
408 |
|
|
valid => s_fifo_valida,
|
409 |
|
|
data_count => data_fifo_cnt,
|
410 |
|
|
prog_full => prog_full1,
|
411 |
|
|
full => s_full_a,
|
412 |
|
|
empty => s_empty_a
|
413 |
|
|
);
|
414 |
|
|
--========================Fifo for Ping_Pong Writing and Reading Data =============================
|
415 |
|
|
inst_Tlast_fifo:Arr_fifo_KED
|
416 |
|
|
port map
|
417 |
|
|
(
|
418 |
|
|
clk => i_clk,
|
419 |
|
|
srst => s_rst_a,
|
420 |
|
|
wr_en => s_wr_en_b,
|
421 |
|
|
din => s_dinb,
|
422 |
|
|
rd_en => s_rd_enb,
|
423 |
|
|
dout => s_doutb,
|
424 |
|
|
valid => s_fifo_validb,
|
425 |
|
|
full => s_full_b,
|
426 |
|
|
empty => s_empty_b
|
427 |
|
|
);
|
428 |
|
|
|
429 |
|
|
--=================================================================================================
|
430 |
|
|
--my_ila_ping_pong : entity work.ila_LAN
|
431 |
|
|
--PORT MAP (
|
432 |
|
|
-- clk => i_clk,
|
433 |
|
|
|
434 |
|
|
-- probe0(0) => s_rst_a,
|
435 |
|
|
-- probe0(1) => s_wr_en_a,
|
436 |
|
|
-- probe0(9 downto 2) => s_dina,
|
437 |
|
|
-- probe0(10) => s_rd_ena,
|
438 |
|
|
-- probe0(18 downto 11) => s_douta,
|
439 |
|
|
-- probe0(19) => s_fifo_valida,
|
440 |
|
|
-- probe0(20) => prog_full1,
|
441 |
|
|
-- probe0(21) => s_full_a,
|
442 |
|
|
-- probe0(22) => s_empty_a,
|
443 |
|
|
-- probe0(23) => s_mac_ready,
|
444 |
|
|
-- probe0(39 downto 24) => s_wd_cnt,
|
445 |
|
|
-- probe0(55 downto 40) => s_wr_cnta,
|
446 |
|
|
-- probe0(56) => i_din_valid,
|
447 |
|
|
-- probe0(57) => i_din_last,
|
448 |
|
|
|
449 |
|
|
-- probe0(58) => s_wr_en_b,
|
450 |
|
|
-- probe0(74 downto 59) => s_dinb,
|
451 |
|
|
-- probe0(75) => s_rd_enb,
|
452 |
|
|
-- probe0(91 downto 76) => s_doutb,
|
453 |
|
|
-- probe0(92) => s_fifo_validb,
|
454 |
|
|
-- probe0(93) => s_full_b,
|
455 |
|
|
-- probe0(94) => s_empty_b,
|
456 |
|
|
|
457 |
|
|
-- probe0(102 downto 95) => LED_state,
|
458 |
|
|
-- probe0(118 downto 103) => s_fragment,
|
459 |
|
|
-- probe0(134 downto 119) => s_wr_cntb,
|
460 |
|
|
-- probe0(135) => s_wd_cnt_rst,
|
461 |
|
|
-- probe0(151 downto 136) => s_wr_cnta_r2,
|
462 |
|
|
-- probe0(152) => s_wr_en_b_r0 ,
|
463 |
|
|
-- probe0(153) => s_wr_en_b_r1 ,
|
464 |
|
|
-- probe0(154) => Num_frag_rst ,-- LastPacket,-- ,
|
465 |
|
|
-- probe0(162 downto 155) => cntr_frag,--remain_len,--s_dinb_r0 ,
|
466 |
|
|
-- probe0(170 downto 163) => Num_frag,--data_fifo_cnt,
|
467 |
|
|
-- probe0(181 downto 171) => data_fifo_cnt,
|
468 |
|
|
-- probe0(182) => remainPacket,
|
469 |
|
|
-- probe0(183) => readyFornext,
|
470 |
|
|
|
471 |
|
|
-- probe0(255 downto 184) => (others => '0')
|
472 |
|
|
--);
|
473 |
|
|
--=================================================================================================
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
end Behavioral;
|