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boa_a_m |
-------------------------------------------------------------
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-- Filename: PHY_CONFIG_V5.VHD
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-- Version: 2
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-- Date last modified: 2-4-11
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-- Inheritance: PHY_CONFIG.VHD, rev2 2-4-11
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--
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-- description: Configures a PHY through a MDIO interface.
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----------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity PHY_CONFIG is
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generic (
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PHY_ADDR: std_logic_vector(4 downto 0) -- PHY Address
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);
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Port (
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--// CLK, RESET
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SYNC_RESET: in std_logic;
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CLK: in std_logic;
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--// CONTROLS
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CONFIG_CHANGE: in std_logic;
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-- 1 CLK-wide pulse to activate any configuration change below.
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-- Not needed if the default values are acceptable.
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PHY_RESET: in std_logic;
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-- 1 = PHY software reset, 0 = no reset
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SPEED: in std_logic_vector(1 downto 0);
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-- 00 = force 10 Mbps
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-- 01 = force 100 Mbps
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-- 10 = force 1000 Mbps
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-- 11 = auto-negotiation (default)
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DUPLEX: in std_logic;
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-- 1 = full-duplex (default), 0 = half-duplex
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TEST_MODE: in std_logic_vector(1 downto 0);
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-- 00 = normal mode (default)
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-- 01 = loopback mode
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-- 10 = remote loopback
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-- 11 = led test mode
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POWER_DOWN: in std_logic;
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-- software power down mode. 1 = enabled, 0 = disabled (default).
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CLK_SKEW: in std_logic_vector(15 downto 0);
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-- Register 260 RGMII clock and control pad skew
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--// MONITORING
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SREG_READ_START: in std_logic;
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-- 1 CLK wide pulse to start read transaction
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-- will be ignored if the previous transaction is yet to be completed.
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SREG_REGAD: in std_logic_vector(8 downto 0);
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-- 32 register address space for the PHY
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-- 0 - 15 are standard PHY registers as per IEEE specification.
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-- 16 - 31 are vendor-specific registers
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-- 256+ are extended registers
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SREG_DATA : OUT std_logic_vector(15 downto 0);
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-- 16-bit status register. Read when SREG_SAMPLE_CLK = '1'
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SREG_SAMPLE_CLK: out std_logic;
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--// BASIC STATUS REPORT (status register 1)
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LINK_STATUS: out std_logic;
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-- 0 = link down, 1 = link up
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--// serial interface. connect to PHY
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MCLK: out std_logic;
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MDI: in std_logic; -- MDIO input
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MDO: out std_logic; -- MDIO output
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MDT: out std_logic -- MDIO tri-state
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);
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end entity;
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architecture Behavioral of PHY_CONFIG is
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--------------------------------------------------------
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-- COMPONENTS
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--------------------------------------------------------
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COMPONENT MII_MI_V6
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GENERIC (
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PHY_ADDR: std_logic_vector(4 downto 0)
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);
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PORT(
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SYNC_RESET : IN std_logic;
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CLK : IN std_logic;
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MI_REGAD : IN std_logic_vector(4 downto 0);
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MI_TX_DATA : IN std_logic_vector(15 downto 0);
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MI_READ_START : IN std_logic;
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MI_WRITE_START : IN std_logic;
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MDI: in std_logic; -- MDIO input
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MDO: out std_logic; -- MDIO output
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MDT: out std_logic; -- MDIO tri-state
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MI_RX_DATA : OUT std_logic_vector(15 downto 0);
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MI_TRANSACTION_COMPLETE : OUT std_logic;
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MCLK : OUT std_logic
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);
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END COMPONENT;
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--------------------------------------------------------
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-- SIGNALS
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--------------------------------------------------------
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signal STATE: std_logic_vector(3 downto 0) := "0000";
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signal MI_WRITE_START: std_logic := '0';
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signal MI_REGAD: std_logic_vector(4 downto 0) := "00000";
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signal MI_TX_DATA: std_logic_vector(15 downto 0);
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signal MI_READ_START: std_logic := '0';
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signal MI_RX_DATA: std_logic_vector(15 downto 0);
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signal MI_TRANSACTION_COMPLETE: std_logic;
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signal PHY_RESET_D: std_logic;
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signal SPEED_D: std_logic_vector(1 downto 0);
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signal LOOPBACK_MODE: std_logic;
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signal AUTONEG: std_logic;
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signal POWER_DOWN_D: std_logic;
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signal DUPLEX_D: std_logic;
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signal REMOTE_LOOPBACK: std_logic;
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signal LED_TEST_MODE: std_logic;
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constant RGMII_INBAND_STATUS_EN: std_logic := '1'; -- enable in-band status reporting in RGMII
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signal SREG_SAMPLE_CLK_local: std_logic := '0';
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--------------------------------------------------------
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-- IMPLEMENTATION
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--------------------------------------------------------
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begin
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---- save the configuration so that it does not change while the configuration is in progress
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RECLOCK_001: process(CLK)
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begin
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if rising_edge(CLK) then
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if(STATE = 0) and (CONFIG_CHANGE = '1') then
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PHY_RESET_D <= PHY_RESET;
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SPEED_D <= SPEED;
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DUPLEX_D <= DUPLEX;
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POWER_DOWN_D <= POWER_DOWN;
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if(SPEED = "11") then
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AUTONEG <= '1';
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else
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AUTONEG <= '0';
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end if;
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case TEST_MODE is
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when "00" =>
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LOOPBACK_MODE <= '0';
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REMOTE_LOOPBACK <= '0';
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LED_TEST_MODE <= '0';
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when "01" =>
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LOOPBACK_MODE <= '1';
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REMOTE_LOOPBACK <= '0';
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LED_TEST_MODE <= '0';
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when "10" =>
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LOOPBACK_MODE <= '0';
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REMOTE_LOOPBACK <= '1';
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LED_TEST_MODE <= '0';
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when others =>
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LOOPBACK_MODE <= '0';
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REMOTE_LOOPBACK <= '0';
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LED_TEST_MODE <= '1';
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end case;
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end if;
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end if;
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end process;
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-- state machine
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STATE_GEN: process(CLK)
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begin
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if rising_edge(CLK) then
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if(SYNC_RESET = '1') then
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STATE <= (others => '0');
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MI_WRITE_START <= '0';
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MI_READ_START <= '0';
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-- WRITE ALL CONFIGURATION REGISTERS
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elsif(STATE = 0) and (CONFIG_CHANGE = '1') then
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-- triggers a PHY reconfiguration. await PHY MDIO availability
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STATE <= STATE + 1;
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elsif(STATE = 1) and (MI_TRANSACTION_COMPLETE = '1') then
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-- PHY is ready for next transaction.
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-- Register 0: basic control (applicable to all: GMII, MII, RGMII)
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STATE <= STATE + 1;
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MI_REGAD <= "00000";
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MI_TX_DATA(15 downto 8) <= PHY_RESET_D & LOOPBACK_MODE & SPEED_D(0) & AUTONEG & POWER_DOWN_D & "00" & DUPLEX_D;
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MI_TX_DATA(7 downto 0) <= "0" & SPEED_D(1) & "000000";
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MI_WRITE_START <= '1';
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-- tested for Micrel KSZ90212RN -------
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-- adjust as needed depending on the PHY (the extended registers vary depending on the manufacturer/model).
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elsif(STATE = 2) and (MI_TRANSACTION_COMPLETE = '1') then
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STATE <= (others => '0');
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-- READ ONE STATUS REGISTER
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elsif(STATE = 0) and (SREG_READ_START = '1') and (SREG_REGAD(8) = '0') then
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-- triggers a PHY status read. await PHY MDIO availability
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STATE <= "1000";
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elsif(STATE = 8) and (MI_TRANSACTION_COMPLETE = '1') and (SREG_REGAD(8) = '0') then
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-- PHY is ready for next transaction.
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STATE <= STATE + 1;
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MI_REGAD <= SREG_REGAD(4 downto 0);
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MI_READ_START <= '1';
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elsif(STATE = 9) and (MI_TRANSACTION_COMPLETE = '1') then
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-- we are done reading a status register! Going back to idle.
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STATE <= (others => '0');
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SREG_SAMPLE_CLK_local <= '1';
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-- READ ONE EXTENDED REGISTER
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elsif(STATE = 0) and (SREG_READ_START = '1') and (SREG_REGAD(8) = '1') then
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-- Extended register (1/2)
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STATE <= "1000";
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MI_REGAD <= "01011";
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MI_TX_DATA <= "0000000" & SREG_REGAD; -- read extended register
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MI_WRITE_START <= '1';
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elsif(STATE = 8) and (MI_TRANSACTION_COMPLETE = '1') and (SREG_REGAD(8) = '1') then
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-- triggers a PHY status read. await PHY MDIO availability
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STATE <= STATE + 1;
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MI_REGAD <= "01101";
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MI_READ_START <= '1';
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elsif(STATE = 9) and (MI_TRANSACTION_COMPLETE = '1') then
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-- we are done reading a status register! Going back to idle.
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STATE <= (others => '0');
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SREG_SAMPLE_CLK_local <= '1';
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-- PERIODIC READ BASIC STATUS: LINK
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elsif(STATE = 0) and (MI_TRANSACTION_COMPLETE = '1') then
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-- Register 1: basic status (applicable to all: GMII, MII, RGMII)
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STATE <= "1010";
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MI_REGAD <= "10001";
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MI_READ_START <= '1';
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elsif(STATE = 10) and (MI_TRANSACTION_COMPLETE = '1') then
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-- we are done reading a status register! Going back to idle.
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STATE <= (others => '0');
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-- LINK_STATUS <= MI_RX_DATA(2); commented by KED
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else
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MI_WRITE_START <= '0';
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MI_READ_START <= '0';
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SREG_SAMPLE_CLK_local <= '0';
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end if;
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end if;
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end process;
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LINK_STATUS <= '1';--; Added by KED
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-- latch status register
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SREGOUT_001: process(CLK)
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begin
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if rising_edge(CLK) then
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SREG_SAMPLE_CLK <= SREG_SAMPLE_CLK_local;
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if(SREG_SAMPLE_CLK_local = '1') then
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SREG_DATA <= MI_RX_DATA;
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end if;
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end if;
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end process;
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Inst_MII_MI: MII_MI_V6
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GENERIC MAP(
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PHY_ADDR => PHY_ADDR
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)
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PORT MAP(
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SYNC_RESET => SYNC_RESET,
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CLK => CLK,
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MI_REGAD => MI_REGAD,
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MI_TX_DATA => MI_TX_DATA,
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MI_RX_DATA => MI_RX_DATA,
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MI_READ_START => MI_READ_START,
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MI_WRITE_START => MI_WRITE_START,
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MI_TRANSACTION_COMPLETE => MI_TRANSACTION_COMPLETE,
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MCLK => MCLK,
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MDI => MDI,
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MDO => MDO,
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MDT => MDT
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);
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end Behavioral;
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