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--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
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--VERSION_BEGIN 9.1SP2 cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END
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-- Copyright (C) 1991-2010 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--synthesis_resources = lut 1
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SUBDESIGN mux_0oc
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(
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data[3..0] : input;
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result[0..0] : output;
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sel[1..0] : input;
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)
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VARIABLE
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l1_w0_n0_mux_dataout : WIRE;
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l1_w0_n1_mux_dataout : WIRE;
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l2_w0_n0_mux_dataout : WIRE;
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data_wire[5..0] : WIRE;
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result_wire_ext[0..0] : WIRE;
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sel_wire[3..0] : WIRE;
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BEGIN
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l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[1..1] # !(sel_wire[0..0]) & data_wire[0..0];
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l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[3..3] # !(sel_wire[0..0]) & data_wire[2..2];
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l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[5..5] # !(sel_wire[3..3]) & data_wire[4..4];
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data_wire[] = ( l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
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result[] = result_wire_ext[];
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result_wire_ext[] = ( l2_w0_n0_mux_dataout);
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sel_wire[] = ( sel[1..1], B"00", sel[0..0]);
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END;
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--VALID FILE
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