URL
https://opencores.org/ocsvn/gnextrapolator/gnextrapolator/trunk
[/] [gnextrapolator/] [trunk/] [QuartusII/] [db/] [prev_cmp_gnextrapolator.tan.qmsg] - Blame information for rev 5
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 13 23:53:04 2012 " "Info: Processing started: Mon Aug 13 23:53:04 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4 " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
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{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "89 " "Warning: Found 89 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[0\] 0 " "Info: Pin \"indice_p_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[1\] 0 " "Info: Pin \"indice_p_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[2\] 0 " "Info: Pin \"indice_p_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[3\] 0 " "Info: Pin \"indice_p_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[4\] 0 " "Info: Pin \"indice_p_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
|
| 6 |
|
|
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
|
| 7 |
|
|
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_i " "Info: Assuming node \"clk_i\" is an undefined clock" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_i" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
|
| 8 |
|
|
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_i register resultado\[4\] register resultado\[13\] 120.99 MHz 8.265 ns Internal " "Info: Clock \"clk_i\" has Internal fmax of 120.99 MHz between source register \"resultado\[4\]\" and destination register \"resultado\[13\]\" (period= 8.265 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.051 ns + Longest register register " "Info: + Longest register to register delay is 8.051 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns resultado\[4\] 1 REG LCFF_X17_Y12_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y12_N13; Fanout = 3; REG Node = 'resultado\[4\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resultado[4] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.177 ns) 0.431 ns Mux86~0 2 COMB LCCOMB_X17_Y12_N0 7 " "Info: 2: + IC(0.254 ns) + CELL(0.177 ns) = 0.431 ns; Loc. = LCCOMB_X17_Y12_N0; Fanout = 7; COMB Node = 'Mux86~0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.431 ns" { resultado[4] Mux86~0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.403 ns) 2.198 ns Add2~26 3 COMB LCCOMB_X18_Y12_N20 2 " "Info: 3: + IC(1.364 ns) + CELL(0.403 ns) = 2.198 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 2; COMB Node = 'Add2~26'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.767 ns" { Mux86~0 Add2~26 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.239 ns Add2~30 4 COMB LCCOMB_X18_Y12_N22 2 " "Info: 4: + IC(0.000 ns) + CELL(0.041 ns) = 2.239 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 2; COMB Node = 'Add2~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~26 Add2~30 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.280 ns Add2~34 5 COMB LCCOMB_X18_Y12_N24 2 " "Info: 5: + IC(0.000 ns) + CELL(0.041 ns) = 2.280 ns; Loc. = LCCOMB_X18_Y12_N24; Fanout = 2; COMB Node = 'Add2~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~30 Add2~34 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.321 ns Add2~38 6 COMB LCCOMB_X18_Y12_N26 2 " "Info: 6: + IC(0.000 ns) + CELL(0.041 ns) = 2.321 ns; Loc. = LCCOMB_X18_Y12_N26; Fanout = 2; COMB Node = 'Add2~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~34 Add2~38 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.362 ns Add2~42 7 COMB LCCOMB_X18_Y12_N28 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 2.362 ns; Loc. = LCCOMB_X18_Y12_N28; Fanout = 2; COMB Node = 'Add2~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~38 Add2~42 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.205 ns) 2.567 ns Add2~46 8 COMB LCCOMB_X18_Y12_N30 2 " "Info: 8: + IC(0.000 ns) + CELL(0.205 ns) = 2.567 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 2; COMB Node = 'Add2~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.205 ns" { Add2~42 Add2~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 2.711 ns Add2~49 9 COMB LCCOMB_X18_Y11_N16 7 " "Info: 9: + IC(0.000 ns) + CELL(0.144 ns) = 2.711 ns; Loc. = LCCOMB_X18_Y11_N16; Fanout = 7; COMB Node = 'Add2~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add2~46 Add2~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.355 ns) 4.036 ns Add3~46 10 COMB LCCOMB_X19_Y13_N22 2 " "Info: 10: + IC(0.970 ns) + CELL(0.355 ns) = 4.036 ns; Loc. = LCCOMB_X19_Y13_N22; Fanout = 2; COMB Node = 'Add3~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { Add2~49 Add3~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 4.180 ns Add3~49 11 COMB LCCOMB_X19_Y13_N24 7 " "Info: 11: + IC(0.000 ns) + CELL(0.144 ns) = 4.180 ns; Loc. = LCCOMB_X19_Y13_N24; Fanout = 7; COMB Node = 'Add3~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add3~46 Add3~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.403 ns) 4.991 ns Add4~54 12 COMB LCCOMB_X18_Y13_N26 2 " "Info: 12: + IC(0.408 ns) + CELL(0.403 ns) = 4.991 ns; Loc. = LCCOMB_X18_Y13_N26; Fanout = 2; COMB Node = 'Add4~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Add3~49 Add4~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 5.135 ns Add4~57 13 COMB LCCOMB_X18_Y13_N28 7 " "Info: 13: + IC(0.000 ns) + CELL(0.144 ns) = 5.135 ns; Loc. = LCCOMB_X18_Y13_N28; Fanout = 7; COMB Node = 'Add4~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~54 Add4~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.403 ns) 5.927 ns Add5~54 14 COMB LCCOMB_X17_Y13_N26 1 " "Info: 14: + IC(0.389 ns) + CELL(0.403 ns) = 5.927 ns; Loc. = LCCOMB_X17_Y13_N26; Fanout = 1; COMB Node = 'Add5~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.792 ns" { Add4~57 Add5~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 6.071 ns Add5~57 15 COMB LCCOMB_X17_Y13_N28 2 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 6.071 ns; Loc. = LCCOMB_X17_Y13_N28; Fanout = 2; COMB Node = 'Add5~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add5~54 Add5~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.565 ns) 7.392 ns Add9~53 16 COMB LCCOMB_X17_Y11_N10 2 " "Info: 16: + IC(0.756 ns) + CELL(0.565 ns) = 7.392 ns; Loc. = LCCOMB_X17_Y11_N10; Fanout = 2; COMB Node = 'Add9~53'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { Add5~57 Add9~53 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 124 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.355 ns) 8.051 ns resultado\[13\] 17 REG LCFF_X17_Y11_N31 2 " "Info: 17: + IC(0.304 ns) + CELL(0.355 ns) = 8.051 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.659 ns" { Add9~53 resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.606 ns ( 44.79 % ) " "Info: Total cell delay = 3.606 ns ( 44.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.445 ns ( 55.21 % ) " "Info: Total interconnect delay = 4.445 ns ( 55.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.051 ns" { resultado[4] Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.051 ns" { resultado[4] {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.254ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.177ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.829 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_i\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns resultado\[13\] 3 REG LCFF_X17_Y11_N31 2 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.830 ns - Longest register " "Info: - Longest clock path from clock \"clk_i\" to source register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[4\] 3 REG LCFF_X17_Y12_N13 3 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X17_Y12_N13; Fanout = 3; REG Node = 'resultado\[4\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[4] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[4] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.051 ns" { resultado[4] Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.051 ns" { resultado[4] {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.254ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.177ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[4] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
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{ "Info" "ITDB_TSU_RESULT" "resultado\[13\] extrapolar_i clk_i 10.977 ns register " "Info: tsu for register \"resultado\[13\]\" (data pin = \"extrapolar_i\", clock pin = \"clk_i\") is 10.977 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.702 ns + Longest pin register " "Info: + Longest pin to register delay is 13.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns extrapolar_i 1 PIN PIN_V11 43 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_V11; Fanout = 43; PIN Node = 'extrapolar_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.825 ns) + CELL(0.313 ns) 6.082 ns Mux86~0 2 COMB LCCOMB_X17_Y12_N0 7 " "Info: 2: + IC(4.825 ns) + CELL(0.313 ns) = 6.082 ns; Loc. = LCCOMB_X17_Y12_N0; Fanout = 7; COMB Node = 'Mux86~0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.138 ns" { extrapolar_i Mux86~0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.403 ns) 7.849 ns Add2~26 3 COMB LCCOMB_X18_Y12_N20 2 " "Info: 3: + IC(1.364 ns) + CELL(0.403 ns) = 7.849 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 2; COMB Node = 'Add2~26'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.767 ns" { Mux86~0 Add2~26 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 7.890 ns Add2~30 4 COMB LCCOMB_X18_Y12_N22 2 " "Info: 4: + IC(0.000 ns) + CELL(0.041 ns) = 7.890 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 2; COMB Node = 'Add2~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~26 Add2~30 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 7.931 ns Add2~34 5 COMB LCCOMB_X18_Y12_N24 2 " "Info: 5: + IC(0.000 ns) + CELL(0.041 ns) = 7.931 ns; Loc. = LCCOMB_X18_Y12_N24; Fanout = 2; COMB Node = 'Add2~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~30 Add2~34 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 7.972 ns Add2~38 6 COMB LCCOMB_X18_Y12_N26 2 " "Info: 6: + IC(0.000 ns) + CELL(0.041 ns) = 7.972 ns; Loc. = LCCOMB_X18_Y12_N26; Fanout = 2; COMB Node = 'Add2~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~34 Add2~38 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.013 ns Add2~42 7 COMB LCCOMB_X18_Y12_N28 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 8.013 ns; Loc. = LCCOMB_X18_Y12_N28; Fanout = 2; COMB Node = 'Add2~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~38 Add2~42 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.205 ns) 8.218 ns Add2~46 8 COMB LCCOMB_X18_Y12_N30 2 " "Info: 8: + IC(0.000 ns) + CELL(0.205 ns) = 8.218 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 2; COMB Node = 'Add2~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.205 ns" { Add2~42 Add2~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 8.362 ns Add2~49 9 COMB LCCOMB_X18_Y11_N16 7 " "Info: 9: + IC(0.000 ns) + CELL(0.144 ns) = 8.362 ns; Loc. = LCCOMB_X18_Y11_N16; Fanout = 7; COMB Node = 'Add2~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add2~46 Add2~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.355 ns) 9.687 ns Add3~46 10 COMB LCCOMB_X19_Y13_N22 2 " "Info: 10: + IC(0.970 ns) + CELL(0.355 ns) = 9.687 ns; Loc. = LCCOMB_X19_Y13_N22; Fanout = 2; COMB Node = 'Add3~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { Add2~49 Add3~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 9.831 ns Add3~49 11 COMB LCCOMB_X19_Y13_N24 7 " "Info: 11: + IC(0.000 ns) + CELL(0.144 ns) = 9.831 ns; Loc. = LCCOMB_X19_Y13_N24; Fanout = 7; COMB Node = 'Add3~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add3~46 Add3~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.403 ns) 10.642 ns Add4~54 12 COMB LCCOMB_X18_Y13_N26 2 " "Info: 12: + IC(0.408 ns) + CELL(0.403 ns) = 10.642 ns; Loc. = LCCOMB_X18_Y13_N26; Fanout = 2; COMB Node = 'Add4~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Add3~49 Add4~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 10.786 ns Add4~57 13 COMB LCCOMB_X18_Y13_N28 7 " "Info: 13: + IC(0.000 ns) + CELL(0.144 ns) = 10.786 ns; Loc. = LCCOMB_X18_Y13_N28; Fanout = 7; COMB Node = 'Add4~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~54 Add4~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.403 ns) 11.578 ns Add5~54 14 COMB LCCOMB_X17_Y13_N26 1 " "Info: 14: + IC(0.389 ns) + CELL(0.403 ns) = 11.578 ns; Loc. = LCCOMB_X17_Y13_N26; Fanout = 1; COMB Node = 'Add5~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.792 ns" { Add4~57 Add5~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 11.722 ns Add5~57 15 COMB LCCOMB_X17_Y13_N28 2 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 11.722 ns; Loc. = LCCOMB_X17_Y13_N28; Fanout = 2; COMB Node = 'Add5~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add5~54 Add5~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.565 ns) 13.043 ns Add9~53 16 COMB LCCOMB_X17_Y11_N10 2 " "Info: 16: + IC(0.756 ns) + CELL(0.565 ns) = 13.043 ns; Loc. = LCCOMB_X17_Y11_N10; Fanout = 2; COMB Node = 'Add9~53'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { Add5~57 Add9~53 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 124 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.355 ns) 13.702 ns resultado\[13\] 17 REG LCFF_X17_Y11_N31 2 " "Info: 17: + IC(0.304 ns) + CELL(0.355 ns) = 13.702 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.659 ns" { Add9~53 resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.686 ns ( 34.20 % ) " "Info: Total cell delay = 4.686 ns ( 34.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.016 ns ( 65.80 % ) " "Info: Total interconnect delay = 9.016 ns ( 65.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.702 ns" { extrapolar_i Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "13.702 ns" { extrapolar_i {} extrapolar_i~combout {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.000ns 4.825ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.944ns 0.313ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.829 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_i\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns resultado\[13\] 3 REG LCFF_X17_Y11_N31 2 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.702 ns" { extrapolar_i Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "13.702 ns" { extrapolar_i {} extrapolar_i~combout {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.000ns 4.825ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.944ns 0.313ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
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{ "Info" "ITDB_FULL_TCO_RESULT" "clk_i fxx3_o\[13\] fxx3_o\[13\]~reg0 7.983 ns register " "Info: tco from clock \"clk_i\" to destination pin \"fxx3_o\[13\]\" through register \"fxx3_o\[13\]~reg0\" is 7.983 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.829 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to source register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns fxx3_o\[13\]~reg0 3 REG LCFF_X15_Y12_N1 1 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X15_Y12_N1; Fanout = 1; REG Node = 'fxx3_o\[13\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl fxx3_o[13]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx3_o[13]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[13]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.045 ns + Longest register pin " "Info: + Longest register to pin delay is 5.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fxx3_o\[13\]~reg0 1 REG LCFF_X15_Y12_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y12_N1; Fanout = 1; REG Node = 'fxx3_o\[13\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[13]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.445 ns) 5.045 ns fxx3_o\[13\] 2 PIN PIN_K3 0 " "Info: 2: + IC(2.600 ns) + CELL(2.445 ns) = 5.045 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'fxx3_o\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { fxx3_o[13]~reg0 fxx3_o[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.445 ns ( 48.46 % ) " "Info: Total cell delay = 2.445 ns ( 48.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 51.54 % ) " "Info: Total interconnect delay = 2.600 ns ( 51.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { fxx3_o[13]~reg0 fxx3_o[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.045 ns" { fxx3_o[13]~reg0 {} fxx3_o[13] {} } { 0.000ns 2.600ns } { 0.000ns 2.445ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx3_o[13]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[13]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { fxx3_o[13]~reg0 fxx3_o[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.045 ns" { fxx3_o[13]~reg0 {} fxx3_o[13] {} } { 0.000ns 2.600ns } { 0.000ns 2.445ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
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{ "Info" "ITDB_TH_RESULT" "fxx_o\[5\]~reg0 rst_i clk_i -0.647 ns register " "Info: th for register \"fxx_o\[5\]~reg0\" (data pin = \"rst_i\", clock pin = \"clk_i\") is -0.647 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.829 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns fxx_o\[5\]~reg0 3 REG LCFF_X18_Y11_N3 1 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X18_Y11_N3; Fanout = 1; REG Node = 'fxx_o\[5\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl fxx_o[5]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.172 ns + " "Info: + Micro hold delay of destination is 0.172 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.648 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns rst_i 1 PIN PIN_M21 86 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_M21; Fanout = 86; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(0.858 ns) 3.648 ns fxx_o\[5\]~reg0 2 REG LCFF_X18_Y11_N3 1 " "Info: 2: + IC(1.806 ns) + CELL(0.858 ns) = 3.648 ns; Loc. = LCFF_X18_Y11_N3; Fanout = 1; REG Node = 'fxx_o\[5\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { rst_i fxx_o[5]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.842 ns ( 50.49 % ) " "Info: Total cell delay = 1.842 ns ( 50.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.806 ns ( 49.51 % ) " "Info: Total interconnect delay = 1.806 ns ( 49.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.648 ns" { rst_i fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.648 ns" { rst_i {} rst_i~combout {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.984ns 0.858ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.648 ns" { rst_i fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.648 ns" { rst_i {} rst_i~combout {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.984ns 0.858ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Peak virtual memory: 152 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 13 23:53:09 2012 " "Info: Processing ended: Mon Aug 13 23:53:09 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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