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Classic Timing Analyzer report for gnextrapolator
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Tue Aug 14 00:28:18 2012
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Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Timing Analyzer Settings
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4. Clock Settings Summary
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5. Clock Setup: 'clk_i'
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6. tsu
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7. tco
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8. th
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9. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------+-----------------+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------+-----------------+------------+----------+--------------+
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; Worst-case tsu ; N/A ; None ; 12.402 ns ; extrapolar_i ; resultado[15] ; -- ; clk_i ; 0 ;
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; Worst-case tco ; N/A ; None ; 8.310 ns ; fxx3_o[14]~reg0 ; fxx3_o[14] ; clk_i ; -- ; 0 ;
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; Worst-case th ; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[15]~reg0 ; -- ; clk_i ; 0 ;
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; Clock Setup: 'clk_i' ; N/A ; None ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[15] ; clk_i ; clk_i ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------+-----------------+------------+----------+--------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Settings ;
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+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
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; Option ; Setting ; From ; To ; Entity Name ;
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+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
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; Device Name ; EP2S15F484C4 ; ; ; ;
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; Timing Models ; Final ; ; ; ;
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; Default hold multicycle ; Same as Multicycle ; ; ; ;
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; Cut paths between unrelated clock domains ; On ; ; ; ;
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; Cut off read during write signal paths ; On ; ; ; ;
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; Cut off feedback from I/O pins ; On ; ; ; ;
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; Report Combined Fast/Slow Timing ; Off ; ; ; ;
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; Ignore Clock Settings ; Off ; ; ; ;
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; Analyze latches as synchronous elements ; On ; ; ; ;
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
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; Enable Clock Latency ; Off ; ; ; ;
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; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
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; Minimum Core Junction Temperature ; 0 ; ; ; ;
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; Maximum Core Junction Temperature ; 85 ; ; ; ;
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; Number of source nodes to report per destination node ; 10 ; ; ; ;
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; Number of destination nodes to report ; 10 ; ; ; ;
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; Number of paths to report ; 200 ; ; ; ;
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; Report Minimum Timing Checks ; Off ; ; ; ;
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; Use Fast Timing Models ; Off ; ; ; ;
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; Report IO Paths Separately ; Off ; ; ; ;
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; Perform Multicorner Analysis ; On ; ; ; ;
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
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; Reports worst-case timing paths for each clock domain and analysis ; Off ; ; ; ;
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; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
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; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
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; Output I/O Timing Endpoint ; Near End ; ; ; ;
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+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Settings Summary ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; clk_i ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Setup: 'clk_i' ;
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+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
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+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ;
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; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ;
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; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ;
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; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ;
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; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ;
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; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ;
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; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ;
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; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ;
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; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ;
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; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ;
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; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ;
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; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ;
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; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ;
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; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ;
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; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ;
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; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ;
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; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ;
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; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ;
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; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ;
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; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ;
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; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ;
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; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ;
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; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ;
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; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ;
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; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ;
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; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ;
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; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ;
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; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ;
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; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ;
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; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ;
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; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ;
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; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ;
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; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ;
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; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ;
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; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ;
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; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ;
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; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ;
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; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ;
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139 |
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; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ;
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140 |
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; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ;
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141 |
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; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ;
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142 |
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; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ;
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143 |
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; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ;
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144 |
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; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ;
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145 |
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; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ;
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146 |
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; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ;
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147 |
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; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ;
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148 |
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; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ;
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149 |
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; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ;
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150 |
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; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ;
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151 |
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; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ;
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152 |
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; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ;
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153 |
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; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ;
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154 |
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; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ;
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155 |
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; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ;
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156 |
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; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ;
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157 |
|
|
; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ;
|
158 |
|
|
; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ;
|
159 |
|
|
; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ;
|
160 |
|
|
; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ;
|
161 |
|
|
; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ;
|
162 |
|
|
; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ;
|
163 |
|
|
; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ;
|
164 |
|
|
; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ;
|
165 |
|
|
; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ;
|
166 |
|
|
; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ;
|
167 |
|
|
; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ;
|
168 |
|
|
; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ;
|
169 |
|
|
; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ;
|
170 |
|
|
; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ;
|
171 |
|
|
; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ;
|
172 |
|
|
; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ;
|
173 |
|
|
; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ;
|
174 |
|
|
; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ;
|
175 |
|
|
; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ;
|
176 |
|
|
; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ;
|
177 |
|
|
; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ;
|
178 |
|
|
; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ;
|
179 |
|
|
; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ;
|
180 |
|
|
; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ;
|
181 |
|
|
; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ;
|
182 |
|
|
; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ;
|
183 |
|
|
; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ;
|
184 |
|
|
; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ;
|
185 |
|
|
; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ;
|
186 |
|
|
; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ;
|
187 |
|
|
; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ;
|
188 |
|
|
; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ;
|
189 |
|
|
; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ;
|
190 |
|
|
; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ;
|
191 |
|
|
; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ;
|
192 |
|
|
; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ;
|
193 |
|
|
; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ;
|
194 |
|
|
; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ;
|
195 |
|
|
; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ;
|
196 |
|
|
; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ;
|
197 |
|
|
; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ;
|
198 |
|
|
; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ;
|
199 |
|
|
; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ;
|
200 |
|
|
; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ;
|
201 |
|
|
; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ;
|
202 |
|
|
; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ;
|
203 |
|
|
; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ;
|
204 |
|
|
; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ;
|
205 |
|
|
; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ;
|
206 |
|
|
; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ;
|
207 |
|
|
; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ;
|
208 |
|
|
; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ;
|
209 |
|
|
; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ;
|
210 |
|
|
; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ;
|
211 |
|
|
; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ;
|
212 |
|
|
; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ;
|
213 |
|
|
; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ;
|
214 |
|
|
; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ;
|
215 |
|
|
; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ;
|
216 |
|
|
; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ;
|
217 |
|
|
; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ;
|
218 |
|
|
; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ;
|
219 |
|
|
; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ;
|
220 |
|
|
; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ;
|
221 |
|
|
; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ;
|
222 |
|
|
; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ;
|
223 |
|
|
; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ;
|
224 |
|
|
; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ;
|
225 |
|
|
; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ;
|
226 |
|
|
; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ;
|
227 |
|
|
; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ;
|
228 |
|
|
; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ;
|
229 |
|
|
; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ;
|
230 |
|
|
; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ;
|
231 |
|
|
; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ;
|
232 |
|
|
; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ;
|
233 |
|
|
; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ;
|
234 |
|
|
; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ;
|
235 |
|
|
; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ;
|
236 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ;
|
237 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ;
|
238 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ;
|
239 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ;
|
240 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ;
|
241 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ;
|
242 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ;
|
243 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ;
|
244 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ;
|
245 |
|
|
; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ;
|
246 |
|
|
; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ;
|
247 |
|
|
; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ;
|
248 |
|
|
; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ;
|
249 |
|
|
; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ;
|
250 |
|
|
; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ;
|
251 |
|
|
; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ;
|
252 |
|
|
; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ;
|
253 |
|
|
; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ;
|
254 |
|
|
; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ;
|
255 |
|
|
; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ;
|
256 |
|
|
; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ;
|
257 |
|
|
; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ;
|
258 |
|
|
; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ;
|
259 |
|
|
; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ;
|
260 |
|
|
; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ;
|
261 |
|
|
; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ;
|
262 |
|
|
; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ;
|
263 |
|
|
; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ;
|
264 |
|
|
; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ;
|
265 |
|
|
; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ;
|
266 |
|
|
; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ;
|
267 |
|
|
; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ;
|
268 |
|
|
; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ;
|
269 |
|
|
; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ;
|
270 |
|
|
; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ;
|
271 |
|
|
; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ;
|
272 |
|
|
; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ;
|
273 |
|
|
; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ;
|
274 |
|
|
; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ;
|
275 |
|
|
; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ;
|
276 |
|
|
; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ;
|
277 |
|
|
; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ;
|
278 |
|
|
; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ;
|
279 |
|
|
; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ;
|
280 |
|
|
; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ;
|
281 |
|
|
; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ;
|
282 |
|
|
; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ;
|
283 |
|
|
; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ;
|
284 |
|
|
; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ;
|
285 |
|
|
; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ;
|
286 |
|
|
; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ;
|
287 |
|
|
; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ;
|
288 |
|
|
; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ;
|
289 |
|
|
; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ;
|
290 |
|
|
; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ;
|
291 |
|
|
; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ;
|
292 |
|
|
; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ;
|
293 |
|
|
; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ;
|
294 |
|
|
; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ;
|
295 |
|
|
; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ;
|
296 |
|
|
; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ;
|
297 |
|
|
; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ;
|
298 |
|
|
; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ;
|
299 |
|
|
; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ;
|
300 |
|
|
; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ;
|
301 |
|
|
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
|
302 |
|
|
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
|
306 |
|
|
; tsu ;
|
307 |
|
|
+-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------+----------+
|
308 |
|
|
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
|
309 |
|
|
+-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------+----------+
|
310 |
|
|
; N/A ; None ; 12.402 ns ; extrapolar_i ; resultado[15] ; clk_i ;
|
311 |
|
|
; N/A ; None ; 12.105 ns ; extrapolar_i ; resultado[14] ; clk_i ;
|
312 |
|
|
; N/A ; None ; 11.898 ns ; extrapolar_i ; resultado[13] ; clk_i ;
|
313 |
|
|
; N/A ; None ; 11.647 ns ; extrapolar_i ; resul_o[12]~reg0 ; clk_i ;
|
314 |
|
|
; N/A ; None ; 11.573 ns ; extrapolar_i ; resul_o[11]~reg0 ; clk_i ;
|
315 |
|
|
; N/A ; None ; 11.555 ns ; extrapolar_i ; resultado[8] ; clk_i ;
|
316 |
|
|
; N/A ; None ; 11.482 ns ; extrapolar_i ; resul_o[9]~reg0 ; clk_i ;
|
317 |
|
|
; N/A ; None ; 11.411 ns ; extrapolar_i ; resultado[6] ; clk_i ;
|
318 |
|
|
; N/A ; None ; 11.393 ns ; extrapolar_i ; resul_o[10]~reg0 ; clk_i ;
|
319 |
|
|
; N/A ; None ; 11.238 ns ; extrapolar_i ; resul_o[15]~reg0 ; clk_i ;
|
320 |
|
|
; N/A ; None ; 11.163 ns ; extrapolar_i ; resul_o[7]~reg0 ; clk_i ;
|
321 |
|
|
; N/A ; None ; 11.121 ns ; extrapolar_i ; resul_o[14]~reg0 ; clk_i ;
|
322 |
|
|
; N/A ; None ; 11.080 ns ; extrapolar_i ; resul_o[13]~reg0 ; clk_i ;
|
323 |
|
|
; N/A ; None ; 11.013 ns ; extrapolar_i ; resultado[12] ; clk_i ;
|
324 |
|
|
; N/A ; None ; 10.943 ns ; extrapolar_i ; resultado[11] ; clk_i ;
|
325 |
|
|
; N/A ; None ; 10.900 ns ; extrapolar_i ; resultado[10] ; clk_i ;
|
326 |
|
|
; N/A ; None ; 10.859 ns ; extrapolar_i ; resultado[9] ; clk_i ;
|
327 |
|
|
; N/A ; None ; 10.810 ns ; extrapolar_i ; resul_o[8]~reg0 ; clk_i ;
|
328 |
|
|
; N/A ; None ; 10.742 ns ; extrapolar_i ; resultado[5] ; clk_i ;
|
329 |
|
|
; N/A ; None ; 10.718 ns ; extrapolar_i ; resultado[4] ; clk_i ;
|
330 |
|
|
; N/A ; None ; 10.667 ns ; extrapolar_i ; resultado[7] ; clk_i ;
|
331 |
|
|
; N/A ; None ; 10.666 ns ; extrapolar_i ; resultado[3] ; clk_i ;
|
332 |
|
|
; N/A ; None ; 10.664 ns ; extrapolar_i ; resultado[2] ; clk_i ;
|
333 |
|
|
; N/A ; None ; 10.578 ns ; extrapolar_i ; resul_o[6]~reg0 ; clk_i ;
|
334 |
|
|
; N/A ; None ; 10.392 ns ; extrapolar_i ; resultado[1] ; clk_i ;
|
335 |
|
|
; N/A ; None ; 10.228 ns ; extrapolar_i ; resultado[0] ; clk_i ;
|
336 |
|
|
; N/A ; None ; 10.068 ns ; extrapolar_i ; fxx4_o[15]~reg0 ; clk_i ;
|
337 |
|
|
; N/A ; None ; 9.925 ns ; extrapolar_i ; fxx4_o[14]~reg0 ; clk_i ;
|
338 |
|
|
; N/A ; None ; 9.884 ns ; extrapolar_i ; fxx4_o[13]~reg0 ; clk_i ;
|
339 |
|
|
; N/A ; None ; 9.843 ns ; extrapolar_i ; fxx4_o[12]~reg0 ; clk_i ;
|
340 |
|
|
; N/A ; None ; 9.802 ns ; extrapolar_i ; fxx4_o[11]~reg0 ; clk_i ;
|
341 |
|
|
; N/A ; None ; 9.761 ns ; extrapolar_i ; fxx4_o[10]~reg0 ; clk_i ;
|
342 |
|
|
; N/A ; None ; 9.720 ns ; extrapolar_i ; fxx4_o[9]~reg0 ; clk_i ;
|
343 |
|
|
; N/A ; None ; 9.693 ns ; extrapolar_i ; fxx3_o[12]~reg0 ; clk_i ;
|
344 |
|
|
; N/A ; None ; 9.679 ns ; extrapolar_i ; fxx4_o[8]~reg0 ; clk_i ;
|
345 |
|
|
; N/A ; None ; 9.626 ns ; extrapolar_i ; resul_o[5]~reg0 ; clk_i ;
|
346 |
|
|
; N/A ; None ; 9.612 ns ; extrapolar_i ; fxx4_o[7]~reg0 ; clk_i ;
|
347 |
|
|
; N/A ; None ; 9.607 ns ; extrapolar_i ; fxx3_o[10]~reg0 ; clk_i ;
|
348 |
|
|
; N/A ; None ; 9.585 ns ; extrapolar_i ; resul_o[4]~reg0 ; clk_i ;
|
349 |
|
|
; N/A ; None ; 9.544 ns ; extrapolar_i ; resul_o[3]~reg0 ; clk_i ;
|
350 |
|
|
; N/A ; None ; 9.503 ns ; extrapolar_i ; resul_o[2]~reg0 ; clk_i ;
|
351 |
|
|
; N/A ; None ; 9.498 ns ; extrapolar_i ; nabla3fx[0][14] ; clk_i ;
|
352 |
|
|
; N/A ; None ; 9.436 ns ; extrapolar_i ; resul_o[1]~reg0 ; clk_i ;
|
353 |
|
|
; N/A ; None ; 9.415 ns ; extrapolar_i ; fxx3_o[15]~reg0 ; clk_i ;
|
354 |
|
|
; N/A ; None ; 9.375 ns ; extrapolar_i ; nabla3fx[0][11] ; clk_i ;
|
355 |
|
|
; N/A ; None ; 9.336 ns ; extrapolar_i ; fxx3_o[13]~reg0 ; clk_i ;
|
356 |
|
|
; N/A ; None ; 9.298 ns ; extrapolar_i ; nabla3fx[0][9] ; clk_i ;
|
357 |
|
|
; N/A ; None ; 9.128 ns ; extrapolar_i ; nabla3fx[0][8] ; clk_i ;
|
358 |
|
|
; N/A ; None ; 9.118 ns ; extrapolar_i ; resul_o[0]~reg0 ; clk_i ;
|
359 |
|
|
; N/A ; None ; 9.015 ns ; extrapolar_i ; fxx4_o[6]~reg0 ; clk_i ;
|
360 |
|
|
; N/A ; None ; 8.984 ns ; extrapolar_i ; nabla3fx[0][15] ; clk_i ;
|
361 |
|
|
; N/A ; None ; 8.943 ns ; extrapolar_i ; fxx3_o[14]~reg0 ; clk_i ;
|
362 |
|
|
; N/A ; None ; 8.902 ns ; extrapolar_i ; nabla3fx[0][13] ; clk_i ;
|
363 |
|
|
; N/A ; None ; 8.861 ns ; extrapolar_i ; nabla3fx[0][12] ; clk_i ;
|
364 |
|
|
; N/A ; None ; 8.850 ns ; extrapolar_i ; fxx3_o[7]~reg0 ; clk_i ;
|
365 |
|
|
; N/A ; None ; 8.841 ns ; extrapolar_i ; fxx2_o[13]~reg0 ; clk_i ;
|
366 |
|
|
; N/A ; None ; 8.820 ns ; extrapolar_i ; fxx3_o[11]~reg0 ; clk_i ;
|
367 |
|
|
; N/A ; None ; 8.779 ns ; extrapolar_i ; nabla3fx[0][10] ; clk_i ;
|
368 |
|
|
; N/A ; None ; 8.772 ns ; extrapolar_i ; fxx2_o[15]~reg0 ; clk_i ;
|
369 |
|
|
; N/A ; None ; 8.758 ns ; extrapolar_i ; nabla3fx[0][6] ; clk_i ;
|
370 |
|
|
; N/A ; None ; 8.738 ns ; extrapolar_i ; fxx3_o[9]~reg0 ; clk_i ;
|
371 |
|
|
; N/A ; None ; 8.726 ns ; extrapolar_i ; fxx2_o[14]~reg0 ; clk_i ;
|
372 |
|
|
; N/A ; None ; 8.697 ns ; extrapolar_i ; fxx3_o[8]~reg0 ; clk_i ;
|
373 |
|
|
; N/A ; None ; 8.674 ns ; extrapolar_i ; fxx2_o[10]~reg0 ; clk_i ;
|
374 |
|
|
; N/A ; None ; 8.628 ns ; extrapolar_i ; fxx2_o[12]~reg0 ; clk_i ;
|
375 |
|
|
; N/A ; None ; 8.610 ns ; extrapolar_i ; fxx2_o[8]~reg0 ; clk_i ;
|
376 |
|
|
; N/A ; None ; 8.490 ns ; extrapolar_i ; nabla2fx[0][11] ; clk_i ;
|
377 |
|
|
; N/A ; None ; 8.422 ns ; extrapolar_i ; nabla2fx[0][9] ; clk_i ;
|
378 |
|
|
; N/A ; None ; 8.416 ns ; extrapolar_i ; nabla3fx[0][7] ; clk_i ;
|
379 |
|
|
; N/A ; None ; 8.202 ns ; extrapolar_i ; fxx3_o[6]~reg0 ; clk_i ;
|
380 |
|
|
; N/A ; None ; 7.921 ns ; extrapolar_i ; fxx1_o[14]~reg0 ; clk_i ;
|
381 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[3] ; clk_i ;
|
382 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[2] ; clk_i ;
|
383 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[7] ; clk_i ;
|
384 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[6] ; clk_i ;
|
385 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[1] ; clk_i ;
|
386 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[0] ; clk_i ;
|
387 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[4] ; clk_i ;
|
388 |
|
|
; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[5] ; clk_i ;
|
389 |
|
|
; N/A ; None ; 7.802 ns ; extrapolar_i ; fxx4_o[5]~reg0 ; clk_i ;
|
390 |
|
|
; N/A ; None ; 7.760 ns ; extrapolar_i ; fxx2_o[7]~reg0 ; clk_i ;
|
391 |
|
|
; N/A ; None ; 7.753 ns ; extrapolar_i ; nabla2fx[0][15] ; clk_i ;
|
392 |
|
|
; N/A ; None ; 7.746 ns ; extrapolar_i ; fxx4_o[4]~reg0 ; clk_i ;
|
393 |
|
|
; N/A ; None ; 7.723 ns ; extrapolar_i ; fxx1_o[11]~reg0 ; clk_i ;
|
394 |
|
|
; N/A ; None ; 7.682 ns ; extrapolar_i ; fxx4_o[3]~reg0 ; clk_i ;
|
395 |
|
|
; N/A ; None ; 7.650 ns ; extrapolar_i ; fxx3_o[3]~reg0 ; clk_i ;
|
396 |
|
|
; N/A ; None ; 7.642 ns ; extrapolar_i ; nabla2fx[0][14] ; clk_i ;
|
397 |
|
|
; N/A ; None ; 7.641 ns ; extrapolar_i ; fxx4_o[2]~reg0 ; clk_i ;
|
398 |
|
|
; N/A ; None ; 7.620 ns ; extrapolar_i ; nabla1fx[0][7] ; clk_i ;
|
399 |
|
|
; N/A ; None ; 7.601 ns ; extrapolar_i ; nabla2fx[0][13] ; clk_i ;
|
400 |
|
|
; N/A ; None ; 7.595 ns ; extrapolar_i ; fxx3_o[2]~reg0 ; clk_i ;
|
401 |
|
|
; N/A ; None ; 7.574 ns ; extrapolar_i ; fxx4_o[1]~reg0 ; clk_i ;
|
402 |
|
|
; N/A ; None ; 7.560 ns ; extrapolar_i ; nabla2fx[0][12] ; clk_i ;
|
403 |
|
|
; N/A ; None ; 7.547 ns ; extrapolar_i ; fxx3_o[1]~reg0 ; clk_i ;
|
404 |
|
|
; N/A ; None ; 7.519 ns ; extrapolar_i ; fxx2_o[11]~reg0 ; clk_i ;
|
405 |
|
|
; N/A ; None ; 7.508 ns ; extrapolar_i ; fxx1_o[9]~reg0 ; clk_i ;
|
406 |
|
|
; N/A ; None ; 7.478 ns ; extrapolar_i ; nabla2fx[0][10] ; clk_i ;
|
407 |
|
|
; N/A ; None ; 7.457 ns ; extrapolar_i ; nabla2fx[0][6] ; clk_i ;
|
408 |
|
|
; N/A ; None ; 7.443 ns ; extrapolar_i ; nabla1fx[0][15] ; clk_i ;
|
409 |
|
|
; N/A ; None ; 7.437 ns ; extrapolar_i ; fxx2_o[9]~reg0 ; clk_i ;
|
410 |
|
|
; N/A ; None ; 7.428 ns ; extrapolar_i ; fxx4_o[0]~reg0 ; clk_i ;
|
411 |
|
|
; N/A ; None ; 7.413 ns ; extrapolar_i ; nabla3fx[0][4] ; clk_i ;
|
412 |
|
|
; N/A ; None ; 7.396 ns ; extrapolar_i ; nabla2fx[0][8] ; clk_i ;
|
413 |
|
|
; N/A ; None ; 7.354 ns ; extrapolar_i ; nabla1fx[0][10] ; clk_i ;
|
414 |
|
|
; N/A ; None ; 7.341 ns ; extrapolar_i ; fxx3_o[5]~reg0 ; clk_i ;
|
415 |
|
|
; N/A ; None ; 7.323 ns ; extrapolar_i ; nabla2fx[0][7] ; clk_i ;
|
416 |
|
|
; N/A ; None ; 7.229 ns ; extrapolar_i ; nabla1fx[0][12] ; clk_i ;
|
417 |
|
|
; N/A ; None ; 7.154 ns ; extrapolar_i ; nabla1fx[0][13] ; clk_i ;
|
418 |
|
|
; N/A ; None ; 7.056 ns ; extrapolar_i ; nabla3fx[0][0] ; clk_i ;
|
419 |
|
|
; N/A ; None ; 7.023 ns ; extrapolar_i ; fxx2_o[6]~reg0 ; clk_i ;
|
420 |
|
|
; N/A ; None ; 6.946 ns ; extrapolar_i ; nabla1fx[0][8] ; clk_i ;
|
421 |
|
|
; N/A ; None ; 6.911 ns ; extrapolar_i ; fxx1_o[6]~reg0 ; clk_i ;
|
422 |
|
|
; N/A ; None ; 6.908 ns ; extrapolar_i ; nabla3fx[0][5] ; clk_i ;
|
423 |
|
|
; N/A ; None ; 6.870 ns ; extrapolar_i ; fxx2_o[3]~reg0 ; clk_i ;
|
424 |
|
|
; N/A ; None ; 6.859 ns ; extrapolar_i ; fxx3_o[4]~reg0 ; clk_i ;
|
425 |
|
|
; N/A ; None ; 6.818 ns ; extrapolar_i ; nabla3fx[0][3] ; clk_i ;
|
426 |
|
|
; N/A ; None ; 6.777 ns ; extrapolar_i ; nabla3fx[0][2] ; clk_i ;
|
427 |
|
|
; N/A ; None ; 6.716 ns ; extrapolar_i ; fxx1_o[15]~reg0 ; clk_i ;
|
428 |
|
|
; N/A ; None ; 6.710 ns ; extrapolar_i ; nabla3fx[0][1] ; clk_i ;
|
429 |
|
|
; N/A ; None ; 6.675 ns ; extrapolar_i ; nabla1fx[0][14] ; clk_i ;
|
430 |
|
|
; N/A ; None ; 6.634 ns ; extrapolar_i ; fxx1_o[13]~reg0 ; clk_i ;
|
431 |
|
|
; N/A ; None ; 6.619 ns ; extrapolar_i ; fxx3_o[0]~reg0 ; clk_i ;
|
432 |
|
|
; N/A ; None ; 6.593 ns ; extrapolar_i ; fxx1_o[12]~reg0 ; clk_i ;
|
433 |
|
|
; N/A ; None ; 6.552 ns ; extrapolar_i ; nabla1fx[0][11] ; clk_i ;
|
434 |
|
|
; N/A ; None ; 6.511 ns ; extrapolar_i ; fxx1_o[10]~reg0 ; clk_i ;
|
435 |
|
|
; N/A ; None ; 6.470 ns ; extrapolar_i ; nabla1fx[0][9] ; clk_i ;
|
436 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[0]~reg0 ; clk_i ;
|
437 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[1]~reg0 ; clk_i ;
|
438 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[2]~reg0 ; clk_i ;
|
439 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[3]~reg0 ; clk_i ;
|
440 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[4]~reg0 ; clk_i ;
|
441 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[5]~reg0 ; clk_i ;
|
442 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[6]~reg0 ; clk_i ;
|
443 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[8]~reg0 ; clk_i ;
|
444 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[13]~reg0 ; clk_i ;
|
445 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[14]~reg0 ; clk_i ;
|
446 |
|
|
; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[15]~reg0 ; clk_i ;
|
447 |
|
|
; N/A ; None ; 6.429 ns ; extrapolar_i ; fxx1_o[8]~reg0 ; clk_i ;
|
448 |
|
|
; N/A ; None ; 6.376 ns ; extrapolar_i ; nabla2fx[0][0] ; clk_i ;
|
449 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[0]~reg0 ; clk_i ;
|
450 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[1]~reg0 ; clk_i ;
|
451 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[2]~reg0 ; clk_i ;
|
452 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[3]~reg0 ; clk_i ;
|
453 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[4]~reg0 ; clk_i ;
|
454 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[5]~reg0 ; clk_i ;
|
455 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[6]~reg0 ; clk_i ;
|
456 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[8]~reg0 ; clk_i ;
|
457 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[13]~reg0 ; clk_i ;
|
458 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[14]~reg0 ; clk_i ;
|
459 |
|
|
; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[15]~reg0 ; clk_i ;
|
460 |
|
|
; N/A ; None ; 6.275 ns ; extrapolar_i ; fxx1_o[2]~reg0 ; clk_i ;
|
461 |
|
|
; N/A ; None ; 6.272 ns ; extrapolar_i ; nabla2fx[0][5] ; clk_i ;
|
462 |
|
|
; N/A ; None ; 6.218 ns ; extrapolar_i ; fxx1_o[7]~reg0 ; clk_i ;
|
463 |
|
|
; N/A ; None ; 6.151 ns ; extrapolar_i ; nabla1fx[0][6] ; clk_i ;
|
464 |
|
|
; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[7]~reg0 ; clk_i ;
|
465 |
|
|
; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[9]~reg0 ; clk_i ;
|
466 |
|
|
; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[10]~reg0 ; clk_i ;
|
467 |
|
|
; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[11]~reg0 ; clk_i ;
|
468 |
|
|
; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[12]~reg0 ; clk_i ;
|
469 |
|
|
; N/A ; None ; 6.113 ns ; extrapolar_i ; nabla2fx[0][4] ; clk_i ;
|
470 |
|
|
; N/A ; None ; 6.092 ns ; extrapolar_i ; nabla2fx[0][2] ; clk_i ;
|
471 |
|
|
; N/A ; None ; 6.075 ns ; extrapolar_i ; fxx1_o[1]~reg0 ; clk_i ;
|
472 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[3] ; clk_i ;
|
473 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[2] ; clk_i ;
|
474 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[7] ; clk_i ;
|
475 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[6] ; clk_i ;
|
476 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[1] ; clk_i ;
|
477 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[0] ; clk_i ;
|
478 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[4] ; clk_i ;
|
479 |
|
|
; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[5] ; clk_i ;
|
480 |
|
|
; N/A ; None ; 6.026 ns ; extrapolar_i ; fxx1_o[5]~reg0 ; clk_i ;
|
481 |
|
|
; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[7]~reg0 ; clk_i ;
|
482 |
|
|
; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[9]~reg0 ; clk_i ;
|
483 |
|
|
; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[10]~reg0 ; clk_i ;
|
484 |
|
|
; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[11]~reg0 ; clk_i ;
|
485 |
|
|
; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[12]~reg0 ; clk_i ;
|
486 |
|
|
; N/A ; None ; 5.978 ns ; extrapolar_i ; fx[0][8] ; clk_i ;
|
487 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[0]~reg0 ; clk_i ;
|
488 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[1]~reg0 ; clk_i ;
|
489 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[2]~reg0 ; clk_i ;
|
490 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[3]~reg0 ; clk_i ;
|
491 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[4]~reg0 ; clk_i ;
|
492 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[5]~reg0 ; clk_i ;
|
493 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[6]~reg0 ; clk_i ;
|
494 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[8]~reg0 ; clk_i ;
|
495 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[13]~reg0 ; clk_i ;
|
496 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[14]~reg0 ; clk_i ;
|
497 |
|
|
; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[15]~reg0 ; clk_i ;
|
498 |
|
|
; N/A ; None ; 5.907 ns ; extrapolar_i ; nabla2fx[0][1] ; clk_i ;
|
499 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[3] ; clk_i ;
|
500 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[2] ; clk_i ;
|
501 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[7] ; clk_i ;
|
502 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[6] ; clk_i ;
|
503 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[1] ; clk_i ;
|
504 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[0] ; clk_i ;
|
505 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[4] ; clk_i ;
|
506 |
|
|
; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[5] ; clk_i ;
|
507 |
|
|
; N/A ; None ; 5.720 ns ; extrapolar_i ; fxx2_o[5]~reg0 ; clk_i ;
|
508 |
|
|
; N/A ; None ; 5.697 ns ; rst_i ; resul_o[0]~reg0 ; clk_i ;
|
509 |
|
|
; N/A ; None ; 5.697 ns ; rst_i ; resul_o[1]~reg0 ; clk_i ;
|
510 |
|
|
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ;
|
511 |
|
|
+-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------+----------+
|
512 |
|
|
|
513 |
|
|
|
514 |
|
|
+---------------------------------------------------------------------------------+
|
515 |
|
|
; tco ;
|
516 |
|
|
+-------+--------------+------------+------------------+-------------+------------+
|
517 |
|
|
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
|
518 |
|
|
+-------+--------------+------------+------------------+-------------+------------+
|
519 |
|
|
; N/A ; None ; 8.310 ns ; fxx3_o[14]~reg0 ; fxx3_o[14] ; clk_i ;
|
520 |
|
|
; N/A ; None ; 8.308 ns ; resul_o[11]~reg0 ; resul_o[11] ; clk_i ;
|
521 |
|
|
; N/A ; None ; 8.281 ns ; fxx3_o[15]~reg0 ; fxx3_o[15] ; clk_i ;
|
522 |
|
|
; N/A ; None ; 8.216 ns ; fxx2_o[14]~reg0 ; fxx2_o[14] ; clk_i ;
|
523 |
|
|
; N/A ; None ; 8.118 ns ; fxx3_o[3]~reg0 ; fxx3_o[3] ; clk_i ;
|
524 |
|
|
; N/A ; None ; 7.959 ns ; fxx3_o[0]~reg0 ; fxx3_o[0] ; clk_i ;
|
525 |
|
|
; N/A ; None ; 7.910 ns ; fxx_o[12]~reg0 ; fxx_o[12] ; clk_i ;
|
526 |
|
|
; N/A ; None ; 7.902 ns ; fxx1_o[1]~reg0 ; fxx1_o[1] ; clk_i ;
|
527 |
|
|
; N/A ; None ; 7.891 ns ; resul_o[7]~reg0 ; resul_o[7] ; clk_i ;
|
528 |
|
|
; N/A ; None ; 7.865 ns ; fxx2_o[7]~reg0 ; fxx2_o[7] ; clk_i ;
|
529 |
|
|
; N/A ; None ; 7.859 ns ; fxx3_o[7]~reg0 ; fxx3_o[7] ; clk_i ;
|
530 |
|
|
; N/A ; None ; 7.853 ns ; fxx1_o[8]~reg0 ; fxx1_o[8] ; clk_i ;
|
531 |
|
|
; N/A ; None ; 7.848 ns ; fxx3_o[5]~reg0 ; fxx3_o[5] ; clk_i ;
|
532 |
|
|
; N/A ; None ; 7.836 ns ; fxx_o[0]~reg0 ; fxx_o[0] ; clk_i ;
|
533 |
|
|
; N/A ; None ; 7.762 ns ; fxx1_o[15]~reg0 ; fxx1_o[15] ; clk_i ;
|
534 |
|
|
; N/A ; None ; 7.757 ns ; fxx1_o[12]~reg0 ; fxx1_o[12] ; clk_i ;
|
535 |
|
|
; N/A ; None ; 7.677 ns ; fxx_o[4]~reg0 ; fxx_o[4] ; clk_i ;
|
536 |
|
|
; N/A ; None ; 7.677 ns ; fxx_o[3]~reg0 ; fxx_o[3] ; clk_i ;
|
537 |
|
|
; N/A ; None ; 7.650 ns ; fxx_o[10]~reg0 ; fxx_o[10] ; clk_i ;
|
538 |
|
|
; N/A ; None ; 7.650 ns ; fxx_o[6]~reg0 ; fxx_o[6] ; clk_i ;
|
539 |
|
|
; N/A ; None ; 7.646 ns ; fxx1_o[2]~reg0 ; fxx1_o[2] ; clk_i ;
|
540 |
|
|
; N/A ; None ; 7.645 ns ; fxx2_o[15]~reg0 ; fxx2_o[15] ; clk_i ;
|
541 |
|
|
; N/A ; None ; 7.612 ns ; fxx2_o[1]~reg0 ; fxx2_o[1] ; clk_i ;
|
542 |
|
|
; N/A ; None ; 7.604 ns ; resul_o[14]~reg0 ; resul_o[14] ; clk_i ;
|
543 |
|
|
; N/A ; None ; 7.589 ns ; fxx_o[1]~reg0 ; fxx_o[1] ; clk_i ;
|
544 |
|
|
; N/A ; None ; 7.588 ns ; fxx3_o[2]~reg0 ; fxx3_o[2] ; clk_i ;
|
545 |
|
|
; N/A ; None ; 7.588 ns ; fxx1_o[0]~reg0 ; fxx1_o[0] ; clk_i ;
|
546 |
|
|
; N/A ; None ; 7.584 ns ; fxx1_o[11]~reg0 ; fxx1_o[11] ; clk_i ;
|
547 |
|
|
; N/A ; None ; 7.581 ns ; fxx1_o[4]~reg0 ; fxx1_o[4] ; clk_i ;
|
548 |
|
|
; N/A ; None ; 7.567 ns ; fxx2_o[6]~reg0 ; fxx2_o[6] ; clk_i ;
|
549 |
|
|
; N/A ; None ; 7.551 ns ; fxx_o[2]~reg0 ; fxx_o[2] ; clk_i ;
|
550 |
|
|
; N/A ; None ; 7.479 ns ; fxx4_o[9]~reg0 ; fxx4_o[9] ; clk_i ;
|
551 |
|
|
; N/A ; None ; 7.473 ns ; fxx4_o[13]~reg0 ; fxx4_o[13] ; clk_i ;
|
552 |
|
|
; N/A ; None ; 7.469 ns ; fxx3_o[12]~reg0 ; fxx3_o[12] ; clk_i ;
|
553 |
|
|
; N/A ; None ; 7.467 ns ; fxx2_o[8]~reg0 ; fxx2_o[8] ; clk_i ;
|
554 |
|
|
; N/A ; None ; 7.435 ns ; fxx4_o[15]~reg0 ; fxx4_o[15] ; clk_i ;
|
555 |
|
|
; N/A ; None ; 7.370 ns ; resul_o[8]~reg0 ; resul_o[8] ; clk_i ;
|
556 |
|
|
; N/A ; None ; 7.340 ns ; fxx3_o[9]~reg0 ; fxx3_o[9] ; clk_i ;
|
557 |
|
|
; N/A ; None ; 7.337 ns ; fxx2_o[2]~reg0 ; fxx2_o[2] ; clk_i ;
|
558 |
|
|
; N/A ; None ; 7.331 ns ; fxx_o[11]~reg0 ; fxx_o[11] ; clk_i ;
|
559 |
|
|
; N/A ; None ; 7.328 ns ; fxx2_o[9]~reg0 ; fxx2_o[9] ; clk_i ;
|
560 |
|
|
; N/A ; None ; 7.279 ns ; fxx1_o[6]~reg0 ; fxx1_o[6] ; clk_i ;
|
561 |
|
|
; N/A ; None ; 7.204 ns ; fxx3_o[11]~reg0 ; fxx3_o[11] ; clk_i ;
|
562 |
|
|
; N/A ; None ; 7.201 ns ; resul_o[6]~reg0 ; resul_o[6] ; clk_i ;
|
563 |
|
|
; N/A ; None ; 7.181 ns ; fxx4_o[14]~reg0 ; fxx4_o[14] ; clk_i ;
|
564 |
|
|
; N/A ; None ; 7.179 ns ; fxx4_o[12]~reg0 ; fxx4_o[12] ; clk_i ;
|
565 |
|
|
; N/A ; None ; 7.154 ns ; fxx4_o[11]~reg0 ; fxx4_o[11] ; clk_i ;
|
566 |
|
|
; N/A ; None ; 7.154 ns ; fxx3_o[8]~reg0 ; fxx3_o[8] ; clk_i ;
|
567 |
|
|
; N/A ; None ; 7.137 ns ; fxx4_o[1]~reg0 ; fxx4_o[1] ; clk_i ;
|
568 |
|
|
; N/A ; None ; 7.135 ns ; fxx_o[5]~reg0 ; fxx_o[5] ; clk_i ;
|
569 |
|
|
; N/A ; None ; 7.114 ns ; fxx2_o[4]~reg0 ; fxx2_o[4] ; clk_i ;
|
570 |
|
|
; N/A ; None ; 7.066 ns ; fxx2_o[3]~reg0 ; fxx2_o[3] ; clk_i ;
|
571 |
|
|
; N/A ; None ; 7.046 ns ; resul_o[15]~reg0 ; resul_o[15] ; clk_i ;
|
572 |
|
|
; N/A ; None ; 7.035 ns ; fxx_o[8]~reg0 ; fxx_o[8] ; clk_i ;
|
573 |
|
|
; N/A ; None ; 7.010 ns ; resul_o[5]~reg0 ; resul_o[5] ; clk_i ;
|
574 |
|
|
; N/A ; None ; 7.004 ns ; fxx3_o[1]~reg0 ; fxx3_o[1] ; clk_i ;
|
575 |
|
|
; N/A ; None ; 7.003 ns ; fxx_o[14]~reg0 ; fxx_o[14] ; clk_i ;
|
576 |
|
|
; N/A ; None ; 6.994 ns ; fxx2_o[0]~reg0 ; fxx2_o[0] ; clk_i ;
|
577 |
|
|
; N/A ; None ; 6.924 ns ; fxx1_o[13]~reg0 ; fxx1_o[13] ; clk_i ;
|
578 |
|
|
; N/A ; None ; 6.921 ns ; fxx1_o[5]~reg0 ; fxx1_o[5] ; clk_i ;
|
579 |
|
|
; N/A ; None ; 6.904 ns ; fxx4_o[4]~reg0 ; fxx4_o[4] ; clk_i ;
|
580 |
|
|
; N/A ; None ; 6.879 ns ; resul_o[4]~reg0 ; resul_o[4] ; clk_i ;
|
581 |
|
|
; N/A ; None ; 6.877 ns ; fxx4_o[7]~reg0 ; fxx4_o[7] ; clk_i ;
|
582 |
|
|
; N/A ; None ; 6.857 ns ; fxx1_o[3]~reg0 ; fxx1_o[3] ; clk_i ;
|
583 |
|
|
; N/A ; None ; 6.835 ns ; fxx_o[7]~reg0 ; fxx_o[7] ; clk_i ;
|
584 |
|
|
; N/A ; None ; 6.753 ns ; resul_o[10]~reg0 ; resul_o[10] ; clk_i ;
|
585 |
|
|
; N/A ; None ; 6.750 ns ; fxx2_o[11]~reg0 ; fxx2_o[11] ; clk_i ;
|
586 |
|
|
; N/A ; None ; 6.736 ns ; fxx4_o[0]~reg0 ; fxx4_o[0] ; clk_i ;
|
587 |
|
|
; N/A ; None ; 6.693 ns ; fxx2_o[5]~reg0 ; fxx2_o[5] ; clk_i ;
|
588 |
|
|
; N/A ; None ; 6.686 ns ; fxx_o[9]~reg0 ; fxx_o[9] ; clk_i ;
|
589 |
|
|
; N/A ; None ; 6.661 ns ; fxx_o[13]~reg0 ; fxx_o[13] ; clk_i ;
|
590 |
|
|
; N/A ; None ; 6.659 ns ; fxx2_o[10]~reg0 ; fxx2_o[10] ; clk_i ;
|
591 |
|
|
; N/A ; None ; 6.647 ns ; fxx4_o[10]~reg0 ; fxx4_o[10] ; clk_i ;
|
592 |
|
|
; N/A ; None ; 6.647 ns ; fxx1_o[14]~reg0 ; fxx1_o[14] ; clk_i ;
|
593 |
|
|
; N/A ; None ; 6.617 ns ; fxx4_o[8]~reg0 ; fxx4_o[8] ; clk_i ;
|
594 |
|
|
; N/A ; None ; 6.561 ns ; fxx3_o[4]~reg0 ; fxx3_o[4] ; clk_i ;
|
595 |
|
|
; N/A ; None ; 6.548 ns ; resul_o[13]~reg0 ; resul_o[13] ; clk_i ;
|
596 |
|
|
; N/A ; None ; 6.541 ns ; resul_o[9]~reg0 ; resul_o[9] ; clk_i ;
|
597 |
|
|
; N/A ; None ; 6.532 ns ; fxx1_o[9]~reg0 ; fxx1_o[9] ; clk_i ;
|
598 |
|
|
; N/A ; None ; 6.504 ns ; fxx4_o[2]~reg0 ; fxx4_o[2] ; clk_i ;
|
599 |
|
|
; N/A ; None ; 6.489 ns ; fxx4_o[6]~reg0 ; fxx4_o[6] ; clk_i ;
|
600 |
|
|
; N/A ; None ; 6.479 ns ; resul_o[12]~reg0 ; resul_o[12] ; clk_i ;
|
601 |
|
|
; N/A ; None ; 6.479 ns ; fxx4_o[3]~reg0 ; fxx4_o[3] ; clk_i ;
|
602 |
|
|
; N/A ; None ; 6.476 ns ; fxx3_o[6]~reg0 ; fxx3_o[6] ; clk_i ;
|
603 |
|
|
; N/A ; None ; 6.456 ns ; resul_o[3]~reg0 ; resul_o[3] ; clk_i ;
|
604 |
|
|
; N/A ; None ; 6.435 ns ; resul_o[2]~reg0 ; resul_o[2] ; clk_i ;
|
605 |
|
|
; N/A ; None ; 6.430 ns ; fxx1_o[7]~reg0 ; fxx1_o[7] ; clk_i ;
|
606 |
|
|
; N/A ; None ; 6.415 ns ; fxx1_o[10]~reg0 ; fxx1_o[10] ; clk_i ;
|
607 |
|
|
; N/A ; None ; 6.407 ns ; fxx_o[15]~reg0 ; fxx_o[15] ; clk_i ;
|
608 |
|
|
; N/A ; None ; 6.346 ns ; resul_o[1]~reg0 ; resul_o[1] ; clk_i ;
|
609 |
|
|
; N/A ; None ; 6.190 ns ; fxx4_o[5]~reg0 ; fxx4_o[5] ; clk_i ;
|
610 |
|
|
; N/A ; None ; 6.183 ns ; fxx2_o[13]~reg0 ; fxx2_o[13] ; clk_i ;
|
611 |
|
|
; N/A ; None ; 6.175 ns ; fxx2_o[12]~reg0 ; fxx2_o[12] ; clk_i ;
|
612 |
|
|
; N/A ; None ; 6.173 ns ; fxx3_o[10]~reg0 ; fxx3_o[10] ; clk_i ;
|
613 |
|
|
; N/A ; None ; 6.161 ns ; resul_o[0]~reg0 ; resul_o[0] ; clk_i ;
|
614 |
|
|
; N/A ; None ; 6.114 ns ; fxx3_o[13]~reg0 ; fxx3_o[13] ; clk_i ;
|
615 |
|
|
+-------+--------------+------------+------------------+-------------+------------+
|
616 |
|
|
|
617 |
|
|
|
618 |
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------+
|
619 |
|
|
; th ;
|
620 |
|
|
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+------------------+----------+
|
621 |
|
|
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
|
622 |
|
|
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+------------------+----------+
|
623 |
|
|
; N/A ; None ; -1.094 ns ; rst_i ; resultado[15] ; clk_i ;
|
624 |
|
|
; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[8]~reg0 ; clk_i ;
|
625 |
|
|
; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[10]~reg0 ; clk_i ;
|
626 |
|
|
; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[12]~reg0 ; clk_i ;
|
627 |
|
|
; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[13]~reg0 ; clk_i ;
|
628 |
|
|
; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[15]~reg0 ; clk_i ;
|
629 |
|
|
; N/A ; None ; -3.585 ns ; extrapolar_i ; fxx_o[2]~reg0 ; clk_i ;
|
630 |
|
|
; N/A ; None ; -3.585 ns ; extrapolar_i ; fxx_o[4]~reg0 ; clk_i ;
|
631 |
|
|
; N/A ; None ; -3.585 ns ; extrapolar_i ; fxx_o[5]~reg0 ; clk_i ;
|
632 |
|
|
; N/A ; None ; -3.926 ns ; extrapolar_i ; nabla1fx[0][5] ; clk_i ;
|
633 |
|
|
; N/A ; None ; -3.926 ns ; extrapolar_i ; nabla1fx[0][6] ; clk_i ;
|
634 |
|
|
; N/A ; None ; -3.926 ns ; extrapolar_i ; fxx1_o[4]~reg0 ; clk_i ;
|
635 |
|
|
; N/A ; None ; -3.926 ns ; extrapolar_i ; fxx1_o[7]~reg0 ; clk_i ;
|
636 |
|
|
; N/A ; None ; -3.929 ns ; extrapolar_i ; nabla1fx[0][2] ; clk_i ;
|
637 |
|
|
; N/A ; None ; -3.929 ns ; extrapolar_i ; fxx1_o[3]~reg0 ; clk_i ;
|
638 |
|
|
; N/A ; None ; -3.930 ns ; extrapolar_i ; nabla1fx[0][1] ; clk_i ;
|
639 |
|
|
; N/A ; None ; -3.930 ns ; extrapolar_i ; fxx1_o[0]~reg0 ; clk_i ;
|
640 |
|
|
; N/A ; None ; -3.986 ns ; extrapolar_i ; fxx_o[3]~reg0 ; clk_i ;
|
641 |
|
|
; N/A ; None ; -4.012 ns ; extrapolar_i ; fxx_o[7]~reg0 ; clk_i ;
|
642 |
|
|
; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[0]~reg0 ; clk_i ;
|
643 |
|
|
; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[1]~reg0 ; clk_i ;
|
644 |
|
|
; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[2]~reg0 ; clk_i ;
|
645 |
|
|
; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[4]~reg0 ; clk_i ;
|
646 |
|
|
; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[5]~reg0 ; clk_i ;
|
647 |
|
|
; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[6]~reg0 ; clk_i ;
|
648 |
|
|
; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[0]~reg0 ; clk_i ;
|
649 |
|
|
; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[3]~reg0 ; clk_i ;
|
650 |
|
|
; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[4]~reg0 ; clk_i ;
|
651 |
|
|
; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[7]~reg0 ; clk_i ;
|
652 |
|
|
; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[6]~reg0 ; clk_i ;
|
653 |
|
|
; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[9]~reg0 ; clk_i ;
|
654 |
|
|
; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[11]~reg0 ; clk_i ;
|
655 |
|
|
; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[14]~reg0 ; clk_i ;
|
656 |
|
|
; N/A ; None ; -4.126 ns ; extrapolar_i ; fxx1_o[8]~reg0 ; clk_i ;
|
657 |
|
|
; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[7]~reg0 ; clk_i ;
|
658 |
|
|
; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[9]~reg0 ; clk_i ;
|
659 |
|
|
; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[10]~reg0 ; clk_i ;
|
660 |
|
|
; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[11]~reg0 ; clk_i ;
|
661 |
|
|
; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[12]~reg0 ; clk_i ;
|
662 |
|
|
; N/A ; None ; -4.161 ns ; rst_i ; fxx2_o[7]~reg0 ; clk_i ;
|
663 |
|
|
; N/A ; None ; -4.161 ns ; rst_i ; fxx2_o[9]~reg0 ; clk_i ;
|
664 |
|
|
; N/A ; None ; -4.161 ns ; rst_i ; fxx2_o[11]~reg0 ; clk_i ;
|
665 |
|
|
; N/A ; None ; -4.167 ns ; extrapolar_i ; nabla1fx[0][9] ; clk_i ;
|
666 |
|
|
; N/A ; None ; -4.197 ns ; extrapolar_i ; fxx_o[12]~reg0 ; clk_i ;
|
667 |
|
|
; N/A ; None ; -4.200 ns ; extrapolar_i ; fxx_o[1]~reg0 ; clk_i ;
|
668 |
|
|
; N/A ; None ; -4.201 ns ; extrapolar_i ; fxx_o[0]~reg0 ; clk_i ;
|
669 |
|
|
; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[8]~reg0 ; clk_i ;
|
670 |
|
|
; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[9]~reg0 ; clk_i ;
|
671 |
|
|
; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[11]~reg0 ; clk_i ;
|
672 |
|
|
; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[13]~reg0 ; clk_i ;
|
673 |
|
|
; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[14]~reg0 ; clk_i ;
|
674 |
|
|
; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[15]~reg0 ; clk_i ;
|
675 |
|
|
; N/A ; None ; -4.208 ns ; extrapolar_i ; fxx1_o[10]~reg0 ; clk_i ;
|
676 |
|
|
; N/A ; None ; -4.249 ns ; extrapolar_i ; nabla1fx[0][11] ; clk_i ;
|
677 |
|
|
; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[10]~reg0 ; clk_i ;
|
678 |
|
|
; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[11]~reg0 ; clk_i ;
|
679 |
|
|
; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[14]~reg0 ; clk_i ;
|
680 |
|
|
; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[15]~reg0 ; clk_i ;
|
681 |
|
|
; N/A ; None ; -4.254 ns ; extrapolar_i ; fxx_o[9]~reg0 ; clk_i ;
|
682 |
|
|
; N/A ; None ; -4.254 ns ; extrapolar_i ; fxx_o[13]~reg0 ; clk_i ;
|
683 |
|
|
; N/A ; None ; -4.290 ns ; extrapolar_i ; fxx1_o[12]~reg0 ; clk_i ;
|
684 |
|
|
; N/A ; None ; -4.331 ns ; extrapolar_i ; fxx1_o[13]~reg0 ; clk_i ;
|
685 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; resultado[14] ; clk_i ;
|
686 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[9]~reg0 ; clk_i ;
|
687 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[10]~reg0 ; clk_i ;
|
688 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[11]~reg0 ; clk_i ;
|
689 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[13]~reg0 ; clk_i ;
|
690 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[14]~reg0 ; clk_i ;
|
691 |
|
|
; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[15]~reg0 ; clk_i ;
|
692 |
|
|
; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[7]~reg0 ; clk_i ;
|
693 |
|
|
; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[9]~reg0 ; clk_i ;
|
694 |
|
|
; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[10]~reg0 ; clk_i ;
|
695 |
|
|
; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[11]~reg0 ; clk_i ;
|
696 |
|
|
; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[12]~reg0 ; clk_i ;
|
697 |
|
|
; N/A ; None ; -4.372 ns ; extrapolar_i ; nabla1fx[0][14] ; clk_i ;
|
698 |
|
|
; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[0]~reg0 ; clk_i ;
|
699 |
|
|
; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[4]~reg0 ; clk_i ;
|
700 |
|
|
; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[5]~reg0 ; clk_i ;
|
701 |
|
|
; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[6]~reg0 ; clk_i ;
|
702 |
|
|
; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[7]~reg0 ; clk_i ;
|
703 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; resultado[2] ; clk_i ;
|
704 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; resultado[3] ; clk_i ;
|
705 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; resultado[4] ; clk_i ;
|
706 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; resultado[5] ; clk_i ;
|
707 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[2]~reg0 ; clk_i ;
|
708 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[3]~reg0 ; clk_i ;
|
709 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[4]~reg0 ; clk_i ;
|
710 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[5]~reg0 ; clk_i ;
|
711 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[0]~reg0 ; clk_i ;
|
712 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[1]~reg0 ; clk_i ;
|
713 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[2]~reg0 ; clk_i ;
|
714 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[3]~reg0 ; clk_i ;
|
715 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[4]~reg0 ; clk_i ;
|
716 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[5]~reg0 ; clk_i ;
|
717 |
|
|
; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[6]~reg0 ; clk_i ;
|
718 |
|
|
; N/A ; None ; -4.392 ns ; extrapolar_i ; cont[0] ; clk_i ;
|
719 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; resultado[0] ; clk_i ;
|
720 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; resultado[1] ; clk_i ;
|
721 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; fxx_o[0]~reg0 ; clk_i ;
|
722 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; fxx_o[1]~reg0 ; clk_i ;
|
723 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; fxx2_o[3]~reg0 ; clk_i ;
|
724 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; fxx3_o[1]~reg0 ; clk_i ;
|
725 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; fxx3_o[2]~reg0 ; clk_i ;
|
726 |
|
|
; N/A ; None ; -4.399 ns ; rst_i ; fxx3_o[3]~reg0 ; clk_i ;
|
727 |
|
|
; N/A ; None ; -4.406 ns ; extrapolar_i ; fx[0][2] ; clk_i ;
|
728 |
|
|
; N/A ; None ; -4.413 ns ; extrapolar_i ; fxx1_o[15]~reg0 ; clk_i ;
|
729 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; resultado[6] ; clk_i ;
|
730 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; resultado[8] ; clk_i ;
|
731 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; resultado[13] ; clk_i ;
|
732 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx_o[6]~reg0 ; clk_i ;
|
733 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx_o[8]~reg0 ; clk_i ;
|
734 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[7]~reg0 ; clk_i ;
|
735 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[8]~reg0 ; clk_i ;
|
736 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[9]~reg0 ; clk_i ;
|
737 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[10]~reg0 ; clk_i ;
|
738 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[11]~reg0 ; clk_i ;
|
739 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[12]~reg0 ; clk_i ;
|
740 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[13]~reg0 ; clk_i ;
|
741 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[14]~reg0 ; clk_i ;
|
742 |
|
|
; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[15]~reg0 ; clk_i ;
|
743 |
|
|
; N/A ; None ; -4.426 ns ; extrapolar_i ; fx[0][5] ; clk_i ;
|
744 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[8]~reg0 ; clk_i ;
|
745 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[10]~reg0 ; clk_i ;
|
746 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[12]~reg0 ; clk_i ;
|
747 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[13]~reg0 ; clk_i ;
|
748 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[14]~reg0 ; clk_i ;
|
749 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[15]~reg0 ; clk_i ;
|
750 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx3_o[10]~reg0 ; clk_i ;
|
751 |
|
|
; N/A ; None ; -4.429 ns ; rst_i ; fxx3_o[12]~reg0 ; clk_i ;
|
752 |
|
|
; N/A ; None ; -4.432 ns ; extrapolar_i ; fx[0][7] ; clk_i ;
|
753 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[0]~reg0 ; clk_i ;
|
754 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[1]~reg0 ; clk_i ;
|
755 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[2]~reg0 ; clk_i ;
|
756 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[3]~reg0 ; clk_i ;
|
757 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[4]~reg0 ; clk_i ;
|
758 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[5]~reg0 ; clk_i ;
|
759 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[6]~reg0 ; clk_i ;
|
760 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[8]~reg0 ; clk_i ;
|
761 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[13]~reg0 ; clk_i ;
|
762 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[14]~reg0 ; clk_i ;
|
763 |
|
|
; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[15]~reg0 ; clk_i ;
|
764 |
|
|
; N/A ; None ; -4.443 ns ; extrapolar_i ; fx[0][4] ; clk_i ;
|
765 |
|
|
; N/A ; None ; -4.444 ns ; extrapolar_i ; nabla1fx[0][0] ; clk_i ;
|
766 |
|
|
; N/A ; None ; -4.448 ns ; extrapolar_i ; cont[1] ; clk_i ;
|
767 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[3] ; clk_i ;
|
768 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[2] ; clk_i ;
|
769 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[7] ; clk_i ;
|
770 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[6] ; clk_i ;
|
771 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[1] ; clk_i ;
|
772 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[0] ; clk_i ;
|
773 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[4] ; clk_i ;
|
774 |
|
|
; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[5] ; clk_i ;
|
775 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[3] ; clk_i ;
|
776 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[2] ; clk_i ;
|
777 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[7] ; clk_i ;
|
778 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[6] ; clk_i ;
|
779 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[1] ; clk_i ;
|
780 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[0] ; clk_i ;
|
781 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[4] ; clk_i ;
|
782 |
|
|
; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[5] ; clk_i ;
|
783 |
|
|
; N/A ; None ; -4.489 ns ; extrapolar_i ; cont[2] ; clk_i ;
|
784 |
|
|
; N/A ; None ; -4.530 ns ; extrapolar_i ; cont[3] ; clk_i ;
|
785 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[3] ; clk_i ;
|
786 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[2] ; clk_i ;
|
787 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[7] ; clk_i ;
|
788 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[6] ; clk_i ;
|
789 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[1] ; clk_i ;
|
790 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[0] ; clk_i ;
|
791 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[4] ; clk_i ;
|
792 |
|
|
; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[5] ; clk_i ;
|
793 |
|
|
; N/A ; None ; -4.561 ns ; extrapolar_i ; nabla1fx[0][4] ; clk_i ;
|
794 |
|
|
; N/A ; None ; -4.571 ns ; extrapolar_i ; cont[4] ; clk_i ;
|
795 |
|
|
; N/A ; None ; -4.572 ns ; extrapolar_i ; nabla1fx[0][3] ; clk_i ;
|
796 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[3] ; clk_i ;
|
797 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[2] ; clk_i ;
|
798 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[7] ; clk_i ;
|
799 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[6] ; clk_i ;
|
800 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[1] ; clk_i ;
|
801 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[0] ; clk_i ;
|
802 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[4] ; clk_i ;
|
803 |
|
|
; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[5] ; clk_i ;
|
804 |
|
|
; N/A ; None ; -4.612 ns ; extrapolar_i ; cont[5] ; clk_i ;
|
805 |
|
|
; N/A ; None ; -4.631 ns ; rst_i ; resultado[7] ; clk_i ;
|
806 |
|
|
; N/A ; None ; -4.631 ns ; rst_i ; resultado[9] ; clk_i ;
|
807 |
|
|
; N/A ; None ; -4.631 ns ; rst_i ; resultado[10] ; clk_i ;
|
808 |
|
|
; N/A ; None ; -4.631 ns ; rst_i ; resultado[11] ; clk_i ;
|
809 |
|
|
; N/A ; None ; -4.631 ns ; rst_i ; resultado[12] ; clk_i ;
|
810 |
|
|
; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[7]~reg0 ; clk_i ;
|
811 |
|
|
; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[9]~reg0 ; clk_i ;
|
812 |
|
|
; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[10]~reg0 ; clk_i ;
|
813 |
|
|
; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[11]~reg0 ; clk_i ;
|
814 |
|
|
; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[12]~reg0 ; clk_i ;
|
815 |
|
|
; N/A ; None ; -4.643 ns ; extrapolar_i ; nabla1fx[0][8] ; clk_i ;
|
816 |
|
|
; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[7]~reg0 ; clk_i ;
|
817 |
|
|
; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[9]~reg0 ; clk_i ;
|
818 |
|
|
; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[10]~reg0 ; clk_i ;
|
819 |
|
|
; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[11]~reg0 ; clk_i ;
|
820 |
|
|
; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[12]~reg0 ; clk_i ;
|
821 |
|
|
; N/A ; None ; -4.653 ns ; extrapolar_i ; cont[6] ; clk_i ;
|
822 |
|
|
; N/A ; None ; -4.656 ns ; rst_i ; fxx_o[7]~reg0 ; clk_i ;
|
823 |
|
|
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ;
|
824 |
|
|
+-----------------------------------------+-----------------------------------------------------+-----------+----------------+------------------+----------+
|
825 |
|
|
|
826 |
|
|
|
827 |
|
|
+--------------------------+
|
828 |
|
|
; Timing Analyzer Messages ;
|
829 |
|
|
+--------------------------+
|
830 |
|
|
Info: *******************************************************************
|
831 |
|
|
Info: Running Quartus II Classic Timing Analyzer
|
832 |
|
|
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
|
833 |
|
|
Info: Processing started: Tue Aug 14 00:28:12 2012
|
834 |
|
|
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4
|
835 |
|
|
Info: Started post-fitting delay annotation
|
836 |
|
|
Warning: Found 96 output pins without output pin load capacitance assignment
|
837 |
|
|
Info: Pin "fxx_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
838 |
|
|
Info: Pin "fxx_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
839 |
|
|
Info: Pin "fxx_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
840 |
|
|
Info: Pin "fxx_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
841 |
|
|
Info: Pin "fxx_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
842 |
|
|
Info: Pin "fxx_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
843 |
|
|
Info: Pin "fxx_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
844 |
|
|
Info: Pin "fxx_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
845 |
|
|
Info: Pin "fxx_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
846 |
|
|
Info: Pin "fxx_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
847 |
|
|
Info: Pin "fxx_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
848 |
|
|
Info: Pin "fxx_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
849 |
|
|
Info: Pin "fxx_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
850 |
|
|
Info: Pin "fxx_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
851 |
|
|
Info: Pin "fxx_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
852 |
|
|
Info: Pin "fxx_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
853 |
|
|
Info: Pin "fxx1_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
854 |
|
|
Info: Pin "fxx1_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
855 |
|
|
Info: Pin "fxx1_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
856 |
|
|
Info: Pin "fxx1_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
857 |
|
|
Info: Pin "fxx1_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
858 |
|
|
Info: Pin "fxx1_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
859 |
|
|
Info: Pin "fxx1_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
860 |
|
|
Info: Pin "fxx1_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
861 |
|
|
Info: Pin "fxx1_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
862 |
|
|
Info: Pin "fxx1_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
863 |
|
|
Info: Pin "fxx1_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
864 |
|
|
Info: Pin "fxx1_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
865 |
|
|
Info: Pin "fxx1_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
866 |
|
|
Info: Pin "fxx1_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
867 |
|
|
Info: Pin "fxx1_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
868 |
|
|
Info: Pin "fxx1_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
869 |
|
|
Info: Pin "fxx2_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
870 |
|
|
Info: Pin "fxx2_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
871 |
|
|
Info: Pin "fxx2_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
872 |
|
|
Info: Pin "fxx2_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
873 |
|
|
Info: Pin "fxx2_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
874 |
|
|
Info: Pin "fxx2_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
875 |
|
|
Info: Pin "fxx2_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
876 |
|
|
Info: Pin "fxx2_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
877 |
|
|
Info: Pin "fxx2_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
878 |
|
|
Info: Pin "fxx2_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
879 |
|
|
Info: Pin "fxx2_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
880 |
|
|
Info: Pin "fxx2_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
881 |
|
|
Info: Pin "fxx2_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
882 |
|
|
Info: Pin "fxx2_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
883 |
|
|
Info: Pin "fxx2_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
884 |
|
|
Info: Pin "fxx2_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
885 |
|
|
Info: Pin "fxx3_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
886 |
|
|
Info: Pin "fxx3_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
887 |
|
|
Info: Pin "fxx3_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
888 |
|
|
Info: Pin "fxx3_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
889 |
|
|
Info: Pin "fxx3_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
890 |
|
|
Info: Pin "fxx3_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
891 |
|
|
Info: Pin "fxx3_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
892 |
|
|
Info: Pin "fxx3_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
893 |
|
|
Info: Pin "fxx3_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
894 |
|
|
Info: Pin "fxx3_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
895 |
|
|
Info: Pin "fxx3_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
896 |
|
|
Info: Pin "fxx3_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
897 |
|
|
Info: Pin "fxx3_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
898 |
|
|
Info: Pin "fxx3_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
899 |
|
|
Info: Pin "fxx3_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
900 |
|
|
Info: Pin "fxx3_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
901 |
|
|
Info: Pin "fxx4_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
902 |
|
|
Info: Pin "fxx4_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
903 |
|
|
Info: Pin "fxx4_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
904 |
|
|
Info: Pin "fxx4_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
905 |
|
|
Info: Pin "fxx4_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
906 |
|
|
Info: Pin "fxx4_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
907 |
|
|
Info: Pin "fxx4_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
908 |
|
|
Info: Pin "fxx4_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
909 |
|
|
Info: Pin "fxx4_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
910 |
|
|
Info: Pin "fxx4_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
911 |
|
|
Info: Pin "fxx4_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
912 |
|
|
Info: Pin "fxx4_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
913 |
|
|
Info: Pin "fxx4_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
914 |
|
|
Info: Pin "fxx4_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
915 |
|
|
Info: Pin "fxx4_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
916 |
|
|
Info: Pin "fxx4_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
917 |
|
|
Info: Pin "resul_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
918 |
|
|
Info: Pin "resul_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
919 |
|
|
Info: Pin "resul_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
920 |
|
|
Info: Pin "resul_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
921 |
|
|
Info: Pin "resul_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
922 |
|
|
Info: Pin "resul_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
923 |
|
|
Info: Pin "resul_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
924 |
|
|
Info: Pin "resul_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
925 |
|
|
Info: Pin "resul_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
926 |
|
|
Info: Pin "resul_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
927 |
|
|
Info: Pin "resul_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
928 |
|
|
Info: Pin "resul_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
929 |
|
|
Info: Pin "resul_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
930 |
|
|
Info: Pin "resul_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
931 |
|
|
Info: Pin "resul_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
932 |
|
|
Info: Pin "resul_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
933 |
|
|
Info: Delay annotation completed successfully
|
934 |
|
|
Warning: Found pins functioning as undefined clocks and/or memory enables
|
935 |
|
|
Info: Assuming node "clk_i" is an undefined clock
|
936 |
|
|
Info: Clock "clk_i" has Internal fmax of 46.88 MHz between source memory "altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0" and destination register "resultado[15]" (period= 21.332 ns)
|
937 |
|
|
Info: + Longest memory to register delay is 10.577 ns
|
938 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0'
|
939 |
|
|
Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7'
|
940 |
|
|
Info: 3: + IC(0.866 ns) + CELL(0.060 ns) = 2.987 ns; Loc. = LCCOMB_X27_Y5_N22; Fanout = 2; COMB Node = 'fx~23'
|
941 |
|
|
Info: 4: + IC(0.874 ns) + CELL(0.426 ns) = 4.287 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37'
|
942 |
|
|
Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 5.384 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33'
|
943 |
|
|
Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 6.628 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38'
|
944 |
|
|
Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 6.669 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42'
|
945 |
|
|
Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 6.710 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46'
|
946 |
|
|
Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 6.751 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50'
|
947 |
|
|
Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 6.895 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53'
|
948 |
|
|
Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 8.074 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46'
|
949 |
|
|
Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 8.115 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50'
|
950 |
|
|
Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 8.156 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54'
|
951 |
|
|
Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 8.197 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58'
|
952 |
|
|
Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 8.341 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61'
|
953 |
|
|
Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 9.320 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61'
|
954 |
|
|
Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 10.577 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]'
|
955 |
|
|
Info: Total cell delay = 5.360 ns ( 50.68 % )
|
956 |
|
|
Info: Total interconnect delay = 5.217 ns ( 49.32 % )
|
957 |
|
|
Info: - Smallest clock skew is 0.176 ns
|
958 |
|
|
Info: + Shortest clock path from clock "clk_i" to destination register is 2.830 ns
|
959 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
960 |
|
|
Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'
|
961 |
|
|
Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]'
|
962 |
|
|
Info: Total cell delay = 1.684 ns ( 59.51 % )
|
963 |
|
|
Info: Total interconnect delay = 1.146 ns ( 40.49 % )
|
964 |
|
|
Info: - Longest clock path from clock "clk_i" to source memory is 2.654 ns
|
965 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
966 |
|
|
Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'
|
967 |
|
|
Info: 3: + IC(0.760 ns) + CELL(0.526 ns) = 2.654 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0'
|
968 |
|
|
Info: Total cell delay = 1.500 ns ( 56.52 % )
|
969 |
|
|
Info: Total interconnect delay = 1.154 ns ( 43.48 % )
|
970 |
|
|
Info: + Micro clock to output delay of source is 0.161 ns
|
971 |
|
|
Info: + Micro setup delay of destination is 0.104 ns
|
972 |
|
|
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
|
973 |
|
|
Info: tsu for register "resultado[15]" (data pin = "extrapolar_i", clock pin = "clk_i") is 12.402 ns
|
974 |
|
|
Info: + Longest pin to register delay is 15.128 ns
|
975 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.920 ns) = 0.920 ns; Loc. = PIN_B9; Fanout = 96; PIN Node = 'extrapolar_i'
|
976 |
|
|
Info: 2: + IC(6.261 ns) + CELL(0.435 ns) = 7.616 ns; Loc. = LCCOMB_X23_Y5_N24; Fanout = 2; COMB Node = 'fx~22'
|
977 |
|
|
Info: 3: + IC(0.675 ns) + CELL(0.403 ns) = 8.694 ns; Loc. = LCCOMB_X23_Y8_N28; Fanout = 2; COMB Node = 'Add2~34'
|
978 |
|
|
Info: 4: + IC(0.000 ns) + CELL(0.144 ns) = 8.838 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37'
|
979 |
|
|
Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 9.935 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33'
|
980 |
|
|
Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 11.179 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38'
|
981 |
|
|
Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 11.220 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42'
|
982 |
|
|
Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 11.261 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46'
|
983 |
|
|
Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 11.302 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50'
|
984 |
|
|
Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 11.446 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53'
|
985 |
|
|
Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 12.625 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46'
|
986 |
|
|
Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 12.666 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50'
|
987 |
|
|
Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 12.707 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54'
|
988 |
|
|
Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 12.748 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58'
|
989 |
|
|
Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 12.892 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61'
|
990 |
|
|
Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 13.871 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61'
|
991 |
|
|
Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 15.128 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]'
|
992 |
|
|
Info: Total cell delay = 4.715 ns ( 31.17 % )
|
993 |
|
|
Info: Total interconnect delay = 10.413 ns ( 68.83 % )
|
994 |
|
|
Info: + Micro setup delay of destination is 0.104 ns
|
995 |
|
|
Info: - Shortest clock path from clock "clk_i" to destination register is 2.830 ns
|
996 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
997 |
|
|
Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'
|
998 |
|
|
Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]'
|
999 |
|
|
Info: Total cell delay = 1.684 ns ( 59.51 % )
|
1000 |
|
|
Info: Total interconnect delay = 1.146 ns ( 40.49 % )
|
1001 |
|
|
Info: tco from clock "clk_i" to destination pin "fxx3_o[14]" through register "fxx3_o[14]~reg0" is 8.310 ns
|
1002 |
|
|
Info: + Longest clock path from clock "clk_i" to source register is 2.842 ns
|
1003 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
1004 |
|
|
Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'
|
1005 |
|
|
Info: 3: + IC(0.764 ns) + CELL(0.710 ns) = 2.842 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o[14]~reg0'
|
1006 |
|
|
Info: Total cell delay = 1.684 ns ( 59.25 % )
|
1007 |
|
|
Info: Total interconnect delay = 1.158 ns ( 40.75 % )
|
1008 |
|
|
Info: + Micro clock to output delay of source is 0.109 ns
|
1009 |
|
|
Info: + Longest register to pin delay is 5.359 ns
|
1010 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o[14]~reg0'
|
1011 |
|
|
Info: 2: + IC(2.924 ns) + CELL(2.435 ns) = 5.359 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'fxx3_o[14]'
|
1012 |
|
|
Info: Total cell delay = 2.435 ns ( 45.44 % )
|
1013 |
|
|
Info: Total interconnect delay = 2.924 ns ( 54.56 % )
|
1014 |
|
|
Info: th for register "resultado[15]" (data pin = "rst_i", clock pin = "clk_i") is -1.094 ns
|
1015 |
|
|
Info: + Longest clock path from clock "clk_i" to destination register is 2.830 ns
|
1016 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
1017 |
|
|
Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'
|
1018 |
|
|
Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]'
|
1019 |
|
|
Info: Total cell delay = 1.684 ns ( 59.51 % )
|
1020 |
|
|
Info: Total interconnect delay = 1.146 ns ( 40.49 % )
|
1021 |
|
|
Info: + Micro hold delay of destination is 0.172 ns
|
1022 |
|
|
Info: - Shortest pin to register delay is 4.096 ns
|
1023 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_M21; Fanout = 98; PIN Node = 'rst_i'
|
1024 |
|
|
Info: 2: + IC(2.254 ns) + CELL(0.858 ns) = 4.096 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]'
|
1025 |
|
|
Info: Total cell delay = 1.842 ns ( 44.97 % )
|
1026 |
|
|
Info: Total interconnect delay = 2.254 ns ( 55.03 % )
|
1027 |
|
|
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
|
1028 |
|
|
Info: Peak virtual memory: 153 megabytes
|
1029 |
|
|
Info: Processing ended: Tue Aug 14 00:28:18 2012
|
1030 |
|
|
Info: Elapsed time: 00:00:06
|
1031 |
|
|
Info: Total CPU time (on all processors): 00:00:06
|
1032 |
|
|
|
1033 |
|
|
|