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guangxi.li |
//------------------------------------------------------------------------------
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//
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// gng.v
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//
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// This file is part of the Gaussian Noise Generator IP Core
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//
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// Description
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// Top module of Gaussian noise generator.
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//
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//------------------------------------------------------------------------------
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//
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// Copyright (C) 2014, Guangxi Liu <guangxi.liu@opencores.org>
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation; either version 2.1 of the License,
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// or (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, download it from
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// http://www.opencores.org/lgpl.shtml
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//
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//------------------------------------------------------------------------------
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`timescale 1 ns / 1 ps
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module gng #(
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parameter INIT_Z1 = 64'd5030521883283424767,
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parameter INIT_Z2 = 64'd18445829279364155008,
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parameter INIT_Z3 = 64'd18436106298727503359
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)
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(
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// System signals
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input clk, // system clock
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input rstn, // system synchronous reset, active low
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// Data interface
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input ce, // clock enable
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output valid_out, // output data valid
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output [15:0] data_out // output data, s<16,11>
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);
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// Local variables
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wire valid_out_ctg;
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wire [63:0] data_out_ctg;
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// Instances
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gng_ctg #(
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.INIT_Z1(INIT_Z1),
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.INIT_Z2(INIT_Z2),
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.INIT_Z3(INIT_Z3)
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) u_gng_ctg (
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.clk(clk),
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.rstn(rstn),
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.ce(ce),
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.valid_out(valid_out_ctg),
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.data_out(data_out_ctg)
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);
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gng_interp u_gng_interp (
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.clk(clk),
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.rstn(rstn),
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.valid_in(valid_out_ctg),
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.data_in(data_out_ctg),
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.valid_out(valid_out),
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.data_out(data_out)
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);
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endmodule
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