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[/] [gng/] [trunk/] [rtl/] [gng_smul_16_18_sadd_37.v] - Blame information for rev 2

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1 2 guangxi.li
//------------------------------------------------------------------------------
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//
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// gng_smul_16_18_sadd_37.v
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//
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// This file is part of the Gaussian Noise Generator IP Core
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//
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// Description
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//     Signed multiplier 16-bit x 18-bit follows signed adder 37-bit,
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// delay 3 cyclesĄŁ
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//
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//------------------------------------------------------------------------------
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//
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// Copyright (C) 2014, Guangxi Liu <guangxi.liu@opencores.org>
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation; either version 2.1 of the License,
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// or (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, download it from
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// http://www.opencores.org/lgpl.shtml
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//
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//------------------------------------------------------------------------------
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`timescale 1 ns / 1 ps
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module gng_smul_16_18_sadd_37 (
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    // System signals
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    input clk,                  // system clock
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    // Data interface
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    input [15:0] a,             // multiplicand
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    input [17:0] b,             // multiplicator
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    input [36:0] c,             // adder
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    output [37:0] p             // result
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);
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// Behavioral model
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reg signed [15:0] a_reg;
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reg signed [17:0] b_reg;
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reg signed [36:0] c_reg;
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reg signed [33:0] prod;
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wire signed [37:0] sum;
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reg [37:0] result;
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always @ (posedge clk) begin
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    a_reg <= a;
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    b_reg <= b;
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    c_reg <= c;
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end
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always @ (posedge clk) begin
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    prod <= a_reg * b_reg;
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end
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assign sum = c_reg + prod;
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always @ (posedge clk) begin
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    result <= sum;
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end
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assign p = result;
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endmodule

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