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1 2 guangxi.li
//------------------------------------------------------------------------------
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//
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// tb_gng.sv
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//
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// This file is part of the Gaussian Noise Generator IP Core
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//
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// Description
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//     Systemverilog testbench for module gng. Generate noise sequences of
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// length N and output to file.
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//
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//------------------------------------------------------------------------------
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//
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// Copyright (C) 2014, Guangxi Liu 
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation; either version 2.1 of the License,
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// or (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, download it from
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// http://www.opencores.org/lgpl.shtml
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//
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//------------------------------------------------------------------------------
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`timescale 1 ns / 1 ps
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module tb_gng;
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// Parameters
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parameter ClkPeriod = 10.0;
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parameter N = 10000000;
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// Local variables
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logic clk;
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logic rstn;
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logic ce;
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logic valid_out;
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logic [15:0] data_out;
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// Instances
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gng #(
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   .INIT_Z1(64'd5030521883283424767),
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   .INIT_Z2(64'd18445829279364155008),
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   .INIT_Z3(64'd18436106298727503359)
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)
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u_gng (.*);
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// System signals
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initial begin
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    clk <= 1'b0;
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    forever #(ClkPeriod/2) clk = ~clk;
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end
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initial begin
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    rstn <= 1'b0;
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    #(ClkPeriod*2) rstn = 1'b1;
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end
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// Main process
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int fpOut;
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initial begin
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    fpOut = $fopen("gng_data_out.txt", "w");
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    ce = 0;
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    #(ClkPeriod*10)
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    repeat (N) begin
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        @(posedge clk);
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        ce = 1;
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    end
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    @(posedge clk);
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    ce = 0;
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    #(ClkPeriod*20)
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    $fclose(fpOut);
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    $stop;
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end
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// Record data
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always_ff @ (negedge clk) begin
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    if (valid_out)
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        $fwrite(fpOut, "%0d\n", $signed(data_out));
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end
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endmodule

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