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https://opencores.org/ocsvn/gost28147/gost28147/trunk
[/] [gost28147/] [trunk/] [sim/] [bin/] [gost28147-89.tcl] - Blame information for rev 2
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doka |
## $Id: gost28147-89.tcl 13 2012-03-22 11:02:55Z Doka $ from Russia with love
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####################################################################
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# This file is part of the GOST 28147-89 CryptoCore project #
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# #
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# Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) #
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####################################################################
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## Run this file with command: cd proj/gost28147/sim/bin; source gost28147-89.tcl
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set name_tb "gost28147-89_tb"
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set timesim 2500ns
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#####################################################
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## path to verilog source code
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set dir_src ../../rtl/verilog
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## path to testbenches dir
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set dir_sim ../../sim/src
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## path to script dir
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set dir_script ../bin
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## path to work dir
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set dir_work ../run
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## set include file dirs
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set dir_inc $dir_src+$dir_sim+../../rtl/tech
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## set project defines
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set DEFINE GOST_R_3411_TESTPARAM
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#####################################################
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quit -sim
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vlib work
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vlog +define+$DEFINE +incdir+$dir_inc -sv $dir_src/gost28147-89.sv
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vlog +define+$DEFINE +incdir+$dir_inc -sv $dir_sim/$name_tb.sv
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vsim -novopt +notimingchecks -wlfdeleteonquit -t 1ns work.tb
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run $timesim
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quit
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