Subversion Repositories gost28147

## $Id: gost28147-89.tcl 13 2012-03-22 11:02:55Z Doka $ from Russia with love

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#    This file is part of the GOST 28147-89 CryptoCore project     #

#                                                                  #

#    Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com)   # 

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##  Run this file with command:   cd proj/gost28147/sim/bin; source gost28147-89.tcl

set name_tb "gost28147-89_tb"

set timesim 2500ns

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## path to verilog source code

set dir_src ../../rtl/verilog

## path to testbenches dir

set dir_sim ../../sim/src

## path to script dir

set dir_script ../bin

## path to work  dir

set dir_work ../run

## set include file dirs

set dir_inc  $dir_src+$dir_sim+../../rtl/tech

## set project defines

set DEFINE GOST_R_3411_TESTPARAM

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quit -sim

vlib work

vlog +define+$DEFINE +incdir+$dir_inc -sv  $dir_src/gost28147-89.sv

vlog +define+$DEFINE +incdir+$dir_inc -sv  $dir_sim/$name_tb.sv

vsim -novopt +notimingchecks -wlfdeleteonquit -t 1ns  work.tb

run $timesim

quit