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Subversion Repositories gost28147

[/] [gost28147/] [trunk/] [syn/] [bin/] [synplify.tcl] - Blame information for rev 2

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# $Id:  $  From Russia with love
# synplify -enable64bit -batch synplify.tcl
 
####################################################################
#    This file is part of the GOST 28147-89 CryptoCore project     #
#                                                                  #
#    Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com)   # 
####################################################################
 
 
######## generic synthesis procedures for Synplif FPGA-Compiler ########
 
 
 
#add_file options
add_file -verilog -vlog_std sysv ../../rtl/verilog/gost28147-89.sv
 
#implementation: "xilinx"
impl -add xilinx -type fpga
 
#device options
set_option -technology  SPARTAN3E
set_option -part        XC3S100E
set_option -package     VQ100
set_option -speed_grade -4
set_option -part_companion ""
 
#compilation/mapping options
set_option -top_module "gost_28147_89"
set_option -vlog_std sysv
set_option -project_relative_includes 1
set_option -enable64bit 1
set_option -hdl_define -set GOST_R_3411_TESTPARAM
set_option -include_path "../../rtl/verilog"
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -compiler_compatible 0
set_option -multi_file_compilation_unit 1
 
 
#map options
set_option -frequency 100.000
#set_option -frequency auto
set_option -vendor_xcompatible_mode 0
set_option -run_prop_extract 1
set_option -fanout_limit 10000
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -retiming 1
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -num_critical_paths 10
set_option -num_startend_points 10
set_option -dup 0
set_option -symbolic_fsm_compiler 1
 
#simulation options
set_option -write_verilog 1
set_option -write_vhdl 0
 
#VIF options
set_option -write_vif 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "../out/gost28147.edf"
 
impl -active "xilinx"
 
run

Line No.	Rev	Author	Line
1	2	doka	`# $Id: $ From Russia with love`
2			`# synplify -enable64bit -batch synplify.tcl`
3
4			`####################################################################`
5			`# This file is part of the GOST 28147-89 CryptoCore project #`
6			`# #`
7			`# Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) #`
8			`####################################################################`
9
10
11			`######## generic synthesis procedures for Synplif FPGA-Compiler ########`
12
13
14
15			`#add_file options`
16			`add_file -verilog -vlog_std sysv ../../rtl/verilog/gost28147-89.sv`
17
18			`#implementation: "xilinx"`
19			`impl -add xilinx -type fpga`
20
21			`#device options`
22			`set_option -technology SPARTAN3E`
23			`set_option -part XC3S100E`
24			`set_option -package VQ100`
25			`set_option -speed_grade -4`
26			`set_option -part_companion ""`
27
28			`#compilation/mapping options`
29			`set_option -top_module "gost_28147_89"`
30			`set_option -vlog_std sysv`
31			`set_option -project_relative_includes 1`
32			`set_option -enable64bit 1`
33			`set_option -hdl_define -set GOST_R_3411_TESTPARAM`
34			`set_option -include_path "../../rtl/verilog"`
35			`set_option -default_enum_encoding default`
36			`set_option -resource_sharing 1`
37			`set_option -use_fsm_explorer 0`
38			`set_option -compiler_compatible 0`
39			`set_option -multi_file_compilation_unit 1`
40
41
42			`#map options`
43			`set_option -frequency 100.000`
44			`#set_option -frequency auto`
45			`set_option -vendor_xcompatible_mode 0`
46			`set_option -run_prop_extract 1`
47			`set_option -fanout_limit 10000`
48			`set_option -disable_io_insertion 1`
49			`set_option -pipe 1`
50			`set_option -update_models_cp 0`
51			`set_option -verification_mode 0`
52			`set_option -retiming 1`
53			`set_option -no_sequential_opt 0`
54			`set_option -fixgatedclocks 3`
55			`set_option -fixgeneratedclocks 3`
56			`set_option -num_critical_paths 10`
57			`set_option -num_startend_points 10`
58			`set_option -dup 0`
59			`set_option -symbolic_fsm_compiler 1`
60
61			`#simulation options`
62			`set_option -write_verilog 1`
63			`set_option -write_vhdl 0`
64
65			`#VIF options`
66			`set_option -write_vif 0`
67
68			`#automatic place and route (vendor) options`
69			`set_option -write_apr_constraint 1`
70
71			`#set result format/file last`
72			`project -result_file "../out/gost28147.edf"`
73
74			`impl -active "xilinx"`
75
76			`run`

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[/] [gost28147/] [trunk/] [syn/] [bin/] [synplify.tcl] - Blame information for rev 2