URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [iseconfig/] [proto1.projectmgr] - Blame information for rev 3

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         /EdgeDetector - arch
         /Fifo8b - arch
         /Fifo8b_Test_vhd - behavior
         /RegsGpibFasade - arch
         /RegsGpibFasade_communication_test - behavior
         /Uart - arch
         /gpibInterface - Behavioral
         /main - Behavioral
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/ev - EventReg - arch
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/gpib - gpibInterface - Behavioral
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/ig - InterruptGenerator - arch
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/rc0 - ReaderControlReg0 - arch
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/readerFifo - Fifo8b - arch
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/wc0 - WriterControlReg0 - arch
         /main - Behavioral/gpib0 - RegsGpibFasade - arch/writerFifo - Fifo8b - arch
      
      
         gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000000000064ffffffff000000810000000000000002000001040000000100000000000000000000000100000000
      true
      gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)
   
   
      
         Design Utilities/Compile HDL Simulation Libraries
      
      
         Add Existing Source
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
      false
      Add Existing Source
   
   
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000250000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001840000000100000000
      false
      commandDecoder.vhd
   
   
      
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000
      false
      work
   
   
      
         Design Utilities
         Implement Design
         Synthesize - XST
      
      
         Add Existing Source
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
      false
      Add Existing Source
   
   
      
         User Constraints
      
      
         Add Existing Source
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
      false
      Add Existing Source
   
   000000ff00000000000000020000015e0000012a01000000040100000002
   Implementation
   
      
         /Fifo8b_Test_vhd - behavior
         /MemoryBlock_Test_vhd - behavior
         /MemoryBlock_Test_vhd - behavior/uut - MemoryBlock - arch
         /RegMultiplexer_Test_vhd - behavior
         /RegsGpibFasade_communication_test - behavior
         /RegsGpibFasade_test - behavior
         /RegsGpibFasade_test - behavior/uut - RegsGpibFasade - arch
         /gpibInterfaceTest - behavior
         /gpibReaderTest - behavior
         /gpibWriterReaderTest - behavior
         /gpib_DC_Test - behavior
         /gpib_DT_Test - behavior
         /gpib_PP_Test - behavior
         /gpib_RL_Test - behavior
         /gpib_SeriallPoll_Test - behavior
         /gpib_TE_LE_Test - behavior
         /main - Behavioral
         /main - Behavioral/gpib0 - RegsGpibFasade - arch
      
      
         main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/src/main.vhd)
      
      3
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002a0000000020000000000000000000000000000000064ffffffff000000810000000000000002000002a00000000100000000000000000000000100000000
      false
      main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/src/main.vhd)
   
   
      
         Design Utilities
      
      
         Add Existing Source
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
      false
      Add Existing Source
   
   
      
      
         Behavioral Check Syntax
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
      false
      Behavioral Check Syntax
   


Line No.	Rev	Author	Line
1	3	Andrewski
2
3
4
5
6
7
8
9
10			`/EdgeDetector - arch`
11			`/Fifo8b - arch`
12			`/Fifo8b_Test_vhd - behavior`
13			`/RegsGpibFasade - arch`
14			`/RegsGpibFasade_communication_test - behavior`
15			`/Uart - arch`
16			`/gpibInterface - Behavioral`
17			`/main - Behavioral`
18			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/ev - EventReg - arch`
19			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/gpib - gpibInterface - Behavioral`
20			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/ig - InterruptGenerator - arch`
21			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/rc0 - ReaderControlReg0 - arch`
22			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/readerFifo - Fifo8b - arch`
23			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/wc0 - WriterControlReg0 - arch`
24			`/main - Behavioral/gpib0 - RegsGpibFasade - arch/writerFifo - Fifo8b - arch`
25
26
27			`gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)`
28
29			`0`
30			`0`
31			`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000000000064ffffffff000000810000000000000002000001040000000100000000000000000000000100000000`
32			`true`
33			`gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)`
34
35
36
37			`Design Utilities/Compile HDL Simulation Libraries`
38
39
40			`Add Existing Source`
41
42			`0`
43			`0`
44			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`
45			`false`
46			`Add Existing Source`
47
48
49
50
51			`0`
52			`0`
53			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000250000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001840000000100000000`
54			`false`
55			`commandDecoder.vhd`
56
57
58
59			`work`
60
61
62			`0`
63			`0`
64			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000`
65			`false`
66			`work`
67
68
69
70			`Design Utilities`
71			`Implement Design`
72			`Synthesize - XST`
73
74
75			`Add Existing Source`
76
77			`0`
78			`0`
79			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`
80			`false`
81			`Add Existing Source`
82
83
84
85			`User Constraints`
86
87
88			`Add Existing Source`
89
90			`0`
91			`0`
92			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`
93			`false`
94			`Add Existing Source`
95
96			`000000ff00000000000000020000015e0000012a01000000040100000002`
97			`Implementation`
98
99
100			`/Fifo8b_Test_vhd - behavior`
101			`/MemoryBlock_Test_vhd - behavior`
102			`/MemoryBlock_Test_vhd - behavior/uut - MemoryBlock - arch`
103			`/RegMultiplexer_Test_vhd - behavior`
104			`/RegsGpibFasade_communication_test - behavior`
105			`/RegsGpibFasade_test - behavior`
106			`/RegsGpibFasade_test - behavior/uut - RegsGpibFasade - arch`
107			`/gpibInterfaceTest - behavior`
108			`/gpibReaderTest - behavior`
109			`/gpibWriterReaderTest - behavior`
110			`/gpib_DC_Test - behavior`
111			`/gpib_DT_Test - behavior`
112			`/gpib_PP_Test - behavior`
113			`/gpib_RL_Test - behavior`
114			`/gpib_SeriallPoll_Test - behavior`
115			`/gpib_TE_LE_Test - behavior`
116			`/main - Behavioral`
117			`/main - Behavioral/gpib0 - RegsGpibFasade - arch`
118
119
120			`main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/src/main.vhd)`
121
122			`3`
123			`0`
124			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002a0000000020000000000000000000000000000000064ffffffff000000810000000000000002000002a00000000100000000000000000000000100000000`
125			`false`
126			`main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/src/main.vhd)`
127
128
129
130			`Design Utilities`
131
132
133			`Add Existing Source`
134
135			`0`
136			`0`
137			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`
138			`false`
139			`Add Existing Source`
140
141
142
143
144			`Behavioral Check Syntax`
145
146			`0`
147			`0`
148			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`
149			`false`
150			`Behavioral Check Syntax`
151
152

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [iseconfig/] [proto1.projectmgr] - Blame information for rev 3