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[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [pa.fromNetlist.tcl] - Blame information for rev 13

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1 3 Andrewski
 
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# PlanAhead Launch Script for Post-Synthesis floorplanning, created by Project Navigator
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create_project -name proto1 -dir "J:/projekty/elektronika/GPIB/prototype_1/fpga/proto1/planAhead_run_1" -part xc3s200tq144-4
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set_property design_mode GateLvl [get_property srcset [current_run -impl]]
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set_property edif_top_file "J:/projekty/elektronika/GPIB/prototype_1/fpga/proto1/main.ngc" [ get_property srcset [ current_run ] ]
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add_files -norecurse { {J:/projekty/elektronika/GPIB/prototype_1/fpga/proto1} }
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set_param project.paUcfFile  "J:/projekty/elektronika/GPIB/prototype_1/fpga/proto1/src/main.ucf"
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add_files "J:/projekty/elektronika/GPIB/prototype_1/fpga/proto1/src/main.ucf" -fileset [get_property constrset [current_run]]
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open_netlist_design

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