URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [src/] [main.vhd] - Blame information for rev 3

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:17:28 01/24/2012 
-- Design Name: 
-- Module Name:    main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.communication.ALL;
use work.wrapperComponents.ALL;
use work.helperComponents.ALL;
 
 
entity main is
        port(
                --reset : in std_logic;
                clk : in std_logic;
 
                ------ UART ---------
                RX : in std_logic;
                TX : out std_logic;
 
                ------ GPIB ---------
                DI : in std_logic_vector (7 downto 0);
                DO : out std_logic_vector (7 downto 0);
                ATN_in : in std_logic;
                ATN_out : out std_logic;
                DAV_in : in std_logic;
                DAV_out : out std_logic;
                NRFD_in : in std_logic;
                NRFD_out : out std_logic;
                NDAC_in : in std_logic;
                NDAC_out : out std_logic;
                EOI_in : in std_logic;
                EOI_out : out std_logic;
                SRQ_in : in std_logic;
                SRQ_out : out std_logic;
                IFC_in : in std_logic;
                IFC_out : out std_logic;
                REN_in : in std_logic;
                REN_out : out std_logic;
 
                ------ LEDS ---------
                led1 : out std_logic;
                led2 : out std_logic
                ------ DEBUG --------
                ;debug1 : out std_logic
                ;debug2 : out std_logic
        );
end main;
 
architecture Behavioral of main is
 
        constant BUF_LEN_MAX_BIT_NUM : integer := 11;
 
        type UART_REC_STATES is (
                ST_UART_REC_READ_ADDR,
                ST_UART_REC_READ_B1,
                ST_UART_REC_READ_B2,
 
                ST_UART_REC_READ_BURST_W_LEN_B1,
                ST_UART_REC_READ_BURST_W_LEN_B2,
 
                ST_UART_REC_BURST_READ
        );
 
        type UART_TR_STATES is (
                ST_UART_TR_IDLE,
                ST_UART_TR_WAIT_NOT_READY_TO_SEND_1,
                ST_UART_TR_WRITE_B1,
                ST_UART_TR_WAIT_NOT_READY_TO_SEND_2,
                ST_UART_TR_WRITE_B2,
 
                ST_UART_TR_WRITE_BURST,
                ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND,
                ST_UART_TR_WAIT_BURST_READY_TO_SEND
        );
 
        ---------- global -------------
        signal reset : std_logic;
        signal reset_timer : integer range 0 to 50000000;
 
        ---------- UART ---------------
        signal uart_reset, uart_clk, uart_RX, uart_TX, uart_data_out_ready,
                uart_data_in_ready, uart_ready_to_send : std_logic;
        signal uart_data_out, uart_data_in : std_logic_vector(7 downto 0);
 
        ---------- GPIB ------------------------
        signal gpib_reset, gpib_clk : std_logic;
        ---------- GPIB interface signals ------
        signal gpib_DI, gpib_DO : std_logic_vector (7 downto 0);
        signal gpib_output_valid : std_logic;
        signal gpib_ATN_in, gpib_ATN_out, gpib_DAV_in, gpib_DAV_out, gpib_NRFD_in,
                gpib_NRFD_out, gpib_NDAC_in, gpib_NDAC_out, gpib_EOI_in, gpib_EOI_out,
                gpib_SRQ_in, gpib_SRQ_out, gpib_IFC_in, gpib_IFC_out, gpib_REN_in,
                gpib_REN_out : std_logic;
        ---------- registers access -------------
        signal gpib_data_in, gpib_data_out : std_logic_vector(15 downto 0);
        signal gpib_reg_addr : std_logic_vector(14 downto 0);
        signal gpib_strobe_read, gpib_strobe_write : std_logic;
 
        ----------- writer strobe pulse generator
        signal t_in_strobe_write, t_out_strobe_write : std_logic;
        ----------- reader strobe pulse generator
        signal t_in_strobe_read, t_out_strobe_read : std_logic;
 
        ---------- interrupt line ---------------
        signal gpib_interrupt_line : std_logic;
 
        ---------- UART transceiver -------------
        signal uart_rec_state : UART_REC_STATES;
        signal uart_strobe_write_s1, uart_strobe_write_s2 : std_logic;
        signal uart_tr_state : UART_TR_STATES;
 
        signal burstLen : std_logic_vector (BUF_LEN_MAX_BIT_NUM downto 0);
        signal isBurstRead : std_logic;
        signal subscribeBurstRead_1, subscribeBurstRead_2 : std_logic;
        signal currentBurstReadLen : integer range 0 to 2**BUF_LEN_MAX_BIT_NUM;
 
        -- GPIB synchronizer
        signal gSync_clk : std_logic;
        signal gSync_DI : std_logic_vector(7 downto 0);
        signal gSync_DO : std_logic_vector(7 downto 0);
        signal gSync_ATN_in : std_logic;
        signal gSync_ATN_Out : std_logic;
        signal gSync_DAV_in : std_logic;
        signal gSync_DAV_out : std_logic;
        signal gSync_NRFD_in : std_logic;
        signal gSync_NRFD_out : std_logic;
        signal gSync_NDAC_in : std_logic;
        signal gSync_NDAC_out : std_logic;
        signal gSync_EOI_in : std_logic;
        signal gSync_EOI_out : std_logic;
        signal gSync_SRQ_in : std_logic;
        signal gSync_SRQ_out : std_logic;
        signal gSync_IFC_in : std_logic;
        signal gSync_IFC_out : std_logic;
        signal gSync_REN_in : std_logic;
        signal gSync_REN_out : std_logic;
 
begin
 
        -- UART
        uart_reset <= reset;
        uart_clk <= clk;
        uart_RX <= RX;
        TX <= uart_TX;
 
        -- GPIB sync
        gSync_clk <= clk;
        gSync_DI <= DI;
        gSync_ATN_in <= ATN_in;
        gSync_DAV_in <= DAV_in;
        gSync_NRFD_in <= NRFD_in;
        gSync_NDAC_in <= NDAC_in;
        gSync_EOI_in <= EOI_in;
        gSync_SRQ_in <= SRQ_in;
        gSync_IFC_in <= IFC_in;
        gSync_REN_in <= REN_in;
 
 
        -- GPIB
        gpib_reset <= reset;
        gpib_clk <= clk;
        gpib_DI <= not gSync_DO;
        DO <= gpib_DO when gpib_output_valid = '1' else "00000000";
        gpib_ATN_in <= not gSync_ATN_Out;
        ATN_out <= gpib_ATN_out;
        gpib_DAV_in <= not gSync_DAV_out;
        DAV_out <= gpib_DAV_out;
        gpib_NRFD_in <= not gSync_NRFD_out;
        NRFD_out <= gpib_NRFD_out;
        gpib_NDAC_in <= not gSync_NDAC_out;
        NDAC_out <= gpib_NDAC_out;
        gpib_EOI_in <= not gSync_EOI_out;
        EOI_out <= gpib_EOI_out;
        gpib_SRQ_in <= not gSync_SRQ_out;
        SRQ_out <= gpib_SRQ_out;
        gpib_IFC_in <= not gSync_IFC_out;
        IFC_out <= gpib_IFC_out;
        gpib_REN_in <= not gSync_REN_out;
        REN_out <= gpib_REN_out;
 
        -- DEBUG
        --led1 <= reset;
        led2 <= uart_data_out_ready;
        --debug1 <= gpib_output_valid;
 
        ---------- receive from UART -----------
        process (reset, uart_data_out_ready, uart_strobe_write_s2) begin
                if reset = '1' then
                        uart_strobe_write_s1 <= uart_strobe_write_s2;
                        t_in_strobe_write <= '0';
 
                        subscribeBurstRead_1 <= '0';
 
                        uart_rec_state <= ST_UART_REC_READ_ADDR;
                elsif rising_edge(uart_data_out_ready) then
                        case uart_rec_state is
                                when ST_UART_REC_READ_ADDR =>
                                        gpib_reg_addr(14 downto 6) <= "000000000";
                                        gpib_reg_addr(5 downto 0) <= uart_data_out(5 downto 0);
 
                                        if uart_data_out(7) = '1' then
                                                if uart_data_out(6) = '1' then
                                                        isBurstRead <= '1';
                                                        uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
                                                else
                                                        uart_strobe_write_s1 <= not uart_strobe_write_s2;
                                                        uart_rec_state <= ST_UART_REC_READ_ADDR;
                                                end if;
                                        else
                                                if uart_data_out(6) = '1' then
                                                        isBurstRead <= '0';
                                                        uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;
                                                else
                                                        uart_rec_state <= ST_UART_REC_READ_B1;
                                                end if;
                                        end if;
 
                                when ST_UART_REC_READ_B1 =>
                                        gpib_data_in(7 downto 0) <= uart_data_out;
                                        uart_rec_state <= ST_UART_REC_READ_B2;
 
                                when ST_UART_REC_READ_B2 =>
                                        gpib_data_in(15 downto 8) <= uart_data_out;
                                        t_in_strobe_write <= not t_out_strobe_write;
                                        uart_rec_state <= ST_UART_REC_READ_ADDR;
 
                                -- burst length
                                when ST_UART_REC_READ_BURST_W_LEN_B1 =>
                                        burstLen(7 downto 0) <= uart_data_out;
                                        uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B2;
 
                                when ST_UART_REC_READ_BURST_W_LEN_B2 =>
                                        burstLen(11 downto 8) <= uart_data_out(3 downto 0);
                                        if isBurstRead = '1' then
                                                subscribeBurstRead_1 <= not subscribeBurstRead_2;
                                                uart_rec_state <= ST_UART_REC_READ_ADDR;
                                        else
                                                uart_rec_state <= ST_UART_REC_BURST_READ;
                                        end if;
 
                                when ST_UART_REC_BURST_READ =>
                                        gpib_data_in(7 downto 0) <= uart_data_out;
                                        t_in_strobe_write <= not t_out_strobe_write;
                                        burstLen <= burstLen - 1;
 
                                        if burstLen = "000000000001" then
                                                uart_rec_state <= ST_UART_REC_READ_ADDR;
                                        end if;
 
                                when others =>
                                        uart_rec_state <= ST_UART_REC_READ_ADDR;
                        end case;
                end if;
        end process;
 
        ---------- write to UART ---------------------
        process (reset, clk, uart_strobe_write_s1) begin
                if reset = '1' then
                        uart_strobe_write_s2 <= uart_strobe_write_s1;
                        uart_data_in_ready <= '0';
                        t_in_strobe_read <= '0';
 
                        subscribeBurstRead_2 <= '0';
 
                        led1 <= '0';
 
                        uart_tr_state <= ST_UART_TR_IDLE;
                elsif rising_edge(clk) then
                        case uart_tr_state is
                                when ST_UART_TR_IDLE =>
                                        if uart_strobe_write_s2 /= uart_strobe_write_s1 and
                                                        uart_ready_to_send = '1' then
                                                uart_strobe_write_s2 <= uart_strobe_write_s1;
                                                uart_data_in <= gpib_data_out(7 downto 0);
                                                uart_data_in_ready <= '1';
                                                uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_1;
                                        elsif subscribeBurstRead_1 /= subscribeBurstRead_2 and
                                                        uart_ready_to_send = '1' then
                                                subscribeBurstRead_2 <= subscribeBurstRead_1;
                                                currentBurstReadLen <= conv_integer(UNSIGNED(burstLen));
 
                                                uart_tr_state <= ST_UART_TR_WRITE_BURST;
                                        end if;
 
                                when ST_UART_TR_WAIT_NOT_READY_TO_SEND_1 =>
                                        if uart_ready_to_send = '0' then
                                                uart_data_in_ready <= '0';
                                                uart_tr_state <= ST_UART_TR_WRITE_B1;
                                        end if;
 
                                when ST_UART_TR_WRITE_B1 =>
                                        if uart_ready_to_send = '1' then
                                                uart_data_in <= gpib_data_out(15 downto 8);
                                                uart_data_in_ready <= '1';
                                                uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_2;
                                        end if;
 
                                when ST_UART_TR_WAIT_NOT_READY_TO_SEND_2 =>
                                        if uart_ready_to_send = '0' then
                                                uart_data_in_ready <= '0';
                                                uart_tr_state <= ST_UART_TR_WRITE_B2;
                                        end if;
 
                                when ST_UART_TR_WRITE_B2 =>
                                        if uart_ready_to_send = '1' then
                                                t_in_strobe_read <= not t_out_strobe_read;
 
                                                uart_tr_state <= ST_UART_TR_IDLE;
                                        end if;
 
                                -- burst read
                                when ST_UART_TR_WRITE_BURST =>
                                        if uart_ready_to_send = '1' then
                                                uart_data_in <= gpib_data_out(7 downto 0);
                                                uart_data_in_ready <= '1';
                                                currentBurstReadLen <= currentBurstReadLen - 1;
 
                                                led1 <= '1';
 
                                                uart_tr_state <= ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND;
                                        end if;
 
                                when ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND =>
                                        if uart_ready_to_send = '0' then
                                                uart_data_in_ready <= '0';
                                                t_in_strobe_read <= not t_out_strobe_read;
 
                                                uart_tr_state <= ST_UART_TR_WAIT_BURST_READY_TO_SEND;
                                        end if;
 
                                when ST_UART_TR_WAIT_BURST_READY_TO_SEND =>
                                        if uart_ready_to_send = '1' then
 
                                                if currentBurstReadLen > 0 then
                                                        uart_tr_state <= ST_UART_TR_WRITE_BURST;
                                                else
                                                        led1 <= '0';
                                                        uart_tr_state <= ST_UART_TR_IDLE;
                                                end if;
                                        end if;
 
 
                                when others =>
                                        uart_tr_state <= ST_UART_TR_IDLE;
                        end case;
                end if;
        end process;
 
        process (clk) begin
                if rising_edge(clk) then
                        if reset_timer < 50000000 then
                                reset_timer <= reset_timer + 1;
                                reset <= '1';
                        else
                                reset <= '0';
                        end if;
                end if;
        end process;
 
        uart0: Uart port map(
                reset => uart_reset, clk => uart_clk, RX => uart_RX, TX => uart_TX,
                data_out => uart_data_out, data_out_ready => uart_data_out_ready,
                data_in => uart_data_in, data_in_ready => uart_data_in_ready,
                ready_to_send => uart_ready_to_send
        );
 
        spg_strobe_write: SinglePulseGenerator generic map (WIDTH => 1) port map(
                reset => reset, clk => clk,
                t_in => t_in_strobe_write, t_out => t_out_strobe_write,
                pulse => gpib_strobe_write
        );
 
        spg_strobe_read: SinglePulseGenerator generic map (WIDTH => 1) port map(
                reset => reset, clk => clk,
                t_in => t_in_strobe_read, t_out => t_out_strobe_read,
                pulse => gpib_strobe_read
        );
 
        gpibSync: GpibSynchronizer port map (
                clk => gSync_clk,
                DI => gSync_DI,
                DO => gSync_DO,
                ATN_in => gSync_ATN_in,
                ATN_out => gSync_ATN_Out,
                DAV_in => gSync_DAV_in,
                DAV_out => gSync_DAV_out,
                NRFD_in => gSync_NRFD_in,
                NRFD_out => gSync_NRFD_out,
                NDAC_in => gSync_NDAC_in,
                NDAC_out => gSync_NDAC_out,
                EOI_in => gSync_EOI_in,
                EOI_out => gSync_EOI_out,
                SRQ_in => gSync_SRQ_in,
                SRQ_out => gSync_SRQ_out,
                IFC_in => gSync_IFC_in,
                IFC_out => gSync_IFC_out,
                REN_in => gSync_REN_in,
                REN_out => gSync_REN_out
        );
 
        gpib0: RegsGpibFasade port map(
                reset => gpib_reset, clk => gpib_clk,
                DI => gpib_DI, DO => gpib_DO, output_valid => gpib_output_valid,
                ATN_in => gpib_ATN_in, ATN_out => gpib_ATN_out,
                DAV_in => gpib_DAV_in, DAV_out => gpib_DAV_out,
                NRFD_in => gpib_NRFD_in, NRFD_out => gpib_NRFD_out,
                NDAC_in => gpib_NDAC_in, NDAC_out => gpib_NDAC_out,
                EOI_in => gpib_EOI_in, EOI_out => gpib_EOI_out,
                SRQ_in => gpib_SRQ_in, SRQ_out => gpib_SRQ_out,
                IFC_in => gpib_IFC_in, IFC_out => gpib_IFC_out,
                REN_in => gpib_REN_in, REN_out => gpib_REN_out,
                data_in => gpib_data_in, data_out => gpib_data_out,
                reg_addr => gpib_reg_addr,
                strobe_read => gpib_strobe_read,
                strobe_write => gpib_strobe_write,
                interrupt_line => gpib_interrupt_line,
                debug1 => debug1, debug2 => debug2
        );
 
end Behavioral;
 

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [src/] [main.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	Andrewski	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 22:17:28 01/24/2012`
6			`-- Design Name:`
7			`-- Module Name: main - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`-- Uncomment the following library declaration if using`
26			`-- arithmetic functions with Signed or Unsigned values`
27			`--use IEEE.NUMERIC_STD.ALL;`
28
29			`-- Uncomment the following library declaration if instantiating`
30			`-- any Xilinx primitives in this code.`
31			`--library UNISIM;`
32			`--use UNISIM.VComponents.all;`
33
34			`use work.communication.ALL;`
35			`use work.wrapperComponents.ALL;`
36			`use work.helperComponents.ALL;`
37
38
39			`entity main is`
40			`port(`
41			`--reset : in std_logic;`
42			`clk : in std_logic;`
43
44			`------ UART ---------`
45			`RX : in std_logic;`
46			`TX : out std_logic;`
47
48			`------ GPIB ---------`
49			`DI : in std_logic_vector (7 downto 0);`
50			`DO : out std_logic_vector (7 downto 0);`
51			`ATN_in : in std_logic;`
52			`ATN_out : out std_logic;`
53			`DAV_in : in std_logic;`
54			`DAV_out : out std_logic;`
55			`NRFD_in : in std_logic;`
56			`NRFD_out : out std_logic;`
57			`NDAC_in : in std_logic;`
58			`NDAC_out : out std_logic;`
59			`EOI_in : in std_logic;`
60			`EOI_out : out std_logic;`
61			`SRQ_in : in std_logic;`
62			`SRQ_out : out std_logic;`
63			`IFC_in : in std_logic;`
64			`IFC_out : out std_logic;`
65			`REN_in : in std_logic;`
66			`REN_out : out std_logic;`
67
68			`------ LEDS ---------`
69			`led1 : out std_logic;`
70			`led2 : out std_logic`
71			`------ DEBUG --------`
72			`;debug1 : out std_logic`
73			`;debug2 : out std_logic`
74			`);`
75			`end main;`
76
77			`architecture Behavioral of main is`
78
79			`constant BUF_LEN_MAX_BIT_NUM : integer := 11;`
80
81			`type UART_REC_STATES is (`
82			`ST_UART_REC_READ_ADDR,`
83			`ST_UART_REC_READ_B1,`
84			`ST_UART_REC_READ_B2,`
85
86			`ST_UART_REC_READ_BURST_W_LEN_B1,`
87			`ST_UART_REC_READ_BURST_W_LEN_B2,`
88
89			`ST_UART_REC_BURST_READ`
90			`);`
91
92			`type UART_TR_STATES is (`
93			`ST_UART_TR_IDLE,`
94			`ST_UART_TR_WAIT_NOT_READY_TO_SEND_1,`
95			`ST_UART_TR_WRITE_B1,`
96			`ST_UART_TR_WAIT_NOT_READY_TO_SEND_2,`
97			`ST_UART_TR_WRITE_B2,`
98
99			`ST_UART_TR_WRITE_BURST,`
100			`ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND,`
101			`ST_UART_TR_WAIT_BURST_READY_TO_SEND`
102			`);`
103
104			`---------- global -------------`
105			`signal reset : std_logic;`
106			`signal reset_timer : integer range 0 to 50000000;`
107
108			`---------- UART ---------------`
109			`signal uart_reset, uart_clk, uart_RX, uart_TX, uart_data_out_ready,`
110			`uart_data_in_ready, uart_ready_to_send : std_logic;`
111			`signal uart_data_out, uart_data_in : std_logic_vector(7 downto 0);`
112
113			`---------- GPIB ------------------------`
114			`signal gpib_reset, gpib_clk : std_logic;`
115			`---------- GPIB interface signals ------`
116			`signal gpib_DI, gpib_DO : std_logic_vector (7 downto 0);`
117			`signal gpib_output_valid : std_logic;`
118			`signal gpib_ATN_in, gpib_ATN_out, gpib_DAV_in, gpib_DAV_out, gpib_NRFD_in,`
119			`gpib_NRFD_out, gpib_NDAC_in, gpib_NDAC_out, gpib_EOI_in, gpib_EOI_out,`
120			`gpib_SRQ_in, gpib_SRQ_out, gpib_IFC_in, gpib_IFC_out, gpib_REN_in,`
121			`gpib_REN_out : std_logic;`
122			`---------- registers access -------------`
123			`signal gpib_data_in, gpib_data_out : std_logic_vector(15 downto 0);`
124			`signal gpib_reg_addr : std_logic_vector(14 downto 0);`
125			`signal gpib_strobe_read, gpib_strobe_write : std_logic;`
126
127			`----------- writer strobe pulse generator`
128			`signal t_in_strobe_write, t_out_strobe_write : std_logic;`
129			`----------- reader strobe pulse generator`
130			`signal t_in_strobe_read, t_out_strobe_read : std_logic;`
131
132			`---------- interrupt line ---------------`
133			`signal gpib_interrupt_line : std_logic;`
134
135			`---------- UART transceiver -------------`
136			`signal uart_rec_state : UART_REC_STATES;`
137			`signal uart_strobe_write_s1, uart_strobe_write_s2 : std_logic;`
138			`signal uart_tr_state : UART_TR_STATES;`
139
140			`signal burstLen : std_logic_vector (BUF_LEN_MAX_BIT_NUM downto 0);`
141			`signal isBurstRead : std_logic;`
142			`signal subscribeBurstRead_1, subscribeBurstRead_2 : std_logic;`
143			`signal currentBurstReadLen : integer range 0 to 2**BUF_LEN_MAX_BIT_NUM;`
144
145			`-- GPIB synchronizer`
146			`signal gSync_clk : std_logic;`
147			`signal gSync_DI : std_logic_vector(7 downto 0);`
148			`signal gSync_DO : std_logic_vector(7 downto 0);`
149			`signal gSync_ATN_in : std_logic;`
150			`signal gSync_ATN_Out : std_logic;`
151			`signal gSync_DAV_in : std_logic;`
152			`signal gSync_DAV_out : std_logic;`
153			`signal gSync_NRFD_in : std_logic;`
154			`signal gSync_NRFD_out : std_logic;`
155			`signal gSync_NDAC_in : std_logic;`
156			`signal gSync_NDAC_out : std_logic;`
157			`signal gSync_EOI_in : std_logic;`
158			`signal gSync_EOI_out : std_logic;`
159			`signal gSync_SRQ_in : std_logic;`
160			`signal gSync_SRQ_out : std_logic;`
161			`signal gSync_IFC_in : std_logic;`
162			`signal gSync_IFC_out : std_logic;`
163			`signal gSync_REN_in : std_logic;`
164			`signal gSync_REN_out : std_logic;`
165
166			`begin`
167
168			`-- UART`
169			`uart_reset <= reset;`
170			`uart_clk <= clk;`
171			`uart_RX <= RX;`
172			`TX <= uart_TX;`
173
174			`-- GPIB sync`
175			`gSync_clk <= clk;`
176			`gSync_DI <= DI;`
177			`gSync_ATN_in <= ATN_in;`
178			`gSync_DAV_in <= DAV_in;`
179			`gSync_NRFD_in <= NRFD_in;`
180			`gSync_NDAC_in <= NDAC_in;`
181			`gSync_EOI_in <= EOI_in;`
182			`gSync_SRQ_in <= SRQ_in;`
183			`gSync_IFC_in <= IFC_in;`
184			`gSync_REN_in <= REN_in;`
185
186
187			`-- GPIB`
188			`gpib_reset <= reset;`
189			`gpib_clk <= clk;`
190			`gpib_DI <= not gSync_DO;`
191			`DO <= gpib_DO when gpib_output_valid = '1' else "00000000";`
192			`gpib_ATN_in <= not gSync_ATN_Out;`
193			`ATN_out <= gpib_ATN_out;`
194			`gpib_DAV_in <= not gSync_DAV_out;`
195			`DAV_out <= gpib_DAV_out;`
196			`gpib_NRFD_in <= not gSync_NRFD_out;`
197			`NRFD_out <= gpib_NRFD_out;`
198			`gpib_NDAC_in <= not gSync_NDAC_out;`
199			`NDAC_out <= gpib_NDAC_out;`
200			`gpib_EOI_in <= not gSync_EOI_out;`
201			`EOI_out <= gpib_EOI_out;`
202			`gpib_SRQ_in <= not gSync_SRQ_out;`
203			`SRQ_out <= gpib_SRQ_out;`
204			`gpib_IFC_in <= not gSync_IFC_out;`
205			`IFC_out <= gpib_IFC_out;`
206			`gpib_REN_in <= not gSync_REN_out;`
207			`REN_out <= gpib_REN_out;`
208
209			`-- DEBUG`
210			`--led1 <= reset;`
211			`led2 <= uart_data_out_ready;`
212			`--debug1 <= gpib_output_valid;`
213
214			`---------- receive from UART -----------`
215			`process (reset, uart_data_out_ready, uart_strobe_write_s2) begin`
216			`if reset = '1' then`
217			`uart_strobe_write_s1 <= uart_strobe_write_s2;`
218			`t_in_strobe_write <= '0';`
219
220			`subscribeBurstRead_1 <= '0';`
221
222			`uart_rec_state <= ST_UART_REC_READ_ADDR;`
223			`elsif rising_edge(uart_data_out_ready) then`
224			`case uart_rec_state is`
225			`when ST_UART_REC_READ_ADDR =>`
226			`gpib_reg_addr(14 downto 6) <= "000000000";`
227			`gpib_reg_addr(5 downto 0) <= uart_data_out(5 downto 0);`
228
229			`if uart_data_out(7) = '1' then`
230			`if uart_data_out(6) = '1' then`
231			`isBurstRead <= '1';`
232			`uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;`
233			`else`
234			`uart_strobe_write_s1 <= not uart_strobe_write_s2;`
235			`uart_rec_state <= ST_UART_REC_READ_ADDR;`
236			`end if;`
237			`else`
238			`if uart_data_out(6) = '1' then`
239			`isBurstRead <= '0';`
240			`uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B1;`
241			`else`
242			`uart_rec_state <= ST_UART_REC_READ_B1;`
243			`end if;`
244			`end if;`
245
246			`when ST_UART_REC_READ_B1 =>`
247			`gpib_data_in(7 downto 0) <= uart_data_out;`
248			`uart_rec_state <= ST_UART_REC_READ_B2;`
249
250			`when ST_UART_REC_READ_B2 =>`
251			`gpib_data_in(15 downto 8) <= uart_data_out;`
252			`t_in_strobe_write <= not t_out_strobe_write;`
253			`uart_rec_state <= ST_UART_REC_READ_ADDR;`
254
255			`-- burst length`
256			`when ST_UART_REC_READ_BURST_W_LEN_B1 =>`
257			`burstLen(7 downto 0) <= uart_data_out;`
258			`uart_rec_state <= ST_UART_REC_READ_BURST_W_LEN_B2;`
259
260			`when ST_UART_REC_READ_BURST_W_LEN_B2 =>`
261			`burstLen(11 downto 8) <= uart_data_out(3 downto 0);`
262			`if isBurstRead = '1' then`
263			`subscribeBurstRead_1 <= not subscribeBurstRead_2;`
264			`uart_rec_state <= ST_UART_REC_READ_ADDR;`
265			`else`
266			`uart_rec_state <= ST_UART_REC_BURST_READ;`
267			`end if;`
268
269			`when ST_UART_REC_BURST_READ =>`
270			`gpib_data_in(7 downto 0) <= uart_data_out;`
271			`t_in_strobe_write <= not t_out_strobe_write;`
272			`burstLen <= burstLen - 1;`
273
274			`if burstLen = "000000000001" then`
275			`uart_rec_state <= ST_UART_REC_READ_ADDR;`
276			`end if;`
277
278			`when others =>`
279			`uart_rec_state <= ST_UART_REC_READ_ADDR;`
280			`end case;`
281			`end if;`
282			`end process;`
283
284			`---------- write to UART ---------------------`
285			`process (reset, clk, uart_strobe_write_s1) begin`
286			`if reset = '1' then`
287			`uart_strobe_write_s2 <= uart_strobe_write_s1;`
288			`uart_data_in_ready <= '0';`
289			`t_in_strobe_read <= '0';`
290
291			`subscribeBurstRead_2 <= '0';`
292
293			`led1 <= '0';`
294
295			`uart_tr_state <= ST_UART_TR_IDLE;`
296			`elsif rising_edge(clk) then`
297			`case uart_tr_state is`
298			`when ST_UART_TR_IDLE =>`
299			`if uart_strobe_write_s2 /= uart_strobe_write_s1 and`
300			`uart_ready_to_send = '1' then`
301			`uart_strobe_write_s2 <= uart_strobe_write_s1;`
302			`uart_data_in <= gpib_data_out(7 downto 0);`
303			`uart_data_in_ready <= '1';`
304			`uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_1;`
305			`elsif subscribeBurstRead_1 /= subscribeBurstRead_2 and`
306			`uart_ready_to_send = '1' then`
307			`subscribeBurstRead_2 <= subscribeBurstRead_1;`
308			`currentBurstReadLen <= conv_integer(UNSIGNED(burstLen));`
309
310			`uart_tr_state <= ST_UART_TR_WRITE_BURST;`
311			`end if;`
312
313			`when ST_UART_TR_WAIT_NOT_READY_TO_SEND_1 =>`
314			`if uart_ready_to_send = '0' then`
315			`uart_data_in_ready <= '0';`
316			`uart_tr_state <= ST_UART_TR_WRITE_B1;`
317			`end if;`
318
319			`when ST_UART_TR_WRITE_B1 =>`
320			`if uart_ready_to_send = '1' then`
321			`uart_data_in <= gpib_data_out(15 downto 8);`
322			`uart_data_in_ready <= '1';`
323			`uart_tr_state <= ST_UART_TR_WAIT_NOT_READY_TO_SEND_2;`
324			`end if;`
325
326			`when ST_UART_TR_WAIT_NOT_READY_TO_SEND_2 =>`
327			`if uart_ready_to_send = '0' then`
328			`uart_data_in_ready <= '0';`
329			`uart_tr_state <= ST_UART_TR_WRITE_B2;`
330			`end if;`
331
332			`when ST_UART_TR_WRITE_B2 =>`
333			`if uart_ready_to_send = '1' then`
334			`t_in_strobe_read <= not t_out_strobe_read;`
335
336			`uart_tr_state <= ST_UART_TR_IDLE;`
337			`end if;`
338
339			`-- burst read`
340			`when ST_UART_TR_WRITE_BURST =>`
341			`if uart_ready_to_send = '1' then`
342			`uart_data_in <= gpib_data_out(7 downto 0);`
343			`uart_data_in_ready <= '1';`
344			`currentBurstReadLen <= currentBurstReadLen - 1;`
345
346			`led1 <= '1';`
347
348			`uart_tr_state <= ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND;`
349			`end if;`
350
351			`when ST_UART_TR_WAIT_BURST_NOT_READY_TO_SEND =>`
352			`if uart_ready_to_send = '0' then`
353			`uart_data_in_ready <= '0';`
354			`t_in_strobe_read <= not t_out_strobe_read;`
355
356			`uart_tr_state <= ST_UART_TR_WAIT_BURST_READY_TO_SEND;`
357			`end if;`
358
359			`when ST_UART_TR_WAIT_BURST_READY_TO_SEND =>`
360			`if uart_ready_to_send = '1' then`
361
362			`if currentBurstReadLen > 0 then`
363			`uart_tr_state <= ST_UART_TR_WRITE_BURST;`
364			`else`
365			`led1 <= '0';`
366			`uart_tr_state <= ST_UART_TR_IDLE;`
367			`end if;`
368			`end if;`
369
370
371			`when others =>`
372			`uart_tr_state <= ST_UART_TR_IDLE;`
373			`end case;`
374			`end if;`
375			`end process;`
376
377			`process (clk) begin`
378			`if rising_edge(clk) then`
379			`if reset_timer < 50000000 then`
380			`reset_timer <= reset_timer + 1;`
381			`reset <= '1';`
382			`else`
383			`reset <= '0';`
384			`end if;`
385			`end if;`
386			`end process;`
387
388			`uart0: Uart port map(`
389			`reset => uart_reset, clk => uart_clk, RX => uart_RX, TX => uart_TX,`
390			`data_out => uart_data_out, data_out_ready => uart_data_out_ready,`
391			`data_in => uart_data_in, data_in_ready => uart_data_in_ready,`
392			`ready_to_send => uart_ready_to_send`
393			`);`
394
395			`spg_strobe_write: SinglePulseGenerator generic map (WIDTH => 1) port map(`
396			`reset => reset, clk => clk,`
397			`t_in => t_in_strobe_write, t_out => t_out_strobe_write,`
398			`pulse => gpib_strobe_write`
399			`);`
400
401			`spg_strobe_read: SinglePulseGenerator generic map (WIDTH => 1) port map(`
402			`reset => reset, clk => clk,`
403			`t_in => t_in_strobe_read, t_out => t_out_strobe_read,`
404			`pulse => gpib_strobe_read`
405			`);`
406
407			`gpibSync: GpibSynchronizer port map (`
408			`clk => gSync_clk,`
409			`DI => gSync_DI,`
410			`DO => gSync_DO,`
411			`ATN_in => gSync_ATN_in,`
412			`ATN_out => gSync_ATN_Out,`
413			`DAV_in => gSync_DAV_in,`
414			`DAV_out => gSync_DAV_out,`
415			`NRFD_in => gSync_NRFD_in,`
416			`NRFD_out => gSync_NRFD_out,`
417			`NDAC_in => gSync_NDAC_in,`
418			`NDAC_out => gSync_NDAC_out,`
419			`EOI_in => gSync_EOI_in,`
420			`EOI_out => gSync_EOI_out,`
421			`SRQ_in => gSync_SRQ_in,`
422			`SRQ_out => gSync_SRQ_out,`
423			`IFC_in => gSync_IFC_in,`
424			`IFC_out => gSync_IFC_out,`
425			`REN_in => gSync_REN_in,`
426			`REN_out => gSync_REN_out`
427			`);`
428
429			`gpib0: RegsGpibFasade port map(`
430			`reset => gpib_reset, clk => gpib_clk,`
431			`DI => gpib_DI, DO => gpib_DO, output_valid => gpib_output_valid,`
432			`ATN_in => gpib_ATN_in, ATN_out => gpib_ATN_out,`
433			`DAV_in => gpib_DAV_in, DAV_out => gpib_DAV_out,`
434			`NRFD_in => gpib_NRFD_in, NRFD_out => gpib_NRFD_out,`
435			`NDAC_in => gpib_NDAC_in, NDAC_out => gpib_NDAC_out,`
436			`EOI_in => gpib_EOI_in, EOI_out => gpib_EOI_out,`
437			`SRQ_in => gpib_SRQ_in, SRQ_out => gpib_SRQ_out,`
438			`IFC_in => gpib_IFC_in, IFC_out => gpib_IFC_out,`
439			`REN_in => gpib_REN_in, REN_out => gpib_REN_out,`
440			`data_in => gpib_data_in, data_out => gpib_data_out,`
441			`reg_addr => gpib_reg_addr,`
442			`strobe_read => gpib_strobe_read,`
443			`strobe_write => gpib_strobe_write,`
444			`interrupt_line => gpib_interrupt_line,`
445			`debug1 => debug1, debug2 => debug2`
446			`);`
447
448			`end Behavioral;`
449