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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [comm/] [Uart.vhd] - Blame information for rev 3

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--------------------------------------------------------------------------------
-- Entity: Uart
-- Date:2011-11-26  
-- Author: apaluch     
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
entity Uart is
        port (
                reset : in std_logic;
                clk : in std_logic;
                ---------- UART ---------------
                RX : in std_logic;
                TX : out std_logic;
                ---------- gpib ---------------
                data_out : out std_logic_vector(7 downto 0);
                data_out_ready : out std_logic;
                data_in : in std_logic_vector(7 downto 0);
                data_in_ready : in std_logic;
                ready_to_send : out std_logic
        );
end Uart;
 
architecture arch of Uart is
 
        constant BIT_TIME : integer :=
                -- 115200
                --572
                -- 921600
                72
                ;
        constant HALF_BIT_TIME : integer := BIT_TIME / 2;
 
        type RX_STATES is (
                ST_RX_IDLE,
                ST_RX_HALF_START,
                ST_RX_RECEIVE_BITS,
                ST_RX_RECEIVE_STOP_BIT
        );
 
        type TX_STATES is (
                ST_TX_IDLE,
                ST_TX_SEND_BITS,
                ST_TX_SEND_STOP_BIT
        );
 
        signal syncRX : std_logic;
 
        signal rxState : RX_STATES;
        signal lastRx : std_logic;
        signal rxTimeCounter : integer range 0 to BIT_TIME;
        signal rxBitCounter : integer range 0 to 7;
        signal innerBuf : std_logic_vector(6 downto 0);
 
        signal txState : TX_STATES;
        signal lastData_in_ready : std_logic;
        signal txTimeCounter : integer range 0 to BIT_TIME;
        signal txBitCounter : integer range 0 to 8;
 
begin
 
        -- RX synchronizer
        process(clk, RX) begin
                if rising_edge(clk) then
                        syncRX <= RX;
                end if;
        end process;
 
        -- RX
        process(reset, clk, syncRX) begin
                if reset = '1' then
                        rxState <= ST_RX_IDLE;
                        lastRx <= syncRX;
                        data_out_ready <= '0';
                elsif rising_edge(clk) then
 
                        lastRx <= syncRX;
 
                        if rxTimeCounter < BIT_TIME then
                                rxTimeCounter <= rxTimeCounter + 1;
                        end if;
 
                        case rxState is
                                when ST_RX_IDLE =>
                                        if lastRx /= syncRX and syncRX = '0' then
                                                rxTimeCounter <= 1;
                                                rxState <= ST_RX_HALF_START;
                                        end if;
 
                                when ST_RX_HALF_START =>
                                        if rxTimeCounter >= HALF_BIT_TIME then
                                                rxBitCounter <= 0;
                                                rxTimeCounter <= 1;
                                                rxState <= ST_RX_RECEIVE_BITS;
                                        end if;
 
                                when ST_RX_RECEIVE_BITS =>
                                        if rxTimeCounter >= BIT_TIME then
 
                                                if rxBitCounter < 7 then
                                                        innerBuf(rxBitCounter) <= syncRX;
                                                        rxBitCounter <= rxBitCounter + 1;
                                                        rxTimeCounter <= 1;
                                                elsif rxBitCounter = 7 then
                                                        data_out(7) <= syncRX;
                                                        data_out(6 downto 0) <= innerBuf;
                                                        data_out_ready <= '0';
                                                        rxTimeCounter <= 1;
 
                                                        rxState <= ST_RX_RECEIVE_STOP_BIT;
                                                end if;
                                        end if;
 
                                when ST_RX_RECEIVE_STOP_BIT =>
                                        if rxTimeCounter >= BIT_TIME then
                                                data_out_ready <= '1';
 
                                                rxState <= ST_RX_IDLE;
                                        end if;
 
                                when others =>
                                        rxState <= ST_RX_IDLE;
                        end case;
                end if;
        end process;
 
        -- TX
        process(reset, clk, data_in_ready) begin
                if reset = '1' then
                        TX <= '1';
                        ready_to_send <= '1';
                        txState <= ST_TX_IDLE;
                elsif rising_edge(clk) then
 
                        lastData_in_ready <= data_in_ready;
 
                        if txTimeCounter < BIT_TIME then
                                txTimeCounter <= txTimeCounter + 1;
                        end if;
 
                        case txState is
                                when ST_TX_IDLE =>
                                        if lastData_in_ready /= data_in_ready and
                                                        data_in_ready = '1' then
                                                TX <= '0';
                                                txTimeCounter <= 1;
                                                txBitCounter <= 0;
                                                ready_to_send <= '0';
 
                                                txState <= ST_TX_SEND_BITS;
                                        end if;
                                when ST_TX_SEND_BITS =>
                                        if txTimeCounter >= BIT_TIME then
 
                                                if txBitCounter < 8 then
                                                        TX <= data_in(txBitCounter);
                                                        txBitCounter <= txBitCounter + 1;
                                                        txTimeCounter <= 1;
                                                elsif txBitCounter = 8 then
                                                        TX <= '1';
                                                        txTimeCounter <= 1;
 
                                                        txState <= ST_TX_SEND_STOP_BIT;
                                                end if;
                                        end if;
                                when ST_TX_SEND_STOP_BIT =>
                                        if txTimeCounter >= BIT_TIME then
                                                ready_to_send <= '1';
 
                                                txState <= ST_TX_IDLE;
                                        end if;
                                when others =>
                                        txState <= ST_TX_IDLE;
                        end case;
                end if;
        end process;
 
end arch;
 

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2			`-- Entity: Uart`
3			`-- Date:2011-11-26`
4			`-- Author: apaluch`
5			`--`
6			`-- Description ${cursor}`
7			`--------------------------------------------------------------------------------`
8			`library ieee;`
9			`use ieee.std_logic_1164.all;`
10			`use ieee.std_logic_unsigned.all;`
11
12
13			`entity Uart is`
14			`port (`
15			`reset : in std_logic;`
16			`clk : in std_logic;`
17			`---------- UART ---------------`
18			`RX : in std_logic;`
19			`TX : out std_logic;`
20			`---------- gpib ---------------`
21			`data_out : out std_logic_vector(7 downto 0);`
22			`data_out_ready : out std_logic;`
23			`data_in : in std_logic_vector(7 downto 0);`
24			`data_in_ready : in std_logic;`
25			`ready_to_send : out std_logic`
26			`);`
27			`end Uart;`
28
29			`architecture arch of Uart is`
30
31			`constant BIT_TIME : integer :=`
32			`-- 115200`
33			`--572`
34			`-- 921600`
35			`72`
36			`;`
37			`constant HALF_BIT_TIME : integer := BIT_TIME / 2;`
38
39			`type RX_STATES is (`
40			`ST_RX_IDLE,`
41			`ST_RX_HALF_START,`
42			`ST_RX_RECEIVE_BITS,`
43			`ST_RX_RECEIVE_STOP_BIT`
44			`);`
45
46			`type TX_STATES is (`
47			`ST_TX_IDLE,`
48			`ST_TX_SEND_BITS,`
49			`ST_TX_SEND_STOP_BIT`
50			`);`
51
52			`signal syncRX : std_logic;`
53
54			`signal rxState : RX_STATES;`
55			`signal lastRx : std_logic;`
56			`signal rxTimeCounter : integer range 0 to BIT_TIME;`
57			`signal rxBitCounter : integer range 0 to 7;`
58			`signal innerBuf : std_logic_vector(6 downto 0);`
59
60			`signal txState : TX_STATES;`
61			`signal lastData_in_ready : std_logic;`
62			`signal txTimeCounter : integer range 0 to BIT_TIME;`
63			`signal txBitCounter : integer range 0 to 8;`
64
65			`begin`
66
67			`-- RX synchronizer`
68			`process(clk, RX) begin`
69			`if rising_edge(clk) then`
70			`syncRX <= RX;`
71			`end if;`
72			`end process;`
73
74			`-- RX`
75			`process(reset, clk, syncRX) begin`
76			`if reset = '1' then`
77			`rxState <= ST_RX_IDLE;`
78			`lastRx <= syncRX;`
79			`data_out_ready <= '0';`
80			`elsif rising_edge(clk) then`
81
82			`lastRx <= syncRX;`
83
84			`if rxTimeCounter < BIT_TIME then`
85			`rxTimeCounter <= rxTimeCounter + 1;`
86			`end if;`
87
88			`case rxState is`
89			`when ST_RX_IDLE =>`
90			`if lastRx /= syncRX and syncRX = '0' then`
91			`rxTimeCounter <= 1;`
92			`rxState <= ST_RX_HALF_START;`
93			`end if;`
94
95			`when ST_RX_HALF_START =>`
96			`if rxTimeCounter >= HALF_BIT_TIME then`
97			`rxBitCounter <= 0;`
98			`rxTimeCounter <= 1;`
99			`rxState <= ST_RX_RECEIVE_BITS;`
100			`end if;`
101
102			`when ST_RX_RECEIVE_BITS =>`
103			`if rxTimeCounter >= BIT_TIME then`
104
105			`if rxBitCounter < 7 then`
106			`innerBuf(rxBitCounter) <= syncRX;`
107			`rxBitCounter <= rxBitCounter + 1;`
108			`rxTimeCounter <= 1;`
109			`elsif rxBitCounter = 7 then`
110			`data_out(7) <= syncRX;`
111			`data_out(6 downto 0) <= innerBuf;`
112			`data_out_ready <= '0';`
113			`rxTimeCounter <= 1;`
114
115			`rxState <= ST_RX_RECEIVE_STOP_BIT;`
116			`end if;`
117			`end if;`
118
119			`when ST_RX_RECEIVE_STOP_BIT =>`
120			`if rxTimeCounter >= BIT_TIME then`
121			`data_out_ready <= '1';`
122
123			`rxState <= ST_RX_IDLE;`
124			`end if;`
125
126			`when others =>`
127			`rxState <= ST_RX_IDLE;`
128			`end case;`
129			`end if;`
130			`end process;`
131
132			`-- TX`
133			`process(reset, clk, data_in_ready) begin`
134			`if reset = '1' then`
135			`TX <= '1';`
136			`ready_to_send <= '1';`
137			`txState <= ST_TX_IDLE;`
138			`elsif rising_edge(clk) then`
139
140			`lastData_in_ready <= data_in_ready;`
141
142			`if txTimeCounter < BIT_TIME then`
143			`txTimeCounter <= txTimeCounter + 1;`
144			`end if;`
145
146			`case txState is`
147			`when ST_TX_IDLE =>`
148			`if lastData_in_ready /= data_in_ready and`
149			`data_in_ready = '1' then`
150			`TX <= '0';`
151			`txTimeCounter <= 1;`
152			`txBitCounter <= 0;`
153			`ready_to_send <= '0';`
154
155			`txState <= ST_TX_SEND_BITS;`
156			`end if;`
157			`when ST_TX_SEND_BITS =>`
158			`if txTimeCounter >= BIT_TIME then`
159
160			`if txBitCounter < 8 then`
161			`TX <= data_in(txBitCounter);`
162			`txBitCounter <= txBitCounter + 1;`
163			`txTimeCounter <= 1;`
164			`elsif txBitCounter = 8 then`
165			`TX <= '1';`
166			`txTimeCounter <= 1;`
167
168			`txState <= ST_TX_SEND_STOP_BIT;`
169			`end if;`
170			`end if;`
171			`when ST_TX_SEND_STOP_BIT =>`
172			`if txTimeCounter >= BIT_TIME then`
173			`ready_to_send <= '1';`
174
175			`txState <= ST_TX_IDLE;`
176			`end if;`
177			`when others =>`
178			`txState <= ST_TX_IDLE;`
179			`end case;`
180			`end if;`
181			`end process;`
182
183			`end arch;`
184

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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [comm/] [Uart.vhd] - Blame information for rev 3