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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [common/] [wrapperComponents.vhd] - Blame information for rev 13

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--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: wrapperComponents
-- Date:2011-11-17  
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
package wrapperComponents is
 
        component RegsGpibFasade is
                port (
                        reset : std_logic;
                        clk : in std_logic;
                        -----------------------------------------------------------------------
                        ------------ GPIB interface signals -----------------------------------
                        -----------------------------------------------------------------------
                        DI : in std_logic_vector (7 downto 0);
                        DO : out std_logic_vector (7 downto 0);
                        output_valid : out std_logic;
                        -- attention
                        ATN_in : in std_logic;
                        ATN_out : out std_logic;
                        -- data valid
                        DAV_in : in std_logic;
                        DAV_out : out std_logic;
                        -- not ready for data
                        NRFD_in : in std_logic;
                        NRFD_out : out std_logic;
                        -- no data accepted
                        NDAC_in : in std_logic;
                        NDAC_out : out std_logic;
                        -- end or identify
                        EOI_in : in std_logic;
                        EOI_out : out std_logic;
                        -- service request
                        SRQ_in : in std_logic;
                        SRQ_out : out std_logic;
                        -- interface clear
                        IFC_in : in std_logic;
                        IFC_out : out std_logic;
                        -- remote enable
                        REN_in : in std_logic;
                        REN_out : out std_logic;
                        -----------------------------------------------------------------------
                        ---------------- registers access -------------------------------------
                        -----------------------------------------------------------------------
                        data_in : in std_logic_vector(15 downto 0);
                        data_out : out std_logic_vector(15 downto 0);
                        reg_addr : in std_logic_vector(14 downto 0);
                        strobe_read : in std_logic;
                        strobe_write : in std_logic;
                        -----------------------------------------------------------------------
                        ---------------- additional lines -------------------------------------
                        -----------------------------------------------------------------------
                        interrupt_line : out std_logic
                        ;debug1 : out std_logic
                        ;debug2 : out std_logic
                );
        end component;
 
        component InterruptGenerator is
                port (
                        reset : std_logic;
                        clk : in std_logic;
                        interrupt : out std_logic;
                        -------------------- gpib device ---------------------
                        -- device is local controlled
                        isLocal : in std_logic;
                        -- input buffer ready
                        in_buf_ready : in std_logic;
                        -- output buffer ready
                        out_buf_ready : in std_logic;
                        -- clear device (DC)
                        clr : in std_logic;
                        -- trigger device (DT)
                        trg : in std_logic;
                        -- addressed to talk(L or LE)
                        att : in std_logic;
                        -- addressed to listen (T or TE)
                        atl : in std_logic;
                        -- seriall poll active
                        spa : in std_logic;
                        -------------------- gpib controller ---------------------
                        -- controller write commands
                        cwrc : in std_logic;
                        -- controller write data
                        cwrd : in std_logic;
                        -- service requested
                        srq : in std_logic;
                        -- parallel poll ready
                        ppr : in std_logic;
                        -- stb received
                        stb_received : in std_logic;
                        REN : in std_logic;
                        ATN : in std_logic;
                        IFC : in std_logic
                );
        end component;
 
        component RegMultiplexer is
                generic (
                        ADDR_WIDTH : integer := 15
                );
                port (
                        strobe_read : in std_logic;
                        strobe_write : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        --------------------------------------------------------
                        reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);
                        --------------------------------------------------------
                        reg_strobe_0 : out std_logic;
                        reg_in_0 : out std_logic_vector (15 downto 0);
                        reg_out_0 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_1 : out std_logic;
                        reg_in_1 : out std_logic_vector (15 downto 0);
                        reg_out_1 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_2 : out std_logic;
                        reg_in_2 : out std_logic_vector (15 downto 0);
                        reg_out_2 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_3 : out std_logic;
                        reg_in_3 : out std_logic_vector (15 downto 0);
                        reg_out_3 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_4 : out std_logic;
                        reg_in_4 : out std_logic_vector (15 downto 0);
                        reg_out_4 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_5 : out std_logic;
                        reg_in_5 : out std_logic_vector (15 downto 0);
                        reg_out_5 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_6 : out std_logic;
                        reg_in_6 : out std_logic_vector (15 downto 0);
                        reg_out_6 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_7 : out std_logic;
                        reg_in_7 : out std_logic_vector (15 downto 0);
                        reg_out_7 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_8 : out std_logic;
                        reg_in_8 : out std_logic_vector (15 downto 0);
                        reg_out_8 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_9 : out std_logic;
                        reg_in_9 : out std_logic_vector (15 downto 0);
                        reg_out_9 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_10 : out std_logic;
                        reg_in_10 : out std_logic_vector (15 downto 0);
                        reg_out_10 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_11 : out std_logic;
                        reg_in_11 : out std_logic_vector (15 downto 0);
                        reg_out_11 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_other0 : out std_logic;
                        reg_in_other0 : out std_logic_vector (15 downto 0);
                        reg_out_other0 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_other1 : out std_logic;
                        reg_in_other1 : out std_logic_vector (15 downto 0);
                        reg_out_other1 : in std_logic_vector (15 downto 0)
 
                );
        end component;
 
        component EventReg is
                port (
                        reset : in std_logic;
                        clk : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        -------------------- gpib device ---------------------
                        -- device is local controlled
                        isLocal : in std_logic;
                        -- input buffer ready
                        in_buf_ready : in std_logic;
                        -- output buffer ready
                        out_buf_ready : in std_logic;
                        -- clear device (DC)
                        clr : in std_logic;
                        -- trigger device (DT)
                        trg : in std_logic;
                        -- addressed to talk(L or LE)
                        att : in std_logic;
                        -- addressed to listen (T or TE)
                        atl : in std_logic;
                        -- seriall poll active
                        spa : in std_logic;
                        -------------------- gpib controller ---------------------
                        -- controller write commands
                        cwrc : in std_logic;
                        -- controller write data
                        cwrd : in std_logic;
                        -- service requested
                        srq : in std_logic;
                        -- parallel poll ready
                        ppr : in std_logic;
                        -- stb received
                        stb_received : in std_logic;
                        REN : in std_logic;
                        ATN : in std_logic;
                        IFC : in std_logic
                );
        end component;
 
        component gpibBusReg is
                port (
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------------------------------------
                        -- interface signals
                        DIO : in std_logic_vector (7 downto 0);
                        -- attention
                        ATN : in std_logic;
                        -- data valid
                        DAV : in std_logic;
                        -- not ready for data
                        NRFD : in std_logic;
                        -- no data accepted
                        NDAC : in std_logic;
                        -- end or identify
                        EOI : in std_logic;
                        -- service request
                        SRQ : in std_logic;
                        -- interface clear
                        IFC : in std_logic;
                        -- remote enable
                        REN : in std_logic
                );
        end component;
 
        component gpibControlReg is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------ gpib ------------------------
                        ltn : out std_logic; -- listen (L, LE)
                        lun : out std_logic; -- local unlisten (L, LE)
                        rtl : out std_logic; -- return to local (RL)
                        rsv : out std_logic; -- request service (SR)
                        ist : out std_logic; -- individual status (PP)
                        lpe : out std_logic; -- local poll enable (PP)
                        ------------------------------------------------
                        rsc : out std_logic; -- request system control (C)
                        sic : out std_logic; -- send interface clear (C)
                        sre : out std_logic; -- send remote enable (C)
                        gts : out std_logic; -- go to standby (C)
                        tcs : out std_logic; -- take control synchronously (C, AH)
                        tca : out std_logic; -- take control asynchronously (C)
                        rpp : out std_logic; -- request parallel poll (C)
                        rec_stb : out std_logic -- receives status byte (C)
                );
        end component;
 
        component GpibStatusReg is
                port (
                        data_out : out std_logic_vector (15 downto 0);
                        -- gpib
                        currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr
                        att : in std_logic; -- addressed to talk(L or LE)
                        tac : in std_logic; -- talker active (T, TE)
                        atl : in std_logic; -- addressed to listen (T or TE)
                        lac : in std_logic; -- listener active (L, LE)
                        cwrc : in std_logic; -- controller write commands
                        cwrd : in std_logic; -- controller write data
                        spa : in std_logic; -- seriall poll active
                        isLocal : in std_logic -- device is local controlled
                );
        end component;
 
        component ReaderControlReg0 is
                port (
                        clk : in std_logic;
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------- gpib -------------------------
                        -- buffer ready interrupt
                        buf_interrupt : in std_logic;
                        -- at least one byte available
                        data_available : in std_logic;
                        -- indicates end of stream
                        end_of_stream : in std_logic;
                        -- resets buffer
                        reset_buffer : out std_logic;
                        -- secondary address of data
                        dataSecAddr : in std_logic_vector (4 downto 0)
                );
        end component;
 
        component ReaderControlReg1 is
                port (
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------ gpib --------------------
                        -- num of bytes available in fifo
                        bytes_available_in_fifo : in std_logic_vector (10 downto 0)
                );
        end component;
 
        component SecAddrReg is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        -- gpib
                        secAddrMask : out std_logic_vector (15 downto 0)
                );
        end component;
 
        component SettingsReg0 is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------- gpib -----------------------------
                        isLE_TE : out std_logic;
                        lpeUsed : out std_logic;
                        fixedPpLine : out std_logic_vector (2 downto 0);
                        eosUsed : out std_logic;
                        eosMark : out std_logic_vector (7 downto 0);
                        lon : out std_logic;
                        ton : out std_logic
                );
        end component;
 
        component SettingsReg1 is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        -- gpib
                        myAddr : out std_logic_vector (4 downto 0);
                        T1 : out std_logic_vector (7 downto 0)
                );
        end component;
 
        component WriterControlReg0 is
                port (
                        clk : in std_logic;
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------- gpib -------------------------
                        -- buffer consumed
                        buf_interrupt : in std_logic;
                        -- data avilable - at least one byte in buffer
                        data_available : out std_logic;
                        -- indicates end of stream
                        end_of_stream : out std_logic;
                        -- resets buffer
                        reset_buffer : out std_logic;
                        -- secondary address of data
                        dataSecAddr : out std_logic_vector (4 downto 0);
                        -- serial poll status byte
                        status_byte : out std_logic_vector (6 downto 0)
                );
        end component;
 
        component WriterControlReg1 is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------ gpib --------------------
                        -- num of bytes available in fifo
                        bytes_available_in_fifo : in std_logic_vector (10 downto 0)
                );
        end component;
 
end wrapperComponents;
 

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [common/] [wrapperComponents.vhd] - Blame information for rev 13

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2	13	Andrewski	`--This file is part of fpga_gpib_controller.`
3			`--`
4			`-- Fpga_gpib_controller is free software: you can redistribute it and/or modify`
5			`-- it under the terms of the GNU General Public License as published by`
6			`-- the Free Software Foundation, either version 3 of the License, or`
7			`-- (at your option) any later version.`
8			`--`
9			`-- Fpga_gpib_controller is distributed in the hope that it will be useful,`
10			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
12			`-- GNU General Public License for more details.`
13
14			`-- You should have received a copy of the GNU General Public License`
15			`-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.`
16			`--------------------------------------------------------------------------------`
17	3	Andrewski	`-- Entity: wrapperComponents`
18			`-- Date:2011-11-17`
19	13	Andrewski	`-- Author: Andrzej Paluch`
20	3	Andrewski	`--`
21			`-- Description ${cursor}`
22			`--------------------------------------------------------------------------------`
23			`library ieee;`
24			`use ieee.std_logic_1164.all;`
25			`use ieee.std_logic_unsigned.all;`
26
27
28			`package wrapperComponents is`
29
30			`component RegsGpibFasade is`
31			`port (`
32			`reset : std_logic;`
33			`clk : in std_logic;`
34			`-----------------------------------------------------------------------`
35			`------------ GPIB interface signals -----------------------------------`
36			`-----------------------------------------------------------------------`
37			`DI : in std_logic_vector (7 downto 0);`
38			`DO : out std_logic_vector (7 downto 0);`
39			`output_valid : out std_logic;`
40			`-- attention`
41			`ATN_in : in std_logic;`
42			`ATN_out : out std_logic;`
43			`-- data valid`
44			`DAV_in : in std_logic;`
45			`DAV_out : out std_logic;`
46			`-- not ready for data`
47			`NRFD_in : in std_logic;`
48			`NRFD_out : out std_logic;`
49			`-- no data accepted`
50			`NDAC_in : in std_logic;`
51			`NDAC_out : out std_logic;`
52			`-- end or identify`
53			`EOI_in : in std_logic;`
54			`EOI_out : out std_logic;`
55			`-- service request`
56			`SRQ_in : in std_logic;`
57			`SRQ_out : out std_logic;`
58			`-- interface clear`
59			`IFC_in : in std_logic;`
60			`IFC_out : out std_logic;`
61			`-- remote enable`
62			`REN_in : in std_logic;`
63			`REN_out : out std_logic;`
64			`-----------------------------------------------------------------------`
65			`---------------- registers access -------------------------------------`
66			`-----------------------------------------------------------------------`
67			`data_in : in std_logic_vector(15 downto 0);`
68			`data_out : out std_logic_vector(15 downto 0);`
69			`reg_addr : in std_logic_vector(14 downto 0);`
70			`strobe_read : in std_logic;`
71			`strobe_write : in std_logic;`
72			`-----------------------------------------------------------------------`
73			`---------------- additional lines -------------------------------------`
74			`-----------------------------------------------------------------------`
75			`interrupt_line : out std_logic`
76			`;debug1 : out std_logic`
77			`;debug2 : out std_logic`
78			`);`
79			`end component;`
80
81			`component InterruptGenerator is`
82			`port (`
83			`reset : std_logic;`
84			`clk : in std_logic;`
85			`interrupt : out std_logic;`
86			`-------------------- gpib device ---------------------`
87			`-- device is local controlled`
88			`isLocal : in std_logic;`
89			`-- input buffer ready`
90			`in_buf_ready : in std_logic;`
91			`-- output buffer ready`
92			`out_buf_ready : in std_logic;`
93			`-- clear device (DC)`
94			`clr : in std_logic;`
95			`-- trigger device (DT)`
96			`trg : in std_logic;`
97			`-- addressed to talk(L or LE)`
98			`att : in std_logic;`
99			`-- addressed to listen (T or TE)`
100			`atl : in std_logic;`
101			`-- seriall poll active`
102			`spa : in std_logic;`
103			`-------------------- gpib controller ---------------------`
104			`-- controller write commands`
105			`cwrc : in std_logic;`
106			`-- controller write data`
107			`cwrd : in std_logic;`
108			`-- service requested`
109			`srq : in std_logic;`
110			`-- parallel poll ready`
111			`ppr : in std_logic;`
112			`-- stb received`
113			`stb_received : in std_logic;`
114			`REN : in std_logic;`
115			`ATN : in std_logic;`
116			`IFC : in std_logic`
117			`);`
118			`end component;`
119
120			`component RegMultiplexer is`
121			`generic (`
122			`ADDR_WIDTH : integer := 15`
123			`);`
124			`port (`
125			`strobe_read : in std_logic;`
126			`strobe_write : in std_logic;`
127			`data_in : in std_logic_vector (15 downto 0);`
128			`data_out : out std_logic_vector (15 downto 0);`
129			`--------------------------------------------------------`
130			`reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);`
131			`--------------------------------------------------------`
132			`reg_strobe_0 : out std_logic;`
133			`reg_in_0 : out std_logic_vector (15 downto 0);`
134			`reg_out_0 : in std_logic_vector (15 downto 0);`
135
136			`reg_strobe_1 : out std_logic;`
137			`reg_in_1 : out std_logic_vector (15 downto 0);`
138			`reg_out_1 : in std_logic_vector (15 downto 0);`
139
140			`reg_strobe_2 : out std_logic;`
141			`reg_in_2 : out std_logic_vector (15 downto 0);`
142			`reg_out_2 : in std_logic_vector (15 downto 0);`
143
144			`reg_strobe_3 : out std_logic;`
145			`reg_in_3 : out std_logic_vector (15 downto 0);`
146			`reg_out_3 : in std_logic_vector (15 downto 0);`
147
148			`reg_strobe_4 : out std_logic;`
149			`reg_in_4 : out std_logic_vector (15 downto 0);`
150			`reg_out_4 : in std_logic_vector (15 downto 0);`
151
152			`reg_strobe_5 : out std_logic;`
153			`reg_in_5 : out std_logic_vector (15 downto 0);`
154			`reg_out_5 : in std_logic_vector (15 downto 0);`
155
156			`reg_strobe_6 : out std_logic;`
157			`reg_in_6 : out std_logic_vector (15 downto 0);`
158			`reg_out_6 : in std_logic_vector (15 downto 0);`
159
160			`reg_strobe_7 : out std_logic;`
161			`reg_in_7 : out std_logic_vector (15 downto 0);`
162			`reg_out_7 : in std_logic_vector (15 downto 0);`
163
164			`reg_strobe_8 : out std_logic;`
165			`reg_in_8 : out std_logic_vector (15 downto 0);`
166			`reg_out_8 : in std_logic_vector (15 downto 0);`
167
168			`reg_strobe_9 : out std_logic;`
169			`reg_in_9 : out std_logic_vector (15 downto 0);`
170			`reg_out_9 : in std_logic_vector (15 downto 0);`
171
172			`reg_strobe_10 : out std_logic;`
173			`reg_in_10 : out std_logic_vector (15 downto 0);`
174			`reg_out_10 : in std_logic_vector (15 downto 0);`
175
176			`reg_strobe_11 : out std_logic;`
177			`reg_in_11 : out std_logic_vector (15 downto 0);`
178			`reg_out_11 : in std_logic_vector (15 downto 0);`
179
180			`reg_strobe_other0 : out std_logic;`
181			`reg_in_other0 : out std_logic_vector (15 downto 0);`
182			`reg_out_other0 : in std_logic_vector (15 downto 0);`
183
184			`reg_strobe_other1 : out std_logic;`
185			`reg_in_other1 : out std_logic_vector (15 downto 0);`
186			`reg_out_other1 : in std_logic_vector (15 downto 0)`
187
188			`);`
189			`end component;`
190
191			`component EventReg is`
192			`port (`
193			`reset : in std_logic;`
194			`clk : in std_logic;`
195			`strobe : in std_logic;`
196			`data_in : in std_logic_vector (15 downto 0);`
197			`data_out : out std_logic_vector (15 downto 0);`
198			`-------------------- gpib device ---------------------`
199			`-- device is local controlled`
200			`isLocal : in std_logic;`
201			`-- input buffer ready`
202			`in_buf_ready : in std_logic;`
203			`-- output buffer ready`
204			`out_buf_ready : in std_logic;`
205			`-- clear device (DC)`
206			`clr : in std_logic;`
207			`-- trigger device (DT)`
208			`trg : in std_logic;`
209			`-- addressed to talk(L or LE)`
210			`att : in std_logic;`
211			`-- addressed to listen (T or TE)`
212			`atl : in std_logic;`
213			`-- seriall poll active`
214			`spa : in std_logic;`
215			`-------------------- gpib controller ---------------------`
216			`-- controller write commands`
217			`cwrc : in std_logic;`
218			`-- controller write data`
219			`cwrd : in std_logic;`
220			`-- service requested`
221			`srq : in std_logic;`
222			`-- parallel poll ready`
223			`ppr : in std_logic;`
224			`-- stb received`
225			`stb_received : in std_logic;`
226			`REN : in std_logic;`
227			`ATN : in std_logic;`
228			`IFC : in std_logic`
229			`);`
230			`end component;`
231
232			`component gpibBusReg is`
233			`port (`
234			`data_out : out std_logic_vector (15 downto 0);`
235			`------------------------------------------------`
236			`-- interface signals`
237			`DIO : in std_logic_vector (7 downto 0);`
238			`-- attention`
239			`ATN : in std_logic;`
240			`-- data valid`
241			`DAV : in std_logic;`
242			`-- not ready for data`
243			`NRFD : in std_logic;`
244			`-- no data accepted`
245			`NDAC : in std_logic;`
246			`-- end or identify`
247			`EOI : in std_logic;`
248			`-- service request`
249			`SRQ : in std_logic;`
250			`-- interface clear`
251			`IFC : in std_logic;`
252			`-- remote enable`
253			`REN : in std_logic`
254			`);`
255			`end component;`
256
257			`component gpibControlReg is`
258			`port (`
259			`reset : in std_logic;`
260			`strobe : in std_logic;`
261			`data_in : in std_logic_vector (15 downto 0);`
262			`data_out : out std_logic_vector (15 downto 0);`
263			`------------------ gpib ------------------------`
264			`ltn : out std_logic; -- listen (L, LE)`
265			`lun : out std_logic; -- local unlisten (L, LE)`
266			`rtl : out std_logic; -- return to local (RL)`
267			`rsv : out std_logic; -- request service (SR)`
268			`ist : out std_logic; -- individual status (PP)`
269			`lpe : out std_logic; -- local poll enable (PP)`
270			`------------------------------------------------`
271			`rsc : out std_logic; -- request system control (C)`
272			`sic : out std_logic; -- send interface clear (C)`
273			`sre : out std_logic; -- send remote enable (C)`
274			`gts : out std_logic; -- go to standby (C)`
275			`tcs : out std_logic; -- take control synchronously (C, AH)`
276			`tca : out std_logic; -- take control asynchronously (C)`
277			`rpp : out std_logic; -- request parallel poll (C)`
278			`rec_stb : out std_logic -- receives status byte (C)`
279			`);`
280			`end component;`
281
282			`component GpibStatusReg is`
283			`port (`
284			`data_out : out std_logic_vector (15 downto 0);`
285			`-- gpib`
286			`currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr`
287			`att : in std_logic; -- addressed to talk(L or LE)`
288			`tac : in std_logic; -- talker active (T, TE)`
289			`atl : in std_logic; -- addressed to listen (T or TE)`
290			`lac : in std_logic; -- listener active (L, LE)`
291			`cwrc : in std_logic; -- controller write commands`
292			`cwrd : in std_logic; -- controller write data`
293			`spa : in std_logic; -- seriall poll active`
294			`isLocal : in std_logic -- device is local controlled`
295			`);`
296			`end component;`
297
298			`component ReaderControlReg0 is`
299			`port (`
300			`clk : in std_logic;`
301			`reset : in std_logic;`
302			`strobe : in std_logic;`
303			`data_in : in std_logic_vector (15 downto 0);`
304			`data_out : out std_logic_vector (15 downto 0);`
305			`------------------- gpib -------------------------`
306			`-- buffer ready interrupt`
307			`buf_interrupt : in std_logic;`
308			`-- at least one byte available`
309			`data_available : in std_logic;`
310			`-- indicates end of stream`
311			`end_of_stream : in std_logic;`
312			`-- resets buffer`
313			`reset_buffer : out std_logic;`
314			`-- secondary address of data`
315			`dataSecAddr : in std_logic_vector (4 downto 0)`
316			`);`
317			`end component;`
318
319			`component ReaderControlReg1 is`
320			`port (`
321			`data_out : out std_logic_vector (15 downto 0);`
322			`------------------ gpib --------------------`
323			`-- num of bytes available in fifo`
324			`bytes_available_in_fifo : in std_logic_vector (10 downto 0)`
325			`);`
326			`end component;`
327
328			`component SecAddrReg is`
329			`port (`
330			`reset : in std_logic;`
331			`strobe : in std_logic;`
332			`data_in : in std_logic_vector (15 downto 0);`
333			`data_out : out std_logic_vector (15 downto 0);`
334			`-- gpib`
335			`secAddrMask : out std_logic_vector (15 downto 0)`
336			`);`
337			`end component;`
338
339			`component SettingsReg0 is`
340			`port (`
341			`reset : in std_logic;`
342			`strobe : in std_logic;`
343			`data_in : in std_logic_vector (15 downto 0);`
344			`data_out : out std_logic_vector (15 downto 0);`
345			`------------- gpib -----------------------------`
346			`isLE_TE : out std_logic;`
347			`lpeUsed : out std_logic;`
348			`fixedPpLine : out std_logic_vector (2 downto 0);`
349			`eosUsed : out std_logic;`
350			`eosMark : out std_logic_vector (7 downto 0);`
351			`lon : out std_logic;`
352			`ton : out std_logic`
353			`);`
354			`end component;`
355
356			`component SettingsReg1 is`
357			`port (`
358			`reset : in std_logic;`
359			`strobe : in std_logic;`
360			`data_in : in std_logic_vector (15 downto 0);`
361			`data_out : out std_logic_vector (15 downto 0);`
362			`-- gpib`
363			`myAddr : out std_logic_vector (4 downto 0);`
364			`T1 : out std_logic_vector (7 downto 0)`
365			`);`
366			`end component;`
367
368			`component WriterControlReg0 is`
369			`port (`
370			`clk : in std_logic;`
371			`reset : in std_logic;`
372			`strobe : in std_logic;`
373			`data_in : in std_logic_vector (15 downto 0);`
374			`data_out : out std_logic_vector (15 downto 0);`
375			`------------------- gpib -------------------------`
376			`-- buffer consumed`
377			`buf_interrupt : in std_logic;`
378			`-- data avilable - at least one byte in buffer`
379			`data_available : out std_logic;`
380			`-- indicates end of stream`
381			`end_of_stream : out std_logic;`
382			`-- resets buffer`
383			`reset_buffer : out std_logic;`
384			`-- secondary address of data`
385			`dataSecAddr : out std_logic_vector (4 downto 0);`
386			`-- serial poll status byte`
387			`status_byte : out std_logic_vector (6 downto 0)`
388			`);`
389			`end component;`
390
391			`component WriterControlReg1 is`
392			`port (`
393			`reset : in std_logic;`
394			`strobe : in std_logic;`
395			`data_in : in std_logic_vector (15 downto 0);`
396			`data_out : out std_logic_vector (15 downto 0);`
397			`------------------ gpib --------------------`
398			`-- num of bytes available in fifo`
399			`bytes_available_in_fifo : in std_logic_vector (10 downto 0)`
400			`);`
401			`end component;`
402
403			`end wrapperComponents;`
404