URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [common/] [wrapperComponents.vhd] - Blame information for rev 3

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--------------------------------------------------------------------------------
-- Entity: wrapperComponents
-- Date:2011-11-17  
-- Author: apaluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
package wrapperComponents is
 
        component RegsGpibFasade is
                port (
                        reset : std_logic;
                        clk : in std_logic;
                        -----------------------------------------------------------------------
                        ------------ GPIB interface signals -----------------------------------
                        -----------------------------------------------------------------------
                        DI : in std_logic_vector (7 downto 0);
                        DO : out std_logic_vector (7 downto 0);
                        output_valid : out std_logic;
                        -- attention
                        ATN_in : in std_logic;
                        ATN_out : out std_logic;
                        -- data valid
                        DAV_in : in std_logic;
                        DAV_out : out std_logic;
                        -- not ready for data
                        NRFD_in : in std_logic;
                        NRFD_out : out std_logic;
                        -- no data accepted
                        NDAC_in : in std_logic;
                        NDAC_out : out std_logic;
                        -- end or identify
                        EOI_in : in std_logic;
                        EOI_out : out std_logic;
                        -- service request
                        SRQ_in : in std_logic;
                        SRQ_out : out std_logic;
                        -- interface clear
                        IFC_in : in std_logic;
                        IFC_out : out std_logic;
                        -- remote enable
                        REN_in : in std_logic;
                        REN_out : out std_logic;
                        -----------------------------------------------------------------------
                        ---------------- registers access -------------------------------------
                        -----------------------------------------------------------------------
                        data_in : in std_logic_vector(15 downto 0);
                        data_out : out std_logic_vector(15 downto 0);
                        reg_addr : in std_logic_vector(14 downto 0);
                        strobe_read : in std_logic;
                        strobe_write : in std_logic;
                        -----------------------------------------------------------------------
                        ---------------- additional lines -------------------------------------
                        -----------------------------------------------------------------------
                        interrupt_line : out std_logic
                        ;debug1 : out std_logic
                        ;debug2 : out std_logic
                );
        end component;
 
        component InterruptGenerator is
                port (
                        reset : std_logic;
                        clk : in std_logic;
                        interrupt : out std_logic;
                        -------------------- gpib device ---------------------
                        -- device is local controlled
                        isLocal : in std_logic;
                        -- input buffer ready
                        in_buf_ready : in std_logic;
                        -- output buffer ready
                        out_buf_ready : in std_logic;
                        -- clear device (DC)
                        clr : in std_logic;
                        -- trigger device (DT)
                        trg : in std_logic;
                        -- addressed to talk(L or LE)
                        att : in std_logic;
                        -- addressed to listen (T or TE)
                        atl : in std_logic;
                        -- seriall poll active
                        spa : in std_logic;
                        -------------------- gpib controller ---------------------
                        -- controller write commands
                        cwrc : in std_logic;
                        -- controller write data
                        cwrd : in std_logic;
                        -- service requested
                        srq : in std_logic;
                        -- parallel poll ready
                        ppr : in std_logic;
                        -- stb received
                        stb_received : in std_logic;
                        REN : in std_logic;
                        ATN : in std_logic;
                        IFC : in std_logic
                );
        end component;
 
        component RegMultiplexer is
                generic (
                        ADDR_WIDTH : integer := 15
                );
                port (
                        strobe_read : in std_logic;
                        strobe_write : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        --------------------------------------------------------
                        reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);
                        --------------------------------------------------------
                        reg_strobe_0 : out std_logic;
                        reg_in_0 : out std_logic_vector (15 downto 0);
                        reg_out_0 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_1 : out std_logic;
                        reg_in_1 : out std_logic_vector (15 downto 0);
                        reg_out_1 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_2 : out std_logic;
                        reg_in_2 : out std_logic_vector (15 downto 0);
                        reg_out_2 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_3 : out std_logic;
                        reg_in_3 : out std_logic_vector (15 downto 0);
                        reg_out_3 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_4 : out std_logic;
                        reg_in_4 : out std_logic_vector (15 downto 0);
                        reg_out_4 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_5 : out std_logic;
                        reg_in_5 : out std_logic_vector (15 downto 0);
                        reg_out_5 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_6 : out std_logic;
                        reg_in_6 : out std_logic_vector (15 downto 0);
                        reg_out_6 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_7 : out std_logic;
                        reg_in_7 : out std_logic_vector (15 downto 0);
                        reg_out_7 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_8 : out std_logic;
                        reg_in_8 : out std_logic_vector (15 downto 0);
                        reg_out_8 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_9 : out std_logic;
                        reg_in_9 : out std_logic_vector (15 downto 0);
                        reg_out_9 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_10 : out std_logic;
                        reg_in_10 : out std_logic_vector (15 downto 0);
                        reg_out_10 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_11 : out std_logic;
                        reg_in_11 : out std_logic_vector (15 downto 0);
                        reg_out_11 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_other0 : out std_logic;
                        reg_in_other0 : out std_logic_vector (15 downto 0);
                        reg_out_other0 : in std_logic_vector (15 downto 0);
 
                        reg_strobe_other1 : out std_logic;
                        reg_in_other1 : out std_logic_vector (15 downto 0);
                        reg_out_other1 : in std_logic_vector (15 downto 0)
 
                );
        end component;
 
        component EventReg is
                port (
                        reset : in std_logic;
                        clk : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        -------------------- gpib device ---------------------
                        -- device is local controlled
                        isLocal : in std_logic;
                        -- input buffer ready
                        in_buf_ready : in std_logic;
                        -- output buffer ready
                        out_buf_ready : in std_logic;
                        -- clear device (DC)
                        clr : in std_logic;
                        -- trigger device (DT)
                        trg : in std_logic;
                        -- addressed to talk(L or LE)
                        att : in std_logic;
                        -- addressed to listen (T or TE)
                        atl : in std_logic;
                        -- seriall poll active
                        spa : in std_logic;
                        -------------------- gpib controller ---------------------
                        -- controller write commands
                        cwrc : in std_logic;
                        -- controller write data
                        cwrd : in std_logic;
                        -- service requested
                        srq : in std_logic;
                        -- parallel poll ready
                        ppr : in std_logic;
                        -- stb received
                        stb_received : in std_logic;
                        REN : in std_logic;
                        ATN : in std_logic;
                        IFC : in std_logic
                );
        end component;
 
        component gpibBusReg is
                port (
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------------------------------------
                        -- interface signals
                        DIO : in std_logic_vector (7 downto 0);
                        -- attention
                        ATN : in std_logic;
                        -- data valid
                        DAV : in std_logic;
                        -- not ready for data
                        NRFD : in std_logic;
                        -- no data accepted
                        NDAC : in std_logic;
                        -- end or identify
                        EOI : in std_logic;
                        -- service request
                        SRQ : in std_logic;
                        -- interface clear
                        IFC : in std_logic;
                        -- remote enable
                        REN : in std_logic
                );
        end component;
 
        component gpibControlReg is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------ gpib ------------------------
                        ltn : out std_logic; -- listen (L, LE)
                        lun : out std_logic; -- local unlisten (L, LE)
                        rtl : out std_logic; -- return to local (RL)
                        rsv : out std_logic; -- request service (SR)
                        ist : out std_logic; -- individual status (PP)
                        lpe : out std_logic; -- local poll enable (PP)
                        ------------------------------------------------
                        rsc : out std_logic; -- request system control (C)
                        sic : out std_logic; -- send interface clear (C)
                        sre : out std_logic; -- send remote enable (C)
                        gts : out std_logic; -- go to standby (C)
                        tcs : out std_logic; -- take control synchronously (C, AH)
                        tca : out std_logic; -- take control asynchronously (C)
                        rpp : out std_logic; -- request parallel poll (C)
                        rec_stb : out std_logic -- receives status byte (C)
                );
        end component;
 
        component GpibStatusReg is
                port (
                        data_out : out std_logic_vector (15 downto 0);
                        -- gpib
                        currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr
                        att : in std_logic; -- addressed to talk(L or LE)
                        tac : in std_logic; -- talker active (T, TE)
                        atl : in std_logic; -- addressed to listen (T or TE)
                        lac : in std_logic; -- listener active (L, LE)
                        cwrc : in std_logic; -- controller write commands
                        cwrd : in std_logic; -- controller write data
                        spa : in std_logic; -- seriall poll active
                        isLocal : in std_logic -- device is local controlled
                );
        end component;
 
        component ReaderControlReg0 is
                port (
                        clk : in std_logic;
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------- gpib -------------------------
                        -- buffer ready interrupt
                        buf_interrupt : in std_logic;
                        -- at least one byte available
                        data_available : in std_logic;
                        -- indicates end of stream
                        end_of_stream : in std_logic;
                        -- resets buffer
                        reset_buffer : out std_logic;
                        -- secondary address of data
                        dataSecAddr : in std_logic_vector (4 downto 0)
                );
        end component;
 
        component ReaderControlReg1 is
                port (
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------ gpib --------------------
                        -- num of bytes available in fifo
                        bytes_available_in_fifo : in std_logic_vector (10 downto 0)
                );
        end component;
 
        component SecAddrReg is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        -- gpib
                        secAddrMask : out std_logic_vector (15 downto 0)
                );
        end component;
 
        component SettingsReg0 is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------- gpib -----------------------------
                        isLE_TE : out std_logic;
                        lpeUsed : out std_logic;
                        fixedPpLine : out std_logic_vector (2 downto 0);
                        eosUsed : out std_logic;
                        eosMark : out std_logic_vector (7 downto 0);
                        lon : out std_logic;
                        ton : out std_logic
                );
        end component;
 
        component SettingsReg1 is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        -- gpib
                        myAddr : out std_logic_vector (4 downto 0);
                        T1 : out std_logic_vector (7 downto 0)
                );
        end component;
 
        component WriterControlReg0 is
                port (
                        clk : in std_logic;
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------- gpib -------------------------
                        -- buffer consumed
                        buf_interrupt : in std_logic;
                        -- data avilable - at least one byte in buffer
                        data_available : out std_logic;
                        -- indicates end of stream
                        end_of_stream : out std_logic;
                        -- resets buffer
                        reset_buffer : out std_logic;
                        -- secondary address of data
                        dataSecAddr : out std_logic_vector (4 downto 0);
                        -- serial poll status byte
                        status_byte : out std_logic_vector (6 downto 0)
                );
        end component;
 
        component WriterControlReg1 is
                port (
                        reset : in std_logic;
                        strobe : in std_logic;
                        data_in : in std_logic_vector (15 downto 0);
                        data_out : out std_logic_vector (15 downto 0);
                        ------------------ gpib --------------------
                        -- num of bytes available in fifo
                        bytes_available_in_fifo : in std_logic_vector (10 downto 0)
                );
        end component;
 
end wrapperComponents;
 

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [common/] [wrapperComponents.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2			`-- Entity: wrapperComponents`
3			`-- Date:2011-11-17`
4			`-- Author: apaluch`
5			`--`
6			`-- Description ${cursor}`
7			`--------------------------------------------------------------------------------`
8			`library ieee;`
9			`use ieee.std_logic_1164.all;`
10			`use ieee.std_logic_unsigned.all;`
11
12
13			`package wrapperComponents is`
14
15			`component RegsGpibFasade is`
16			`port (`
17			`reset : std_logic;`
18			`clk : in std_logic;`
19			`-----------------------------------------------------------------------`
20			`------------ GPIB interface signals -----------------------------------`
21			`-----------------------------------------------------------------------`
22			`DI : in std_logic_vector (7 downto 0);`
23			`DO : out std_logic_vector (7 downto 0);`
24			`output_valid : out std_logic;`
25			`-- attention`
26			`ATN_in : in std_logic;`
27			`ATN_out : out std_logic;`
28			`-- data valid`
29			`DAV_in : in std_logic;`
30			`DAV_out : out std_logic;`
31			`-- not ready for data`
32			`NRFD_in : in std_logic;`
33			`NRFD_out : out std_logic;`
34			`-- no data accepted`
35			`NDAC_in : in std_logic;`
36			`NDAC_out : out std_logic;`
37			`-- end or identify`
38			`EOI_in : in std_logic;`
39			`EOI_out : out std_logic;`
40			`-- service request`
41			`SRQ_in : in std_logic;`
42			`SRQ_out : out std_logic;`
43			`-- interface clear`
44			`IFC_in : in std_logic;`
45			`IFC_out : out std_logic;`
46			`-- remote enable`
47			`REN_in : in std_logic;`
48			`REN_out : out std_logic;`
49			`-----------------------------------------------------------------------`
50			`---------------- registers access -------------------------------------`
51			`-----------------------------------------------------------------------`
52			`data_in : in std_logic_vector(15 downto 0);`
53			`data_out : out std_logic_vector(15 downto 0);`
54			`reg_addr : in std_logic_vector(14 downto 0);`
55			`strobe_read : in std_logic;`
56			`strobe_write : in std_logic;`
57			`-----------------------------------------------------------------------`
58			`---------------- additional lines -------------------------------------`
59			`-----------------------------------------------------------------------`
60			`interrupt_line : out std_logic`
61			`;debug1 : out std_logic`
62			`;debug2 : out std_logic`
63			`);`
64			`end component;`
65
66			`component InterruptGenerator is`
67			`port (`
68			`reset : std_logic;`
69			`clk : in std_logic;`
70			`interrupt : out std_logic;`
71			`-------------------- gpib device ---------------------`
72			`-- device is local controlled`
73			`isLocal : in std_logic;`
74			`-- input buffer ready`
75			`in_buf_ready : in std_logic;`
76			`-- output buffer ready`
77			`out_buf_ready : in std_logic;`
78			`-- clear device (DC)`
79			`clr : in std_logic;`
80			`-- trigger device (DT)`
81			`trg : in std_logic;`
82			`-- addressed to talk(L or LE)`
83			`att : in std_logic;`
84			`-- addressed to listen (T or TE)`
85			`atl : in std_logic;`
86			`-- seriall poll active`
87			`spa : in std_logic;`
88			`-------------------- gpib controller ---------------------`
89			`-- controller write commands`
90			`cwrc : in std_logic;`
91			`-- controller write data`
92			`cwrd : in std_logic;`
93			`-- service requested`
94			`srq : in std_logic;`
95			`-- parallel poll ready`
96			`ppr : in std_logic;`
97			`-- stb received`
98			`stb_received : in std_logic;`
99			`REN : in std_logic;`
100			`ATN : in std_logic;`
101			`IFC : in std_logic`
102			`);`
103			`end component;`
104
105			`component RegMultiplexer is`
106			`generic (`
107			`ADDR_WIDTH : integer := 15`
108			`);`
109			`port (`
110			`strobe_read : in std_logic;`
111			`strobe_write : in std_logic;`
112			`data_in : in std_logic_vector (15 downto 0);`
113			`data_out : out std_logic_vector (15 downto 0);`
114			`--------------------------------------------------------`
115			`reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);`
116			`--------------------------------------------------------`
117			`reg_strobe_0 : out std_logic;`
118			`reg_in_0 : out std_logic_vector (15 downto 0);`
119			`reg_out_0 : in std_logic_vector (15 downto 0);`
120
121			`reg_strobe_1 : out std_logic;`
122			`reg_in_1 : out std_logic_vector (15 downto 0);`
123			`reg_out_1 : in std_logic_vector (15 downto 0);`
124
125			`reg_strobe_2 : out std_logic;`
126			`reg_in_2 : out std_logic_vector (15 downto 0);`
127			`reg_out_2 : in std_logic_vector (15 downto 0);`
128
129			`reg_strobe_3 : out std_logic;`
130			`reg_in_3 : out std_logic_vector (15 downto 0);`
131			`reg_out_3 : in std_logic_vector (15 downto 0);`
132
133			`reg_strobe_4 : out std_logic;`
134			`reg_in_4 : out std_logic_vector (15 downto 0);`
135			`reg_out_4 : in std_logic_vector (15 downto 0);`
136
137			`reg_strobe_5 : out std_logic;`
138			`reg_in_5 : out std_logic_vector (15 downto 0);`
139			`reg_out_5 : in std_logic_vector (15 downto 0);`
140
141			`reg_strobe_6 : out std_logic;`
142			`reg_in_6 : out std_logic_vector (15 downto 0);`
143			`reg_out_6 : in std_logic_vector (15 downto 0);`
144
145			`reg_strobe_7 : out std_logic;`
146			`reg_in_7 : out std_logic_vector (15 downto 0);`
147			`reg_out_7 : in std_logic_vector (15 downto 0);`
148
149			`reg_strobe_8 : out std_logic;`
150			`reg_in_8 : out std_logic_vector (15 downto 0);`
151			`reg_out_8 : in std_logic_vector (15 downto 0);`
152
153			`reg_strobe_9 : out std_logic;`
154			`reg_in_9 : out std_logic_vector (15 downto 0);`
155			`reg_out_9 : in std_logic_vector (15 downto 0);`
156
157			`reg_strobe_10 : out std_logic;`
158			`reg_in_10 : out std_logic_vector (15 downto 0);`
159			`reg_out_10 : in std_logic_vector (15 downto 0);`
160
161			`reg_strobe_11 : out std_logic;`
162			`reg_in_11 : out std_logic_vector (15 downto 0);`
163			`reg_out_11 : in std_logic_vector (15 downto 0);`
164
165			`reg_strobe_other0 : out std_logic;`
166			`reg_in_other0 : out std_logic_vector (15 downto 0);`
167			`reg_out_other0 : in std_logic_vector (15 downto 0);`
168
169			`reg_strobe_other1 : out std_logic;`
170			`reg_in_other1 : out std_logic_vector (15 downto 0);`
171			`reg_out_other1 : in std_logic_vector (15 downto 0)`
172
173			`);`
174			`end component;`
175
176			`component EventReg is`
177			`port (`
178			`reset : in std_logic;`
179			`clk : in std_logic;`
180			`strobe : in std_logic;`
181			`data_in : in std_logic_vector (15 downto 0);`
182			`data_out : out std_logic_vector (15 downto 0);`
183			`-------------------- gpib device ---------------------`
184			`-- device is local controlled`
185			`isLocal : in std_logic;`
186			`-- input buffer ready`
187			`in_buf_ready : in std_logic;`
188			`-- output buffer ready`
189			`out_buf_ready : in std_logic;`
190			`-- clear device (DC)`
191			`clr : in std_logic;`
192			`-- trigger device (DT)`
193			`trg : in std_logic;`
194			`-- addressed to talk(L or LE)`
195			`att : in std_logic;`
196			`-- addressed to listen (T or TE)`
197			`atl : in std_logic;`
198			`-- seriall poll active`
199			`spa : in std_logic;`
200			`-------------------- gpib controller ---------------------`
201			`-- controller write commands`
202			`cwrc : in std_logic;`
203			`-- controller write data`
204			`cwrd : in std_logic;`
205			`-- service requested`
206			`srq : in std_logic;`
207			`-- parallel poll ready`
208			`ppr : in std_logic;`
209			`-- stb received`
210			`stb_received : in std_logic;`
211			`REN : in std_logic;`
212			`ATN : in std_logic;`
213			`IFC : in std_logic`
214			`);`
215			`end component;`
216
217			`component gpibBusReg is`
218			`port (`
219			`data_out : out std_logic_vector (15 downto 0);`
220			`------------------------------------------------`
221			`-- interface signals`
222			`DIO : in std_logic_vector (7 downto 0);`
223			`-- attention`
224			`ATN : in std_logic;`
225			`-- data valid`
226			`DAV : in std_logic;`
227			`-- not ready for data`
228			`NRFD : in std_logic;`
229			`-- no data accepted`
230			`NDAC : in std_logic;`
231			`-- end or identify`
232			`EOI : in std_logic;`
233			`-- service request`
234			`SRQ : in std_logic;`
235			`-- interface clear`
236			`IFC : in std_logic;`
237			`-- remote enable`
238			`REN : in std_logic`
239			`);`
240			`end component;`
241
242			`component gpibControlReg is`
243			`port (`
244			`reset : in std_logic;`
245			`strobe : in std_logic;`
246			`data_in : in std_logic_vector (15 downto 0);`
247			`data_out : out std_logic_vector (15 downto 0);`
248			`------------------ gpib ------------------------`
249			`ltn : out std_logic; -- listen (L, LE)`
250			`lun : out std_logic; -- local unlisten (L, LE)`
251			`rtl : out std_logic; -- return to local (RL)`
252			`rsv : out std_logic; -- request service (SR)`
253			`ist : out std_logic; -- individual status (PP)`
254			`lpe : out std_logic; -- local poll enable (PP)`
255			`------------------------------------------------`
256			`rsc : out std_logic; -- request system control (C)`
257			`sic : out std_logic; -- send interface clear (C)`
258			`sre : out std_logic; -- send remote enable (C)`
259			`gts : out std_logic; -- go to standby (C)`
260			`tcs : out std_logic; -- take control synchronously (C, AH)`
261			`tca : out std_logic; -- take control asynchronously (C)`
262			`rpp : out std_logic; -- request parallel poll (C)`
263			`rec_stb : out std_logic -- receives status byte (C)`
264			`);`
265			`end component;`
266
267			`component GpibStatusReg is`
268			`port (`
269			`data_out : out std_logic_vector (15 downto 0);`
270			`-- gpib`
271			`currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr`
272			`att : in std_logic; -- addressed to talk(L or LE)`
273			`tac : in std_logic; -- talker active (T, TE)`
274			`atl : in std_logic; -- addressed to listen (T or TE)`
275			`lac : in std_logic; -- listener active (L, LE)`
276			`cwrc : in std_logic; -- controller write commands`
277			`cwrd : in std_logic; -- controller write data`
278			`spa : in std_logic; -- seriall poll active`
279			`isLocal : in std_logic -- device is local controlled`
280			`);`
281			`end component;`
282
283			`component ReaderControlReg0 is`
284			`port (`
285			`clk : in std_logic;`
286			`reset : in std_logic;`
287			`strobe : in std_logic;`
288			`data_in : in std_logic_vector (15 downto 0);`
289			`data_out : out std_logic_vector (15 downto 0);`
290			`------------------- gpib -------------------------`
291			`-- buffer ready interrupt`
292			`buf_interrupt : in std_logic;`
293			`-- at least one byte available`
294			`data_available : in std_logic;`
295			`-- indicates end of stream`
296			`end_of_stream : in std_logic;`
297			`-- resets buffer`
298			`reset_buffer : out std_logic;`
299			`-- secondary address of data`
300			`dataSecAddr : in std_logic_vector (4 downto 0)`
301			`);`
302			`end component;`
303
304			`component ReaderControlReg1 is`
305			`port (`
306			`data_out : out std_logic_vector (15 downto 0);`
307			`------------------ gpib --------------------`
308			`-- num of bytes available in fifo`
309			`bytes_available_in_fifo : in std_logic_vector (10 downto 0)`
310			`);`
311			`end component;`
312
313			`component SecAddrReg is`
314			`port (`
315			`reset : in std_logic;`
316			`strobe : in std_logic;`
317			`data_in : in std_logic_vector (15 downto 0);`
318			`data_out : out std_logic_vector (15 downto 0);`
319			`-- gpib`
320			`secAddrMask : out std_logic_vector (15 downto 0)`
321			`);`
322			`end component;`
323
324			`component SettingsReg0 is`
325			`port (`
326			`reset : in std_logic;`
327			`strobe : in std_logic;`
328			`data_in : in std_logic_vector (15 downto 0);`
329			`data_out : out std_logic_vector (15 downto 0);`
330			`------------- gpib -----------------------------`
331			`isLE_TE : out std_logic;`
332			`lpeUsed : out std_logic;`
333			`fixedPpLine : out std_logic_vector (2 downto 0);`
334			`eosUsed : out std_logic;`
335			`eosMark : out std_logic_vector (7 downto 0);`
336			`lon : out std_logic;`
337			`ton : out std_logic`
338			`);`
339			`end component;`
340
341			`component SettingsReg1 is`
342			`port (`
343			`reset : in std_logic;`
344			`strobe : in std_logic;`
345			`data_in : in std_logic_vector (15 downto 0);`
346			`data_out : out std_logic_vector (15 downto 0);`
347			`-- gpib`
348			`myAddr : out std_logic_vector (4 downto 0);`
349			`T1 : out std_logic_vector (7 downto 0)`
350			`);`
351			`end component;`
352
353			`component WriterControlReg0 is`
354			`port (`
355			`clk : in std_logic;`
356			`reset : in std_logic;`
357			`strobe : in std_logic;`
358			`data_in : in std_logic_vector (15 downto 0);`
359			`data_out : out std_logic_vector (15 downto 0);`
360			`------------------- gpib -------------------------`
361			`-- buffer consumed`
362			`buf_interrupt : in std_logic;`
363			`-- data avilable - at least one byte in buffer`
364			`data_available : out std_logic;`
365			`-- indicates end of stream`
366			`end_of_stream : out std_logic;`
367			`-- resets buffer`
368			`reset_buffer : out std_logic;`
369			`-- secondary address of data`
370			`dataSecAddr : out std_logic_vector (4 downto 0);`
371			`-- serial poll status byte`
372			`status_byte : out std_logic_vector (6 downto 0)`
373			`);`
374			`end component;`
375
376			`component WriterControlReg1 is`
377			`port (`
378			`reset : in std_logic;`
379			`strobe : in std_logic;`
380			`data_in : in std_logic_vector (15 downto 0);`
381			`data_out : out std_logic_vector (15 downto 0);`
382			`------------------ gpib --------------------`
383			`-- num of bytes available in fifo`
384			`bytes_available_in_fifo : in std_logic_vector (10 downto 0)`
385			`);`
386			`end component;`
387
388			`end wrapperComponents;`
389