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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_AH.vhd] - Blame information for rev 3

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:04:57 10/01/2011 
-- Design Name: 
-- Module Name:    if_func_AH - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
use work.utilPkg.all;
 
 
entity if_func_AH is
        port(
                -- device inputs
                clk : in std_logic; -- clock
                pon : in std_logic; -- power on
                rdy : in std_logic; -- ready for next message
                tcs : in std_logic; -- take control synchronously
                -- state inputs
                LACS : in std_logic; -- listener active state
                LADS : in std_logic; -- listener addressed state
                -- interface inputs
                ATN : in std_logic; -- attention
                DAV : in std_logic; -- data accepted
                -- interface outputs
                RFD : out std_logic; -- ready for data
                DAC : out std_logic; -- data accepted
                -- reported state
                ANRS : out std_logic; -- acceptor not ready state
                ACDS : out std_logic -- accept data state
        );
end if_func_AH;
 
architecture Behavioral of if_func_AH is
 
        -- states
        type AH_STATE is (
                -- acceptor idle state
                ST_AIDS,
                -- acceptor not ready state
                ST_ANRS,
                -- acceptor ready state
                ST_ACRS,
                -- acceptor wait for new cycle state
                ST_AWNS,
                -- accept data state
                ST_ACDS
        );
 
        -- current state
        signal current_state : AH_STATE;
 
        -- events
        signal event1, event2, event3, event4, event5, event6, event7 : boolean;
 
        -- timers
        constant TIMER_T3_MAX : integer := 3;
        constant TIMER_T3_TIMEOUT : integer := 2;
        signal timerT3 : integer range 0 to TIMER_T3_MAX;
        signal timerT3Expired : boolean;
 
begin
 
        -- state machine process
        process(pon, clk) begin
                if pon = '1' then
                        current_state <= ST_AIDS;
                elsif rising_edge(clk) then
                        case current_state is
                                ------------------
                                when ST_AIDS =>
                                        if event2 then
                                                -- no state change
                                        elsif event1 then
                                                current_state <= ST_ANRS;
                                        end if;
                                ------------------
                                when ST_ANRS =>
                                        if event2 then
                                                current_state <= ST_AIDS;
                                        elsif event4 then
                                                current_state <= ST_ACRS;
                                        end if;
                                ------------------
                                when ST_ACRS =>
                                        if event2 then
                                                current_state <= ST_AIDS;
                                        elsif event5 then
                                                current_state <= ST_ANRS;
                                        elsif event6 then
                                                timerT3 <= 0;
                                                current_state <= ST_ACDS;
                                        end if;
                                ------------------
                                when ST_ACDS =>
                                        if event2 then
                                                current_state <= ST_AIDS;
                                        elsif event3 then
                                                current_state <= ST_AWNS;
                                        end if;
 
                                        if timerT3 < TIMER_T3_MAX then
                                                timerT3 <= timerT3 + 1;
                                        end if;
                                ------------------
                                when ST_AWNS =>
                                        if event2 then
                                                current_state <= ST_AIDS;
                                        elsif event7 then
                                                current_state <= ST_ANRS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state <= ST_AIDS;
                        end case;
                end if;
        end process;
 
 
        -- events
        event1 <= ATN='1' or LACS='1' or LADS='1';
        event2 <= not(ATN='1' or LACS='1' or LADS='1');
        event3 <= (rdy='0' and ATN='0') or (timerT3Expired and ATN='1');
        event4 <= (ATN='1' or rdy='1') and tcs='0';
        event5 <= not (ATN='1' or rdy='1');
        event6 <= DAV = '1';
        event7 <= DAV = '0';
 
        -- timers
        timerT3Expired <= timerT3 >= TIMER_T3_TIMEOUT;
 
        RFD <= to_stdl(
                        current_state = ST_AIDS or
                        current_state = ST_ACRS
                );
 
        DAC <= to_stdl(
                        current_state = ST_AIDS or
                        current_state = ST_AWNS
                );
 
        ACDS <= to_stdl(current_state = ST_ACDS);
        ANRS <= to_stdl(current_state = ST_ANRS);
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	3	Andrewski	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 01:04:57 10/01/2011`
6			`-- Design Name:`
7			`-- Module Name: if_func_AH - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22
23			`use work.utilPkg.all;`
24
25
26			`entity if_func_AH is`
27			`port(`
28			`-- device inputs`
29			`clk : in std_logic; -- clock`
30			`pon : in std_logic; -- power on`
31			`rdy : in std_logic; -- ready for next message`
32			`tcs : in std_logic; -- take control synchronously`
33			`-- state inputs`
34			`LACS : in std_logic; -- listener active state`
35			`LADS : in std_logic; -- listener addressed state`
36			`-- interface inputs`
37			`ATN : in std_logic; -- attention`
38			`DAV : in std_logic; -- data accepted`
39			`-- interface outputs`
40			`RFD : out std_logic; -- ready for data`
41			`DAC : out std_logic; -- data accepted`
42			`-- reported state`
43			`ANRS : out std_logic; -- acceptor not ready state`
44			`ACDS : out std_logic -- accept data state`
45			`);`
46			`end if_func_AH;`
47
48			`architecture Behavioral of if_func_AH is`
49
50			`-- states`
51			`type AH_STATE is (`
52			`-- acceptor idle state`
53			`ST_AIDS,`
54			`-- acceptor not ready state`
55			`ST_ANRS,`
56			`-- acceptor ready state`
57			`ST_ACRS,`
58			`-- acceptor wait for new cycle state`
59			`ST_AWNS,`
60			`-- accept data state`
61			`ST_ACDS`
62			`);`
63
64			`-- current state`
65			`signal current_state : AH_STATE;`
66
67			`-- events`
68			`signal event1, event2, event3, event4, event5, event6, event7 : boolean;`
69
70			`-- timers`
71			`constant TIMER_T3_MAX : integer := 3;`
72			`constant TIMER_T3_TIMEOUT : integer := 2;`
73			`signal timerT3 : integer range 0 to TIMER_T3_MAX;`
74			`signal timerT3Expired : boolean;`
75
76			`begin`
77
78			`-- state machine process`
79			`process(pon, clk) begin`
80			`if pon = '1' then`
81			`current_state <= ST_AIDS;`
82			`elsif rising_edge(clk) then`
83			`case current_state is`
84			`------------------`
85			`when ST_AIDS =>`
86			`if event2 then`
87			`-- no state change`
88			`elsif event1 then`
89			`current_state <= ST_ANRS;`
90			`end if;`
91			`------------------`
92			`when ST_ANRS =>`
93			`if event2 then`
94			`current_state <= ST_AIDS;`
95			`elsif event4 then`
96			`current_state <= ST_ACRS;`
97			`end if;`
98			`------------------`
99			`when ST_ACRS =>`
100			`if event2 then`
101			`current_state <= ST_AIDS;`
102			`elsif event5 then`
103			`current_state <= ST_ANRS;`
104			`elsif event6 then`
105			`timerT3 <= 0;`
106			`current_state <= ST_ACDS;`
107			`end if;`
108			`------------------`
109			`when ST_ACDS =>`
110			`if event2 then`
111			`current_state <= ST_AIDS;`
112			`elsif event3 then`
113			`current_state <= ST_AWNS;`
114			`end if;`
115
116			`if timerT3 < TIMER_T3_MAX then`
117			`timerT3 <= timerT3 + 1;`
118			`end if;`
119			`------------------`
120			`when ST_AWNS =>`
121			`if event2 then`
122			`current_state <= ST_AIDS;`
123			`elsif event7 then`
124			`current_state <= ST_ANRS;`
125			`end if;`
126			`------------------`
127			`when others =>`
128			`current_state <= ST_AIDS;`
129			`end case;`
130			`end if;`
131			`end process;`
132
133
134			`-- events`
135			`event1 <= ATN='1' or LACS='1' or LADS='1';`
136			`event2 <= not(ATN='1' or LACS='1' or LADS='1');`
137			`event3 <= (rdy='0' and ATN='0') or (timerT3Expired and ATN='1');`
138			`event4 <= (ATN='1' or rdy='1') and tcs='0';`
139			`event5 <= not (ATN='1' or rdy='1');`
140			`event6 <= DAV = '1';`
141			`event7 <= DAV = '0';`
142
143			`-- timers`
144			`timerT3Expired <= timerT3 >= TIMER_T3_TIMEOUT;`
145
146			`RFD <= to_stdl(`
147			`current_state = ST_AIDS or`
148			`current_state = ST_ACRS`
149			`);`
150
151			`DAC <= to_stdl(`
152			`current_state = ST_AIDS or`
153			`current_state = ST_AWNS`
154			`);`
155
156			`ACDS <= to_stdl(current_state = ST_ACDS);`
157			`ANRS <= to_stdl(current_state = ST_ANRS);`
158
159			`end Behavioral;`
160

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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_AH.vhd] - Blame information for rev 3