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--------------------------------------------------------------------------------
-- Entity:      if_func_C
-- Date:        23:00:30 10/04/2011
-- Author:      apaluch
--------------------------------------------------------------------------------
library ieee;
 
use ieee.std_logic_1164.all;
 
use work.utilPkg.all;
 
 
entity if_func_C is
        port(
                -- device inputs
                clk : in std_logic; -- clock
                pon : in std_logic; -- power on
                gts : in std_logic; -- go to standby
                rpp : in std_logic; -- request parallel poll
                tcs : in std_logic; -- take control synchronously
                tca : in std_logic; -- take control asynchronously
                sic : in std_logic; -- send interface clear
                rsc : in std_logic; -- request system control
                sre : in std_logic; -- send remote enable
                -- state inputs
                TADS : in std_logic; -- talker addressed state (T or TE)
                ACDS : in std_logic; -- accept data state (AH)
                ANRS : in std_logic; -- acceptor not ready state (AH)
                STRS : in std_logic; -- source transfer state (SH)
                SDYS : in std_logic; -- source delay state (SH)
                -- command inputs
                ATN_in : in std_logic; -- attention
                IFC_in : in std_logic; -- interface clear
                TCT_in : in std_logic; -- take control
                SRQ_in : in std_logic; -- service request
                -- command outputs
                ATN_out : out std_logic; -- attention
                IFC_out : out std_logic; -- interface clear
                TCT_out : out std_logic; -- take control
                IDY_out : out std_logic; -- identify
                REN_out : out std_logic; -- remote enable
                -- reported states
                CACS : out std_logic; -- controller active state
                CTRS : out std_logic; -- controller transfer state
                CSBS : out std_logic; -- controller standby state
                CPPS : out std_logic; -- controller parallel poll state
                CSRS : out std_logic; -- controller service requested state
                SACS : out std_logic -- system control active state
        );
end if_func_C;
 
architecture Behavioral of if_func_C is
 
        -- states
        type C_STATE_1 is (
                -- controller idle state
                ST_CIDS,
                -- controller addressed state
                ST_CADS,
                -- controller transfer state
                ST_CTRS,
                -- controller active state
                ST_CACS,
                -- controller standby state
                ST_CSBS,
                -- controllet synchronous wait state
                ST_CSWS,
                -- controller active wait state
                ST_CAWS,
                -- controller parallel poll wait state
                ST_CPWS,
                -- controller parallel poll wait state
                ST_CPPS
        );
 
        -- states
        type C_STATE_2 is (
                -- controller service not requested state
                ST_CSNS,
                -- controller service requested state
                ST_CSRS
 
        );
 
        -- states
        type C_STATE_3 is (
                -- system control interface clear idle state
                ST_SIIS,
                -- system control interface clear active state
                ST_SIAS,
                -- system control interface clear not active state
                ST_SINS
 
        );
 
        -- states
        type C_STATE_4 is (
                -- system control remote enable idle state
                ST_SRIS,
                -- system control remote enable active state
                ST_SRAS,
                -- system control remote enable not active state
                ST_SRNS
 
        );
 
        -- states
        type C_STATE_5 is (
                -- system control not active state
                ST_SNAS,
                -- system control active state
                ST_SACS
 
        );
 
        -- current state
        signal current_state_1 : C_STATE_1;
        signal current_state_2 : C_STATE_2;
        signal current_state_3 : C_STATE_3;
        signal current_state_4 : C_STATE_4;
        signal current_state_5 : C_STATE_5;
 
        -- events
        signal event1_1, event1_2, event1_3, event1_4, event1_5,
                event1_6, event1_7, event1_8, event1_9, event1_10,
                event1_11, event1_12 : boolean;
 
        signal event2_1, event2_2 : boolean;
 
        signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;
 
        signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;
 
        signal event5_1, event5_2 : boolean;
 
        -- timers
        constant TIMER_T6_TIMEOUT : integer := 110;
        constant TIMER_T7_TIMEOUT : integer := 25;
        constant TIMER_T9_TIMEOUT : integer := 75;
        constant TIMER_A_MAX : integer := 128;
        signal timer_a : integer range 0 to TIMER_A_MAX;
        signal timer_T6Expired : boolean;
        signal timer_T7Expired : boolean;
        signal timer_T9Expired : boolean;
 
        constant TIMER_T8_TIMEOUT : integer := 5000;
        constant TIMER_B_MAX : integer := 5004;
        signal timer_b : integer range 0 to TIMER_B_MAX;
        signal timer_b_1 : integer range 0 to TIMER_B_MAX;
        signal timer_T8Expired : boolean;
        signal timer_T8_1Expired : boolean;
 
 
begin
 
        -- state machine process - C_STATE_1
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_1 <= ST_CIDS;
                elsif rising_edge(clk) then
 
                        -- timer
                        if timer_a < TIMER_A_MAX then
                                timer_a <= timer_a + 1;
                        end if;
 
                        -- state machine
                        case current_state_1 is
                                ------------------
                                when ST_CIDS =>
                                        if event1_1 then
                                                -- no state change
                                        elsif event1_2 then
                                                current_state_1 <= ST_CADS;
                                        end if;
                                ------------------
                                when ST_CADS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_4 then
                                                current_state_1 <= ST_CACS;
                                        end if;
                                ------------------
                                when ST_CACS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_5 then
                                                current_state_1 <= ST_CTRS;
                                        elsif event1_6 then
                                                current_state_1 <= ST_CSBS;
                                        elsif event1_7 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CPWS;
                                        end if;
                                ------------------
                                when ST_CTRS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_3 or event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        end if;
                                ------------------
                                when ST_CSBS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_9 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CSWS;
                                        end if;
                                ------------------
                                when ST_CSWS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_10 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CAWS;
                                        end if;
                                ------------------
                                when ST_CAWS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_8 then
                                                current_state_1 <= ST_CACS;
                                        elsif event1_7 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CPWS;
                                        end if;
                                ------------------
                                when ST_CPWS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_11 then
                                                current_state_1 <= ST_CPPS;
                                        end if;
                                ------------------
                                when ST_CPPS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_12 then
                                                current_state_1 <= ST_CAWS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_1 <= ST_CIDS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_2
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_2 <= ST_CSNS;
                elsif rising_edge(clk) then
                        -- state machine
                        case current_state_2 is
                                ------------------
                                when ST_CSNS =>
                                        if event2_1 then
                                                current_state_2 <= ST_CSRS;
                                        end if;
                                ------------------
                                when ST_CSRS =>
                                        if event2_2 then
                                                current_state_2 <= ST_CSNS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_2 <= ST_CSNS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_3
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_3 <= ST_SIIS;
                elsif rising_edge(clk) then
 
                        -- timer
                        if timer_b < TIMER_B_MAX then
                                timer_b <= timer_b + 1;
                        end if;
 
                        -- state machine
                        case current_state_3 is
                                ------------------
                                when ST_SIIS =>
                                        if event3_1 then
                                                -- no state change
                                        elsif event3_2 then
                                                timer_b <= 0;
                                                current_state_3 <= ST_SIAS;
                                        elsif event3_3 then
                                                current_state_3 <= ST_SINS;
                                        end if;
                                ------------------
                                when ST_SIAS =>
                                        if event3_1 then
                                                current_state_3 <= ST_SIIS;
                                        elsif event3_5 then
                                                current_state_3 <= ST_SINS;
                                        end if;
                                ------------------
                                when ST_SINS =>
                                        if event3_1 then
                                                current_state_3 <= ST_SIIS;
                                        elsif event3_4 then
                                                current_state_3 <= ST_SIAS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_3 <= ST_SIIS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_4
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        timer_b_1 <= 0;
                        current_state_4 <= ST_SRIS;
                elsif rising_edge(clk) then
 
                        -- timer
                        if timer_b_1 < TIMER_B_MAX then
                                timer_b_1 <= timer_b_1 + 1;
                        end if;
 
                        -- state machine
                        case current_state_4 is
                                ------------------
                                when ST_SRIS =>
                                        if event4_1 then
                                                -- no state change
                                        elsif event4_2 then
                                                timer_b_1 <= 0;
                                                current_state_4 <= ST_SRAS;
                                        elsif event4_3 then
                                                current_state_4 <= ST_SRNS;
                                        end if;
                                ------------------
                                when ST_SRAS =>
                                        if event4_1 then
                                                current_state_4 <= ST_SRIS;
                                        elsif event4_5 then
                                                current_state_4 <= ST_SRNS;
                                        end if;
                                ------------------
                                when ST_SRNS =>
                                        if event4_1 then
                                                current_state_4 <= ST_SRIS;
                                        elsif event4_4 then
                                                timer_b_1 <= 0;
                                                current_state_4 <= ST_SRAS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_4 <= ST_SRIS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_5
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_5 <= ST_SNAS;
                elsif rising_edge(clk) then
                        -- state machine
                        case current_state_5 is
                                ------------------
                                when ST_SNAS =>
                                        if event5_1 then
                                                current_state_5 <= ST_SACS;
                                        end if;
                                ------------------
                                when ST_SACS =>
                                        if event5_2 then
                                                current_state_5 <= ST_SNAS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_5 <= ST_SNAS;
                        end case;
                end if;
        end process;
 
        -- events
        event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;
        event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;
        event1_3 <= STRS='0';
        event1_4 <= ATN_in='0';
        event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';
        event1_6 <= SDYS='0' and STRS='0' and gts='1';
        event1_7 <= rpp='1';
        event1_8 <= timer_T9Expired and rpp='0';
        event1_9 <= (tcs='1' and ANRS='1') or tca='1';
        event1_10 <= timer_T7Expired;
        event1_11 <= timer_T6Expired;
        event1_12 <= rpp='0';
 
        event2_1 <= SRQ_in='1';
        event2_2 <= SRQ_in='0';
 
        event3_1 <= current_state_5/=ST_SACS;
        event3_2 <= current_state_5=ST_SACS and sic='1';
        event3_3 <= current_state_5=ST_SACS and sic='0';
        event3_4 <= sic='1';
        event3_5 <= sic='0' and timer_T8Expired;
 
        event4_1 <= current_state_5/=ST_SACS;
        event4_2 <= current_state_5=ST_SACS and sre='1';
        event4_3 <= current_state_5=ST_SACS and sre='0';
        event4_4 <= sre='1';
        event4_5 <= sre='0' and timer_T8_1Expired;
 
        event5_1 <= rsc='1';
        event5_2 <= rsc='0';
 
        -- timers
        timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;
        timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;
        timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;
 
        timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;
        timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;
 
 
        CPPS <= to_stdl(current_state_1 = ST_CPPS);
        CSRS <= to_stdl(current_state_2 = ST_CSRS);
        CSBS <= to_stdl(current_state_1 = ST_CSBS);
        CACS <= to_stdl(current_state_1 = ST_CACS);
        SACS <= to_stdl(current_state_5 = ST_SACS);
 
        -- CTRS
        with current_state_1 select
                CTRS <=
                        '1' when ST_CTRS,
                        '0' when others;
 
        -- ATN
        with current_state_1 select
                ATN_out <=
                        '0' when ST_CIDS,
                        '0' when ST_CADS,
                        '0' when ST_CSBS,
                        '1' when others;
 
        -- IDY_out
        with current_state_1 select
                IDY_out <=
                        '1' when ST_CPWS,
                        '1' when ST_CPPS,
                        '0' when others;
 
        -- TCT
        with current_state_1 select
                TCT_out <=
                        '1' when ST_CTRS,
                        '0' when others;
 
        -- IFC
        with current_state_3 select
                IFC_out <=
                        '1' when ST_SIAS,
                        '0' when others;
 
        -- REN
        with current_state_4 select
                REN_out <=
                        '1' when ST_SRAS,
                        '0' when others;
 
end Behavioral;
 

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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_C.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2			`-- Entity: if_func_C`
3			`-- Date: 23:00:30 10/04/2011`
4			`-- Author: apaluch`
5			`--------------------------------------------------------------------------------`
6			`library ieee;`
7
8			`use ieee.std_logic_1164.all;`
9
10			`use work.utilPkg.all;`
11
12
13			`entity if_func_C is`
14			`port(`
15			`-- device inputs`
16			`clk : in std_logic; -- clock`
17			`pon : in std_logic; -- power on`
18			`gts : in std_logic; -- go to standby`
19			`rpp : in std_logic; -- request parallel poll`
20			`tcs : in std_logic; -- take control synchronously`
21			`tca : in std_logic; -- take control asynchronously`
22			`sic : in std_logic; -- send interface clear`
23			`rsc : in std_logic; -- request system control`
24			`sre : in std_logic; -- send remote enable`
25			`-- state inputs`
26			`TADS : in std_logic; -- talker addressed state (T or TE)`
27			`ACDS : in std_logic; -- accept data state (AH)`
28			`ANRS : in std_logic; -- acceptor not ready state (AH)`
29			`STRS : in std_logic; -- source transfer state (SH)`
30			`SDYS : in std_logic; -- source delay state (SH)`
31			`-- command inputs`
32			`ATN_in : in std_logic; -- attention`
33			`IFC_in : in std_logic; -- interface clear`
34			`TCT_in : in std_logic; -- take control`
35			`SRQ_in : in std_logic; -- service request`
36			`-- command outputs`
37			`ATN_out : out std_logic; -- attention`
38			`IFC_out : out std_logic; -- interface clear`
39			`TCT_out : out std_logic; -- take control`
40			`IDY_out : out std_logic; -- identify`
41			`REN_out : out std_logic; -- remote enable`
42			`-- reported states`
43			`CACS : out std_logic; -- controller active state`
44			`CTRS : out std_logic; -- controller transfer state`
45			`CSBS : out std_logic; -- controller standby state`
46			`CPPS : out std_logic; -- controller parallel poll state`
47			`CSRS : out std_logic; -- controller service requested state`
48			`SACS : out std_logic -- system control active state`
49			`);`
50			`end if_func_C;`
51
52			`architecture Behavioral of if_func_C is`
53
54			`-- states`
55			`type C_STATE_1 is (`
56			`-- controller idle state`
57			`ST_CIDS,`
58			`-- controller addressed state`
59			`ST_CADS,`
60			`-- controller transfer state`
61			`ST_CTRS,`
62			`-- controller active state`
63			`ST_CACS,`
64			`-- controller standby state`
65			`ST_CSBS,`
66			`-- controllet synchronous wait state`
67			`ST_CSWS,`
68			`-- controller active wait state`
69			`ST_CAWS,`
70			`-- controller parallel poll wait state`
71			`ST_CPWS,`
72			`-- controller parallel poll wait state`
73			`ST_CPPS`
74			`);`
75
76			`-- states`
77			`type C_STATE_2 is (`
78			`-- controller service not requested state`
79			`ST_CSNS,`
80			`-- controller service requested state`
81			`ST_CSRS`
82
83			`);`
84
85			`-- states`
86			`type C_STATE_3 is (`
87			`-- system control interface clear idle state`
88			`ST_SIIS,`
89			`-- system control interface clear active state`
90			`ST_SIAS,`
91			`-- system control interface clear not active state`
92			`ST_SINS`
93
94			`);`
95
96			`-- states`
97			`type C_STATE_4 is (`
98			`-- system control remote enable idle state`
99			`ST_SRIS,`
100			`-- system control remote enable active state`
101			`ST_SRAS,`
102			`-- system control remote enable not active state`
103			`ST_SRNS`
104
105			`);`
106
107			`-- states`
108			`type C_STATE_5 is (`
109			`-- system control not active state`
110			`ST_SNAS,`
111			`-- system control active state`
112			`ST_SACS`
113
114			`);`
115
116			`-- current state`
117			`signal current_state_1 : C_STATE_1;`
118			`signal current_state_2 : C_STATE_2;`
119			`signal current_state_3 : C_STATE_3;`
120			`signal current_state_4 : C_STATE_4;`
121			`signal current_state_5 : C_STATE_5;`
122
123			`-- events`
124			`signal event1_1, event1_2, event1_3, event1_4, event1_5,`
125			`event1_6, event1_7, event1_8, event1_9, event1_10,`
126			`event1_11, event1_12 : boolean;`
127
128			`signal event2_1, event2_2 : boolean;`
129
130			`signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;`
131
132			`signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;`
133
134			`signal event5_1, event5_2 : boolean;`
135
136			`-- timers`
137			`constant TIMER_T6_TIMEOUT : integer := 110;`
138			`constant TIMER_T7_TIMEOUT : integer := 25;`
139			`constant TIMER_T9_TIMEOUT : integer := 75;`
140			`constant TIMER_A_MAX : integer := 128;`
141			`signal timer_a : integer range 0 to TIMER_A_MAX;`
142			`signal timer_T6Expired : boolean;`
143			`signal timer_T7Expired : boolean;`
144			`signal timer_T9Expired : boolean;`
145
146			`constant TIMER_T8_TIMEOUT : integer := 5000;`
147			`constant TIMER_B_MAX : integer := 5004;`
148			`signal timer_b : integer range 0 to TIMER_B_MAX;`
149			`signal timer_b_1 : integer range 0 to TIMER_B_MAX;`
150			`signal timer_T8Expired : boolean;`
151			`signal timer_T8_1Expired : boolean;`
152
153
154			`begin`
155
156			`-- state machine process - C_STATE_1`
157			`process(pon, clk) begin`
158			`-- async reset`
159			`if pon='1' then`
160			`current_state_1 <= ST_CIDS;`
161			`elsif rising_edge(clk) then`
162
163			`-- timer`
164			`if timer_a < TIMER_A_MAX then`
165			`timer_a <= timer_a + 1;`
166			`end if;`
167
168			`-- state machine`
169			`case current_state_1 is`
170			`------------------`
171			`when ST_CIDS =>`
172			`if event1_1 then`
173			`-- no state change`
174			`elsif event1_2 then`
175			`current_state_1 <= ST_CADS;`
176			`end if;`
177			`------------------`
178			`when ST_CADS =>`
179			`if event1_1 then`
180			`current_state_1 <= ST_CIDS;`
181			`elsif event1_4 then`
182			`current_state_1 <= ST_CACS;`
183			`end if;`
184			`------------------`
185			`when ST_CACS =>`
186			`if event1_1 then`
187			`current_state_1 <= ST_CIDS;`
188			`elsif event1_5 then`
189			`current_state_1 <= ST_CTRS;`
190			`elsif event1_6 then`
191			`current_state_1 <= ST_CSBS;`
192			`elsif event1_7 then`
193			`timer_a <= 0;`
194			`current_state_1 <= ST_CPWS;`
195			`end if;`
196			`------------------`
197			`when ST_CTRS =>`
198			`if event1_1 then`
199			`current_state_1 <= ST_CIDS;`
200			`elsif event1_3 or event1_1 then`
201			`current_state_1 <= ST_CIDS;`
202			`end if;`
203			`------------------`
204			`when ST_CSBS =>`
205			`if event1_1 then`
206			`current_state_1 <= ST_CIDS;`
207			`elsif event1_9 then`
208			`timer_a <= 0;`
209			`current_state_1 <= ST_CSWS;`
210			`end if;`
211			`------------------`
212			`when ST_CSWS =>`
213			`if event1_1 then`
214			`current_state_1 <= ST_CIDS;`
215			`elsif event1_10 then`
216			`timer_a <= 0;`
217			`current_state_1 <= ST_CAWS;`
218			`end if;`
219			`------------------`
220			`when ST_CAWS =>`
221			`if event1_1 then`
222			`current_state_1 <= ST_CIDS;`
223			`elsif event1_8 then`
224			`current_state_1 <= ST_CACS;`
225			`elsif event1_7 then`
226			`timer_a <= 0;`
227			`current_state_1 <= ST_CPWS;`
228			`end if;`
229			`------------------`
230			`when ST_CPWS =>`
231			`if event1_1 then`
232			`current_state_1 <= ST_CIDS;`
233			`elsif event1_11 then`
234			`current_state_1 <= ST_CPPS;`
235			`end if;`
236			`------------------`
237			`when ST_CPPS =>`
238			`if event1_1 then`
239			`current_state_1 <= ST_CIDS;`
240			`elsif event1_12 then`
241			`current_state_1 <= ST_CAWS;`
242			`end if;`
243			`------------------`
244			`when others =>`
245			`current_state_1 <= ST_CIDS;`
246			`end case;`
247			`end if;`
248			`end process;`
249
250			`-- state machine process - C_STATE_2`
251			`process(pon, clk) begin`
252			`-- async reset`
253			`if pon='1' then`
254			`current_state_2 <= ST_CSNS;`
255			`elsif rising_edge(clk) then`
256			`-- state machine`
257			`case current_state_2 is`
258			`------------------`
259			`when ST_CSNS =>`
260			`if event2_1 then`
261			`current_state_2 <= ST_CSRS;`
262			`end if;`
263			`------------------`
264			`when ST_CSRS =>`
265			`if event2_2 then`
266			`current_state_2 <= ST_CSNS;`
267			`end if;`
268			`------------------`
269			`when others =>`
270			`current_state_2 <= ST_CSNS;`
271			`end case;`
272			`end if;`
273			`end process;`
274
275			`-- state machine process - C_STATE_3`
276			`process(pon, clk) begin`
277			`-- async reset`
278			`if pon='1' then`
279			`current_state_3 <= ST_SIIS;`
280			`elsif rising_edge(clk) then`
281
282			`-- timer`
283			`if timer_b < TIMER_B_MAX then`
284			`timer_b <= timer_b + 1;`
285			`end if;`
286
287			`-- state machine`
288			`case current_state_3 is`
289			`------------------`
290			`when ST_SIIS =>`
291			`if event3_1 then`
292			`-- no state change`
293			`elsif event3_2 then`
294			`timer_b <= 0;`
295			`current_state_3 <= ST_SIAS;`
296			`elsif event3_3 then`
297			`current_state_3 <= ST_SINS;`
298			`end if;`
299			`------------------`
300			`when ST_SIAS =>`
301			`if event3_1 then`
302			`current_state_3 <= ST_SIIS;`
303			`elsif event3_5 then`
304			`current_state_3 <= ST_SINS;`
305			`end if;`
306			`------------------`
307			`when ST_SINS =>`
308			`if event3_1 then`
309			`current_state_3 <= ST_SIIS;`
310			`elsif event3_4 then`
311			`current_state_3 <= ST_SIAS;`
312			`end if;`
313			`------------------`
314			`when others =>`
315			`current_state_3 <= ST_SIIS;`
316			`end case;`
317			`end if;`
318			`end process;`
319
320			`-- state machine process - C_STATE_4`
321			`process(pon, clk) begin`
322			`-- async reset`
323			`if pon='1' then`
324			`timer_b_1 <= 0;`
325			`current_state_4 <= ST_SRIS;`
326			`elsif rising_edge(clk) then`
327
328			`-- timer`
329			`if timer_b_1 < TIMER_B_MAX then`
330			`timer_b_1 <= timer_b_1 + 1;`
331			`end if;`
332
333			`-- state machine`
334			`case current_state_4 is`
335			`------------------`
336			`when ST_SRIS =>`
337			`if event4_1 then`
338			`-- no state change`
339			`elsif event4_2 then`
340			`timer_b_1 <= 0;`
341			`current_state_4 <= ST_SRAS;`
342			`elsif event4_3 then`
343			`current_state_4 <= ST_SRNS;`
344			`end if;`
345			`------------------`
346			`when ST_SRAS =>`
347			`if event4_1 then`
348			`current_state_4 <= ST_SRIS;`
349			`elsif event4_5 then`
350			`current_state_4 <= ST_SRNS;`
351			`end if;`
352			`------------------`
353			`when ST_SRNS =>`
354			`if event4_1 then`
355			`current_state_4 <= ST_SRIS;`
356			`elsif event4_4 then`
357			`timer_b_1 <= 0;`
358			`current_state_4 <= ST_SRAS;`
359			`end if;`
360			`------------------`
361			`when others =>`
362			`current_state_4 <= ST_SRIS;`
363			`end case;`
364			`end if;`
365			`end process;`
366
367			`-- state machine process - C_STATE_5`
368			`process(pon, clk) begin`
369			`-- async reset`
370			`if pon='1' then`
371			`current_state_5 <= ST_SNAS;`
372			`elsif rising_edge(clk) then`
373			`-- state machine`
374			`case current_state_5 is`
375			`------------------`
376			`when ST_SNAS =>`
377			`if event5_1 then`
378			`current_state_5 <= ST_SACS;`
379			`end if;`
380			`------------------`
381			`when ST_SACS =>`
382			`if event5_2 then`
383			`current_state_5 <= ST_SNAS;`
384			`end if;`
385			`------------------`
386			`when others =>`
387			`current_state_5 <= ST_SNAS;`
388			`end case;`
389			`end if;`
390			`end process;`
391
392			`-- events`
393			`event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;`
394			`event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;`
395			`event1_3 <= STRS='0';`
396			`event1_4 <= ATN_in='0';`
397			`event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';`
398			`event1_6 <= SDYS='0' and STRS='0' and gts='1';`
399			`event1_7 <= rpp='1';`
400			`event1_8 <= timer_T9Expired and rpp='0';`
401			`event1_9 <= (tcs='1' and ANRS='1') or tca='1';`
402			`event1_10 <= timer_T7Expired;`
403			`event1_11 <= timer_T6Expired;`
404			`event1_12 <= rpp='0';`
405
406			`event2_1 <= SRQ_in='1';`
407			`event2_2 <= SRQ_in='0';`
408
409			`event3_1 <= current_state_5/=ST_SACS;`
410			`event3_2 <= current_state_5=ST_SACS and sic='1';`
411			`event3_3 <= current_state_5=ST_SACS and sic='0';`
412			`event3_4 <= sic='1';`
413			`event3_5 <= sic='0' and timer_T8Expired;`
414
415			`event4_1 <= current_state_5/=ST_SACS;`
416			`event4_2 <= current_state_5=ST_SACS and sre='1';`
417			`event4_3 <= current_state_5=ST_SACS and sre='0';`
418			`event4_4 <= sre='1';`
419			`event4_5 <= sre='0' and timer_T8_1Expired;`
420
421			`event5_1 <= rsc='1';`
422			`event5_2 <= rsc='0';`
423
424			`-- timers`
425			`timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;`
426			`timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;`
427			`timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;`
428
429			`timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;`
430			`timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;`
431
432
433			`CPPS <= to_stdl(current_state_1 = ST_CPPS);`
434			`CSRS <= to_stdl(current_state_2 = ST_CSRS);`
435			`CSBS <= to_stdl(current_state_1 = ST_CSBS);`
436			`CACS <= to_stdl(current_state_1 = ST_CACS);`
437			`SACS <= to_stdl(current_state_5 = ST_SACS);`
438
439			`-- CTRS`
440			`with current_state_1 select`
441			`CTRS <=`
442			`'1' when ST_CTRS,`
443			`'0' when others;`
444
445			`-- ATN`
446			`with current_state_1 select`
447			`ATN_out <=`
448			`'0' when ST_CIDS,`
449			`'0' when ST_CADS,`
450			`'0' when ST_CSBS,`
451			`'1' when others;`
452
453			`-- IDY_out`
454			`with current_state_1 select`
455			`IDY_out <=`
456			`'1' when ST_CPWS,`
457			`'1' when ST_CPPS,`
458			`'0' when others;`
459
460			`-- TCT`
461			`with current_state_1 select`
462			`TCT_out <=`
463			`'1' when ST_CTRS,`
464			`'0' when others;`
465
466			`-- IFC`
467			`with current_state_3 select`
468			`IFC_out <=`
469			`'1' when ST_SIAS,`
470			`'0' when others;`
471
472			`-- REN`
473			`with current_state_4 select`
474			`REN_out <=`
475			`'1' when ST_SRAS,`
476			`'0' when others;`
477
478			`end Behavioral;`
479