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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_L_LE.vhd] - Blame information for rev 3

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--------------------------------------------------------------------------------
-- Entity:      if_func_L_LE
-- Date:        01:04:57 10/01/2011
-- Author:      apaluch
--------------------------------------------------------------------------------
library IEEE;
 
use ieee.std_logic_1164.all;
 
use work.utilPkg.all;
 
 
entity if_func_L_LE is
        port(
                -- clock
                clk : in std_logic; -- clock
                -- function settings
                isLE : in std_logic;
                -- local commands
                pon : in std_logic; -- power on
                ltn : in std_logic; -- listen
                lun : in std_logic; -- local unlisten
                lon : in std_logic; -- listen only
                -- state inputs
                ACDS : in std_logic; -- accept data state (AH)
                CACS : in std_logic; -- controller active state (C)
                TPAS : in std_logic; -- talker primary address state (T)
                -- remote commands
                ATN : in std_logic; -- attention
                IFC : in std_logic; -- interface clear
                MLA : in std_logic; -- my listen address
                MTA : in std_logic; -- my talk address
                UNL : in std_logic; -- unlisten
                PCG : in std_logic; -- primary command group
                MSA : in std_logic; -- my secondary address
                -- reported states
                LACS : out std_logic; -- listener active state
                LADS : out std_logic; -- listener addressed state
                LPAS : out std_logic -- listener primary addressed state
                ;debug1 : out std_logic
        );
end if_func_L_LE;
 
architecture Behavioral of if_func_L_LE is
 
        -- states
        type LE_STATE_1 is (
                -- listener idle state
                ST_LIDS,
                -- listener addressed state
                ST_LADS,
                -- listener active state
                ST_LACS
        );
 
        -- states
        type LE_STATE_2 is (
                -- listener primary idle state
                ST_LPIS,
                -- listener primary addressed state
                ST_LPAS
        );
 
        -- current state
        signal current_state_1 : LE_STATE_1;
        signal current_state_2 : LE_STATE_2;
 
        -- predicates
        signal event0, event1, event2, event3, event4 : boolean;
 
begin
 
        debug1 <= to_stdl(current_state_1 = ST_LACS) or
                to_stdl(current_state_1 = ST_LADS);
 
        -- state machine process - L_STATE_1
        process(pon, clk) begin
        if pon = '1' then
                        current_state_1 <= ST_LIDS;
                elsif rising_edge(clk) then
                        case current_state_1 is
                                ------------------
                                when ST_LIDS =>
                                        if event0 then
                                                -- no state change
                                        elsif event1 then
                                                current_state_1 <= ST_LADS;
                                        end if;
                                ------------------
                                when ST_LADS =>
                                        if event0 then
                                                current_state_1 <= ST_LIDS;
                                        elsif event2 then
                                                current_state_1 <= ST_LIDS;
                                        elsif ATN='0' then
                                                current_state_1 <= ST_LACS;
                                        end if;
                                ------------------
                                when ST_LACS =>
                                        if event0 then
                                                current_state_1 <= ST_LIDS;
                                        elsif ATN='1' then
                                                current_state_1 <= ST_LADS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_1 <= ST_LIDS;
                        end case;
                end if;
        end process;
 
        -- state machine process - L_STATE_2
        process(pon, clk) begin
                if pon = '1' then
                        current_state_2 <= ST_LPIS;
                elsif rising_edge(clk) then
                        case current_state_2 is
                                ------------------
                                when ST_LPIS =>
                                        if event0 then
                                                -- no state change
                                        elsif event3 then
                                                current_state_2 <= ST_LPAS;
                                        end if;
                                ------------------
                                when ST_LPAS =>
                                        if event0 then
                                                current_state_2 <= ST_LPIS;
                                        elsif event4 then
                                                current_state_2 <= ST_LPIS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_2 <= ST_LPIS;
                        end case;
                end if;
        end process;
 
        -- events
        event0 <= IFC='1';
 
        event1 <= (isLE='1' and (
                                lon='1' or (ltn='1' and CACS='1') or
                                (MSA='1' and current_state_2=ST_LPAS and ACDS='1')
                        )) or
                        (isLE='0' and (
                                lon='1' or (MLA='1' and ACDS='1') or (ltn='1' and CACS='1')
                        ));
 
        event2 <= (isLE='1' and (
                                (UNL='1' and ACDS='1') or
                                (lun='1' and CACS='1') or
                                (MSA='1' and TPAS='1' and ACDS='1')
                        )) or
                        (isLE='0' and (
                                (UNL='1' and ACDS='1') or
                                (MTA='1' and ACDS='1') or
                                (lun='1' and CACS='1')
                        ));
 
        event3 <= MLA='1' and ACDS='1';
        event4 <= PCG='1' and MLA='0' and ACDS='1';
 
        LACS <= to_stdl(current_state_1 = ST_LACS);
        LADS <= to_stdl(current_state_1 = ST_LADS);
        LPAS <= to_stdl(current_state_2 = ST_LPAS);
 
end Behavioral;

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2			`-- Entity: if_func_L_LE`
3			`-- Date: 01:04:57 10/01/2011`
4			`-- Author: apaluch`
5			`--------------------------------------------------------------------------------`
6			`library IEEE;`
7
8			`use ieee.std_logic_1164.all;`
9
10			`use work.utilPkg.all;`
11
12
13			`entity if_func_L_LE is`
14			`port(`
15			`-- clock`
16			`clk : in std_logic; -- clock`
17			`-- function settings`
18			`isLE : in std_logic;`
19			`-- local commands`
20			`pon : in std_logic; -- power on`
21			`ltn : in std_logic; -- listen`
22			`lun : in std_logic; -- local unlisten`
23			`lon : in std_logic; -- listen only`
24			`-- state inputs`
25			`ACDS : in std_logic; -- accept data state (AH)`
26			`CACS : in std_logic; -- controller active state (C)`
27			`TPAS : in std_logic; -- talker primary address state (T)`
28			`-- remote commands`
29			`ATN : in std_logic; -- attention`
30			`IFC : in std_logic; -- interface clear`
31			`MLA : in std_logic; -- my listen address`
32			`MTA : in std_logic; -- my talk address`
33			`UNL : in std_logic; -- unlisten`
34			`PCG : in std_logic; -- primary command group`
35			`MSA : in std_logic; -- my secondary address`
36			`-- reported states`
37			`LACS : out std_logic; -- listener active state`
38			`LADS : out std_logic; -- listener addressed state`
39			`LPAS : out std_logic -- listener primary addressed state`
40			`;debug1 : out std_logic`
41			`);`
42			`end if_func_L_LE;`
43
44			`architecture Behavioral of if_func_L_LE is`
45
46			`-- states`
47			`type LE_STATE_1 is (`
48			`-- listener idle state`
49			`ST_LIDS,`
50			`-- listener addressed state`
51			`ST_LADS,`
52			`-- listener active state`
53			`ST_LACS`
54			`);`
55
56			`-- states`
57			`type LE_STATE_2 is (`
58			`-- listener primary idle state`
59			`ST_LPIS,`
60			`-- listener primary addressed state`
61			`ST_LPAS`
62			`);`
63
64			`-- current state`
65			`signal current_state_1 : LE_STATE_1;`
66			`signal current_state_2 : LE_STATE_2;`
67
68			`-- predicates`
69			`signal event0, event1, event2, event3, event4 : boolean;`
70
71			`begin`
72
73			`debug1 <= to_stdl(current_state_1 = ST_LACS) or`
74			`to_stdl(current_state_1 = ST_LADS);`
75
76			`-- state machine process - L_STATE_1`
77			`process(pon, clk) begin`
78			`if pon = '1' then`
79			`current_state_1 <= ST_LIDS;`
80			`elsif rising_edge(clk) then`
81			`case current_state_1 is`
82			`------------------`
83			`when ST_LIDS =>`
84			`if event0 then`
85			`-- no state change`
86			`elsif event1 then`
87			`current_state_1 <= ST_LADS;`
88			`end if;`
89			`------------------`
90			`when ST_LADS =>`
91			`if event0 then`
92			`current_state_1 <= ST_LIDS;`
93			`elsif event2 then`
94			`current_state_1 <= ST_LIDS;`
95			`elsif ATN='0' then`
96			`current_state_1 <= ST_LACS;`
97			`end if;`
98			`------------------`
99			`when ST_LACS =>`
100			`if event0 then`
101			`current_state_1 <= ST_LIDS;`
102			`elsif ATN='1' then`
103			`current_state_1 <= ST_LADS;`
104			`end if;`
105			`------------------`
106			`when others =>`
107			`current_state_1 <= ST_LIDS;`
108			`end case;`
109			`end if;`
110			`end process;`
111
112			`-- state machine process - L_STATE_2`
113			`process(pon, clk) begin`
114			`if pon = '1' then`
115			`current_state_2 <= ST_LPIS;`
116			`elsif rising_edge(clk) then`
117			`case current_state_2 is`
118			`------------------`
119			`when ST_LPIS =>`
120			`if event0 then`
121			`-- no state change`
122			`elsif event3 then`
123			`current_state_2 <= ST_LPAS;`
124			`end if;`
125			`------------------`
126			`when ST_LPAS =>`
127			`if event0 then`
128			`current_state_2 <= ST_LPIS;`
129			`elsif event4 then`
130			`current_state_2 <= ST_LPIS;`
131			`end if;`
132			`------------------`
133			`when others =>`
134			`current_state_2 <= ST_LPIS;`
135			`end case;`
136			`end if;`
137			`end process;`
138
139			`-- events`
140			`event0 <= IFC='1';`
141
142			`event1 <= (isLE='1' and (`
143			`lon='1' or (ltn='1' and CACS='1') or`
144			`(MSA='1' and current_state_2=ST_LPAS and ACDS='1')`
145			`)) or`
146			`(isLE='0' and (`
147			`lon='1' or (MLA='1' and ACDS='1') or (ltn='1' and CACS='1')`
148			`));`
149
150			`event2 <= (isLE='1' and (`
151			`(UNL='1' and ACDS='1') or`
152			`(lun='1' and CACS='1') or`
153			`(MSA='1' and TPAS='1' and ACDS='1')`
154			`)) or`
155			`(isLE='0' and (`
156			`(UNL='1' and ACDS='1') or`
157			`(MTA='1' and ACDS='1') or`
158			`(lun='1' and CACS='1')`
159			`));`
160
161			`event3 <= MLA='1' and ACDS='1';`
162			`event4 <= PCG='1' and MLA='0' and ACDS='1';`
163
164			`LACS <= to_stdl(current_state_1 = ST_LACS);`
165			`LADS <= to_stdl(current_state_1 = ST_LADS);`
166			`LPAS <= to_stdl(current_state_2 = ST_LPAS);`
167
168			`end Behavioral;`

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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_L_LE.vhd] - Blame information for rev 3