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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_SH.vhd] - Blame information for rev 3

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1 3 Andrewski 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    01:04:57 10/01/2011
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-- Design Name:
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-- Module Name:    if_func_SH - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.utilPkg.all;
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entity if_func_SH is
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        port(
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                -- device inputs
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                clk : in std_logic; -- clock
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                -- settingd
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                T1 : in std_logic_vector (7 downto 0);
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                -- local commands
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                pon : in std_logic; -- power on
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                nba : in std_logic; -- new byte available
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                -- state inputs
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                TACS : in std_logic; -- talker active state
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                SPAS : in std_logic; -- seriall poll active state
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                CACS : in std_logic; -- controller active state
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                CTRS : in std_logic; -- controller transfer state
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                -- interface inputs
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                ATN : in std_logic; -- attention
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                DAC : in std_logic; -- data accepted
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                RFD : in std_logic; -- ready for data
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                -- remote instructions
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                DAV : out std_logic; -- data address valid
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                -- device outputs
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                wnc : out std_logic; -- wait for new cycle
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                -- reported states
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                STRS : out std_logic; -- source transfer state
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                SDYS : out std_logic -- source delay state
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        );
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end if_func_SH;
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architecture Behavioral of if_func_SH is
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 -- states
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 type SH_STATE is (
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  -- source idle state
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  ST_SIDS,
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  -- source generate state
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  ST_SGNS,
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  -- source delay state
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  ST_SDYS,
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  -- source transfer state
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  ST_STRS,
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  -- source wait for new cycle state
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  ST_SWNS,
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  -- source idle wait state
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  ST_SIWS
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 );
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        -- current state
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        signal current_state : SH_STATE;
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        -- predicates
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        signal pred1 : boolean;
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        signal pred2 : boolean;
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        -- timers
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        constant TIMER_T1_MAX : integer := 255;
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        signal timerT1 : integer range 0 to TIMER_T1_MAX;
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        signal timerT1Expired : boolean;
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begin
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        -- state machine process
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        process(pon, clk) begin
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                if pon = '1' then
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                        current_state <= ST_SIDS;
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                elsif rising_edge(clk) then
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                        case current_state is
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                                ------------------
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                                when ST_SIDS =>
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                                        if pred1 then
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                                                current_state <= ST_SGNS;
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                                        end if;
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                                ------------------
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                                when ST_SGNS =>
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                                        if nba='1' then
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                                                timerT1 <= 0;
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                                                current_state <= ST_SDYS;
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                                        elsif pred2 then
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                                                current_state <= ST_SIDS;
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                                        end if;
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                                ------------------
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                                when ST_SDYS =>
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                                        if pred2 then
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                                                current_state <= ST_SIDS;
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                                        elsif RFD='1' and timerT1Expired then
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                                                current_state <= ST_STRS;
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                                        end if;
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                                        if timerT1 < TIMER_T1_MAX then
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                                                timerT1 <= timerT1 + 1;
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                                        end if;
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                                ------------------
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                                when ST_STRS =>
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                                        if DAC='1' then
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                                                current_state <= ST_SWNS;
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                                        elsif pred2 then
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                                                current_state <= ST_SIWS;
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                                        end if;
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                                ------------------
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                                when ST_SWNS =>
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                                        if nba='0' then
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                                                current_state <= ST_SGNS;
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                                        elsif pred2 then
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                                                current_state <= ST_SIWS;
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                                        end if;
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                                ------------------
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                                when ST_SIWS =>
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                                        if nba='0' then
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                                                current_state <= ST_SIDS;
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                                        elsif pred1 then
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                                                current_state <= ST_SWNS;
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                                        end if;
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                                ------------------
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                                when others =>
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                                        current_state <= ST_SIDS;
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                        end case;
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                end if;
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        end process;
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        -- events
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        pred1 <= TACS='1' or SPAS='1' or CACS='1';
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        pred2 <= (ATN='1' and not(CACS='1' or CTRS='1')) or
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                         (ATN='0' and not(TACS='1' or SPAS='1'));
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        -- timers
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        timerT1Expired <= timerT1 >= conv_integer(UNSIGNED(T1));
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        -- DAV command
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        DAV <= to_stdl(current_state = ST_STRS);
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        -- wnc command
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        wnc <= to_stdl(current_state = ST_SWNS);
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        -- STRS command
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        STRS <= to_stdl(current_state = ST_STRS);
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        -- SDYS command
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        SDYS <= to_stdl(current_state = ST_SDYS);
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end Behavioral;
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