OpenCores
URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib_helper/] [GpibSynchronizer.vhd] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2
-- Entity: GpibSynchronizer
3
-- Date:2012-02-06  
4
-- Author: andrzej     
5
--
6
-- Description ${cursor}
7
--------------------------------------------------------------------------------
8
library ieee;
9
use ieee.std_logic_1164.all;
10
use ieee.std_logic_unsigned.all;
11
 
12
 
13
entity GpibSynchronizer is
14
        port (
15
                -- clk
16
                clk : std_logic;
17
                -- DIO
18
                DI : in std_logic_vector (7 downto 0);
19
                DO : out std_logic_vector (7 downto 0);
20
                -- attention
21
                ATN_in : in std_logic;
22
                ATN_out : out std_logic;
23
                -- data valid
24
                DAV_in : in std_logic;
25
                DAV_out : out std_logic;
26
                -- not ready for data
27
                NRFD_in : in std_logic;
28
                NRFD_out : out std_logic;
29
                -- no data accepted
30
                NDAC_in : in std_logic;
31
                NDAC_out : out std_logic;
32
                -- end or identify
33
                EOI_in : in std_logic;
34
                EOI_out : out std_logic;
35
                -- service request
36
                SRQ_in : in std_logic;
37
                SRQ_out : out std_logic;
38
                -- interface clear
39
                IFC_in : in std_logic;
40
                IFC_out : out std_logic;
41
                -- remote enable
42
                REN_in : in std_logic;
43
                REN_out : out std_logic
44
        );
45
end GpibSynchronizer;
46
 
47
architecture arch of GpibSynchronizer is
48
 
49
begin
50
 
51
        process(clk) begin
52
                if rising_edge(clk) then
53
 
54
                        DO <= DI;
55
 
56
                        ATN_out <= ATN_in;
57
 
58
                        DAV_out <= DAV_in;
59
 
60
                        NRFD_out <= NRFD_in;
61
 
62
                        NDAC_out <= NDAC_in;
63
 
64
                        EOI_out <= EOI_in;
65
 
66
                        SRQ_out <= SRQ_in;
67
 
68
                        IFC_out <= IFC_in;
69
 
70
                        REN_out <= REN_in;
71
                end if;
72
        end process;
73
 
74
end arch;
75
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.