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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib_helper/] [MemoryBlock.vhd] - Blame information for rev 13

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1 3 Andrewski 
--------------------------------------------------------------------------------
2 13 Andrewski 
--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
17 3 Andrewski 
-- Entity: MemoryBlock
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-- Date:2011-11-14
19 13 Andrewski 
-- Author: Andrzej Paluch
20 3 Andrewski 
--
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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use work.utilPkg.all;
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use work.helperComponents.all;
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entity MemoryBlock is
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        port (
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                reset : in std_logic;
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                clk : in std_logic;
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                -------------------------------------------------
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                p1_addr : in std_logic_vector(10 downto 0);
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                p1_data_in : in std_logic_vector(7 downto 0);
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                p1_strobe : in std_logic;
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                p1_data_out : out std_logic_vector(7 downto 0);
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                -------------------------------------------------
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                p2_addr : in std_logic_vector(10 downto 0);
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                p2_data_in : in std_logic_vector(7 downto 0);
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                p2_strobe : in std_logic;
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                p2_data_out : out std_logic_vector(7 downto 0)
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        );
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end MemoryBlock;
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architecture arch of MemoryBlock is
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        constant ADDR_WIDTH : integer := 11;
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        constant DATA_WIDTH : integer := 8;
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        signal m_p1_parity_in, m_p1_parity_out : std_logic_vector(0 downto 0);
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        signal m_p1_data_in, m_p1_data_out :
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                std_logic_vector((DATA_WIDTH-1) downto 0);
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        signal m_p1_addr : std_logic_vector((ADDR_WIDTH-1) downto 0);
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        signal m_p1_clk, m_p1_en, m_p1_ssr, m_p1_we : std_logic;
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        signal m_p2_parity_in, m_p2_parity_out : std_logic_vector(0 downto 0);
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        signal m_p2_data_in, m_p2_data_out :
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                std_logic_vector((DATA_WIDTH-1) downto 0);
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        signal m_p2_addr : std_logic_vector((ADDR_WIDTH-1) downto 0);
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        signal m_p2_clk, m_p2_en, m_p2_ssr, m_p2_we : std_logic;
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begin
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        m_p1_en <= '1';
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        m_p2_en <= '1';
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        m_p1_ssr <= reset;
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        m_p2_ssr <= reset;
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        m_p1_addr <= p1_addr;
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        m_p2_addr <= p2_addr;
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        p1_data_out <= m_p1_data_out;
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        p2_data_out <= m_p2_data_out;
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        m_p1_data_in <= p1_data_in;
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        m_p2_data_in <= p2_data_in;
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        m_p1_clk <= clk;
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        m_p2_clk <= clk;
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        m_p1_we <= p1_strobe;
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        m_p2_we <= p2_strobe;
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        -- RAMB16_S9_S9: Virtex-II/II-Pro, Spartan-3/3E 2k x 8 + 1 Parity bit Dual-Port RAM
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        -- Xilinx HDL Language Template, version 9.1i
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        RAMB16_S9_S9_inst : RAMB16_S9_S9
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        generic map (
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                INIT_A => X"000", --  Value of output RAM registers on Port A at startup
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                INIT_B => X"000", --  Value of output RAM registers on Port B at startup
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                SRVAL_A => X"000", --  Port A ouput value upon SSR assertion
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                SRVAL_B => X"000", --  Port B ouput value upon SSR assertion
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                WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
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                WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
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                SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
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                -- The following INIT_xx declarations specify the initial contents of the RAM
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                -- Address 0 to 511
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                INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- Address 512 to 1023
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                INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- Address 1024 to 1535
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                INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- Address 1536 to 2047
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                INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- The next set of INITP_xx are for the parity bits
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                -- Address 0 to 511
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                INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- Address 512 to 1023
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                INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- Address 1024 to 1535
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                INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                -- Address 1536 to 2047
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                INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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                INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
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        port map (
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                DOA => m_p1_data_out,           -- Port A 8-bit Data Output
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                DOB => m_p2_data_out,           -- Port B 8-bit Data Output
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                DOPA => m_p1_parity_out,         -- Port A 1-bit Parity Output
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                DOPB => m_p2_parity_out,         -- Port B 1-bit Parity Output
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                ADDRA => m_p1_addr,  -- Port A 11-bit Address Input
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                ADDRB => m_p2_addr,  -- Port B 11-bit Address Input
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                CLKA => m_p1_clk,        -- Port A Clock
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                CLKB => m_p2_clk,        -- Port B Clock
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                DIA => m_p1_data_in,            -- Port A 8-bit Data Input
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                DIB => m_p2_data_in,            -- Port B 8-bit Data Input
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                DIPA => m_p1_parity_in,  -- Port A 1-bit parity Input
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                DIPB => m_p2_parity_in,  -- Port-B 1-bit parity Input
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                ENA => m_p1_en,         -- Port A RAM Enable Input
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                ENB => m_p2_en,         -- PortB RAM Enable Input
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                SSRA => m_p1_ssr,        -- Port A Synchronous Set/Reset Input
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                SSRB => m_p2_ssr,        -- Port B Synchronous Set/Reset Input
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                WEA => m_p1_we,         -- Port A Write Enable Input
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                WEB => m_p2_we           -- Port B Write Enable Input
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        );
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end arch;
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